diff --git a/verilog/dv/gpio_test/gpio_test_tb.v b/verilog/dv/gpio_test/gpio_test_tb.v
index c27fda7..522ef0b 100644
--- a/verilog/dv/gpio_test/gpio_test_tb.v
+++ b/verilog/dv/gpio_test/gpio_test_tb.v
@@ -32,7 +32,10 @@
     	wire [37:0] mprj_io;
 	wire mprj_io_22;
 
-	assign mprj_io_0 = mprj_io[22];
+	reg gpio_clk;
+	assign gpio_clk = mprj_io[17];
+
+	assign mprj_io_22 = mprj_io[22];
 	// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
 
 	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
@@ -52,6 +55,10 @@
 		$dumpfile("gpio_test.vcd");
 		$dumpvars(0, gpio_test_tb);
 		
+		//mprj_io[15] = 1;
+		//mprj_io[21] = 1;
+		//mprj_io[17] = 1;
+
 		/*
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
 		repeat (25) begin
@@ -69,29 +76,25 @@
 		*/
 	end
 
+
+	always  #5 assign gpio_clk = !gpio_clk;
+
 	initial begin
-	    // Observe Output pins [7:0]
-	    wait(mprj_io_0 == 8'h01);
-	    wait(mprj_io_0 == 8'h02);
-	    wait(mprj_io_0 == 8'h03);
-    	    wait(mprj_io_0 == 8'h04);
-	    wait(mprj_io_0 == 8'h05);
-            wait(mprj_io_0 == 8'h06);
-	    wait(mprj_io_0 == 8'h07);
-            wait(mprj_io_0 == 8'h08);
-	    wait(mprj_io_0 == 8'h09);
-            wait(mprj_io_0 == 8'h0A);   
-	    wait(mprj_io_0 == 8'hFF);
-	    wait(mprj_io_0 == 8'h00);
+	    // Observe Output pins [22]
+	    //wait(mprj_io_22 == 8'h00);
 		
+		/*
 		`ifdef GL
 	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
 		`else
 		    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
 		`endif
-	    $finish;
+		*/
+	    //$finish;
 	end
 
+
+
 	initial begin
 		RSTB <= 1'b0;
 		CSB  <= 1'b1;		// Force CSB high
@@ -117,7 +120,7 @@
 	end
 
 	always @(mprj_io) begin
-		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+		#1 $display("MPRJ-IO state = %b ", mprj_io[22]);
 	end
 
 	wire flash_csb;
diff --git a/verilog/rtl/openram_testchip_gpio_tb.v b/verilog/rtl/openram_testchip_gpio_tb.v
index 98d6917..d8f0116 100644
--- a/verilog/rtl/openram_testchip_gpio_tb.v
+++ b/verilog/rtl/openram_testchip_gpio_tb.v
@@ -20,36 +20,27 @@
 
 module test_chip_tb;
 
-  reg          reset;
-  reg          in_select;
-  reg          la_clk;
+  reg          resetn;
+  reg          clk;
   reg          la_in_load; 
   reg          la_sram_load;
   reg  [`TOTAL_SIZE-1:0] la_data_in;
-  reg          gpio_clk;
   reg          gpio_in;
   reg          gpio_scan;
   reg          gpio_sram_load;
-  
-  reg sram_clk;
+  reg          global_csr;
  
-  wire [`ADDR_SIZE-1:0] left_addr0;
-  wire [`DATA_SIZE-1:0] left_din0;
-  wire 		 left_web0;
-  wire [`WMASK_SIZE-1:0] left_wmask0;
-  wire [`ADDR_SIZE-1:0]  left_addr1;
-  wire [`DATA_SIZE-1:0]  left_din1;
-  wire 		  left_web1;
-  wire [`WMASK_SIZE-1:0] left_wmask1;
+  wire [`ADDR_SIZE-1:0] addr0;
+  wire [`DATA_SIZE-1:0] din0;
+  wire 		 web0;
+  wire [`WMASK_SIZE-1:0] wmask0;
+  wire [`ADDR_SIZE-1:0]  addr1;
+  wire [`DATA_SIZE-1:0]  din1;
+  wire 		  web1;
+  wire [`WMASK_SIZE-1:0] wmask1;
   // One CSB for each SRAM
-  wire [`MAX_CHIPS-1:0]  left_csb0;
-  wire [`MAX_CHIPS-1:0]  left_csb1;
-
-  wire [`ADDR_SIZE-1:0]  right_addr0;
-  wire [`DATA_SIZE-1:0] right_din0;
-  wire 		 right_web0;
-  wire [`WMASK_SIZE-1:0] right_wmask0;
-  wire [`MAX_CHIPS-1:0]  right_csb0;  
+  wire [`MAX_CHIPS-1:0]  csb0;
+  wire [`MAX_CHIPS-1:0]  csb1;
 
   wire [`DATA_SIZE-1:0] sram0_data0;
   wire [`DATA_SIZE-1:0] sram0_data1;
@@ -87,16 +78,15 @@
 
   wire [`TOTAL_SIZE-1:0] la_data_out;
 openram_testchip CONTROL_LOGIC(
-    .reset(reset),
-    .in_select(in_select),
-    .la_clk(la_clk),
+    .resetn(resetn),
+    .clk(clk),
     .la_in_load(la_in_load),
     .la_data_in(la_data_in),
     .la_sram_load(la_sram_load),
-    .gpio_clk(gpio_clk),
     .gpio_in(gpio_in),
     .gpio_scan(gpio_scan),
     .gpio_sram_load(gpio_sram_load),
+    .global_csr(global_csr),
     .sram0_data0(sram0_data0),
     .sram0_data1(sram0_data1),
     .sram1_data0(sram1_data0),
@@ -129,21 +119,16 @@
     .sram14_data1(sram14_data1),
     .sram15_data0(sram15_data0),
     .sram15_data1(sram15_data1),
-    .left_addr0(left_addr0),
-    .left_din0(left_din0),
-    .left_web0(left_web0),
-    .left_wmask0(left_wmask0),
-    .left_addr1(left_addr1),
-    .left_din1(left_din1),
-    .left_web1(left_web1),
-    .left_wmask1(left_wmask1),
-    .left_csb0(left_csb0),
-    .left_csb1(left_csb1),
-    .right_addr0(right_addr0),
-    .right_din0(right_din0),
-    .right_web0(right_web0),
-    .right_wmask0(right_wmask0),
-    .right_csb0(right_csb0),
+    .addr0(addr0),
+    .din0(din0),
+    .web0(web0),
+    .wmask0(wmask0),
+    .addr1(addr1),
+    .din1(din1),
+    .web1(web1),
+    .wmask1(wmask1),
+    .csb0(csb0),
+    .csb1(csb1),
     .la_data_out(la_data_out),
     .gpio_out(gpio_out)
 );
@@ -154,16 +139,16 @@
       .vccd1(vccd1),
       .vssd1(vssd1), 
       `endif
-      .clk0   (sram_clk),
-      .csb0   (left_csb0[0]),
-      .web0   (left_web0),
-      .wmask0 (left_wmask0[0]),
-      .addr0  (left_addr0[9:0]),
-      .din0   (left_din0[7:0]),
+      .clk0   (clk),
+      .csb0   (csb0[0]),
+      .web0   (web0),
+      .wmask0 (wmask0[0]),
+      .addr0  (addr0[9:0]),
+      .din0   (din0[7:0]),
       .dout0  (sram0_data0[7:0]),
-      .clk1   (sram_clk),
-      .csb1   (left_csb1[0]),
-      .addr1  (left_addr1[9:0]),
+      .clk1   (clk),
+      .csb1   (csb1[0]),
+      .addr1  (addr1[9:0]),
       .dout1  (sram0_data1[7:0])
       );
 assign sram0_data0[`DATA_SIZE-1:8] = 0;
@@ -175,16 +160,16 @@
       .vccd1(vccd1),
       .vssd1(vssd1), 
       `endif
-      .clk0   (sram_clk),
-      .csb0   (left_csb0[1]),
-      .web0   (left_web0),
-      .wmask0 (left_wmask0),
-      .addr0  (left_addr0[7:0]),
-      .din0   (left_din0),
+      .clk0   (clk),
+      .csb0   (csb0[1]),
+      .web0   (web0),
+      .wmask0 (wmask0),
+      .addr0  (addr0[7:0]),
+      .din0   (din0),
       .dout0  (sram1_data0),
-      .clk1   (sram_clk),
-      .csb1   (left_csb1[1]),
-      .addr1  (left_addr1[7:0]),
+      .clk1   (clk),
+      .csb1   (csb1[1]),
+      .addr1  (addr1[7:0]),
       .dout1  (sram1_data1)
       );
    
@@ -194,16 +179,16 @@
       .vccd1(vccd1),
       .vssd1(vssd1), 
       `endif
-      .clk0   (sram_clk),
-      .csb0   (left_csb0[2]),
-      .web0   (left_web0),
-      .wmask0 (left_wmask0),
-      .addr0  (left_addr0[8:0]),
-      .din0   (left_din0),
+      .clk0   (clk),
+      .csb0   (csb0[2]),
+      .web0   (web0),
+      .wmask0 (wmask0),
+      .addr0  (addr0[8:0]),
+      .din0   (din0),
       .dout0  (sram2_data0),
-      .clk1   (sram_clk),
-      .csb1   (left_csb1[2]),
-      .addr1  (left_addr1[8:0]),
+      .clk1   (clk),
+      .csb1   (csb1[2]),
+      .addr1  (addr1[8:0]),
       .dout1  (sram2_data1)
       );
 
@@ -213,16 +198,16 @@
       .vccd1(vccd1),
       .vssd1(vssd1), 
       `endif
-      .clk0   (sram_clk),
-      .csb0   (left_csb0[3]),
-      .web0   (left_web0),
-      .wmask0 (left_wmask0),
-      .addr0  (left_addr0[9:0]),
-      .din0   (left_din0),
+      .clk0   (clk),
+      .csb0   (csb0[3]),
+      .web0   (web0),
+      .wmask0 (wmask0),
+      .addr0  (addr0[9:0]),
+      .din0   (din0),
       .dout0  (sram3_data0),
-      .clk1   (sram_clk),
-      .csb1   (left_csb1[3]),
-      .addr1  (left_addr1[9:0]),
+      .clk1   (clk),
+      .csb1   (csb1[3]),
+      .addr1  (addr1[9:0]),
       .dout1  (sram3_data1)
       );
    
@@ -232,16 +217,16 @@
       .vccd1(vccd1),
       .vssd1(vssd1), 
       `endif
-      .clk0   (sram_clk),
-      .csb0   (left_csb0[4]),
-      .web0   (left_web0),
-      .wmask0 (left_wmask0),
-      .addr0  (left_addr0[10:0]),
-      .din0   (left_din0),
+      .clk0   (clk),
+      .csb0   (csb0[4]),
+      .web0   (web0),
+      .wmask0 (wmask0),
+      .addr0  (addr0[10:0]),
+      .din0   (din0),
       .dout0  (sram4_data0),
-      .clk1   (sram_clk),
-      .csb1   (left_csb1[4]),
-      .addr1  (left_addr1[10:0]),
+      .clk1   (clk),
+      .csb1   (csb1[4]),
+      .addr1  (addr1[10:0]),
       .dout1  (sram4_data1)
       );
 
@@ -252,14 +237,14 @@
 //       .vccd1(vccd1),
 //       .vssd1(vssd1), 
 //       `endif
-//       .clk0   (sram_clk),
+//       .clk0   (clk),
 //       .csb0   (csb0[6]),
 //       .web0   (web0),
 //       .wmask0 (wmask0),
 //       .addr0  (addr0),
 //       .din0   (din0),
 //       .dout0  (sram6_data0),
-//       .clk1   (sram_clk),
+//       .clk1   (clk),
 //       .csb1   (csb1[6]),
 //       .addr1  (addr1),
 //       .dout1  (sram6_data1)
@@ -274,12 +259,12 @@
       .vccd1(vccd1),
       .vssd1(vssd1), 
       `endif
-      .clk0   (sram_clk),
-      .csb0   (right_csb0[8]),
-      .web0   (right_web0),
-      .wmask0 (right_wmask0),
-      .addr0  (right_addr0[7:0]),
-      .din0   (right_din0),
+      .clk0   (clk),
+      .csb0   (csb0[8]),
+      .web0   (web0),
+      .wmask0 (wmask0),
+      .addr0  (addr0[7:0]),
+      .din0   (din0),
       .dout0  (sram8_data0)
      );
 assign sram8_data1 = 0;
@@ -290,12 +275,12 @@
       .vccd1(vccd1),
       .vssd1(vssd1), 
       `endif
-      .clk0   (sram_clk),
-      .csb0   (right_csb0[9]),
-      .web0   (right_web0),
-      .wmask0 (right_wmask0),
-      .addr0  (right_addr0[8:0]),
-      .din0   (right_din0),
+      .clk0   (clk),
+      .csb0   (csb0[9]),
+      .web0   (web0),
+      .wmask0 (wmask0),
+      .addr0  (addr0[8:0]),
+      .din0   (din0),
       .dout0  (sram9_data0)
      );
 assign sram9_data1 = 0;
@@ -306,12 +291,12 @@
       .vccd1(vccd1),
       .vssd1(vssd1), 
       `endif
-      .clk0   (sram_clk),
-      .csb0   (right_csb0[10]),
-      .web0   (right_web0),
-      .wmask0 (right_wmask0),
-      .addr0  (right_addr0[9:0]),
-      .din0   (right_din0),
+      .clk0   (clk),
+      .csb0   (csb0[10]),
+      .web0   (web0),
+      .wmask0 (wmask0),
+      .addr0  (addr0[9:0]),
+      .din0   (din0),
       .dout0  (sram10_data0)
      );
 assign sram10_data1 = 0;
@@ -323,12 +308,12 @@
       .vccd1(vccd1),
       .vssd1(vssd1), 
       `endif
-      .clk0   (sram_clk),
-      .csb0   (right_csb0[11]),
-      .web0   (right_web0),
-      .wmask0 ({4'd0, right_wmask0}),
-      .addr0  (right_addr0[8:0]),
-      .din0   ({right_din0[31:16], 32'd0, right_din0[15:0]}),
+      .clk0   (clk),
+      .csb0   (csb0[11]),
+      .web0   (web0),
+      .wmask0 ({4'd0, wmask0}),
+      .addr0  (addr0[8:0]),
+      .din0   ({din0[31:16], 32'd0, din0[15:0]}),
       .dout0  (temp_sram11_data0)
      );
 
@@ -343,20 +328,18 @@
 initial begin
   $dumpfile("testchip_tb.vcd");
   $dumpvars(0, test_chip_tb);
-  gpio_clk = 1;
-  la_clk = 0;
   la_in_load = 0;
   la_sram_load = 0;
   la_data_in = 0;
-  sram_clk = 0;
-  reset = 0;
+  resetn = 1;
+  global_csr = 1;
+  clk = 1;
   
   //Testing 32B Dual Port Memories
   for(i = 0; i < 5; i = i + 1) begin
     sel = i;
       
     //Write 1 to addr1 using GPIO Pins
-    in_select = 1;
     gpio_scan = 1;
     gpio_sram_load = 0;
     in_data = {sel, 16'd1, 32'd1, 1'b0, 1'b0, 4'd15, 16'd0, 32'd0, 1'b1, 1'b1, 4'd0};
@@ -367,12 +350,12 @@
     end
     
     gpio_scan = 0;
+    global_csr = 0;
+    #10;
+    global_csr = 1;
     gpio_sram_load = 1;
-    sram_clk = 1;
-    #5;
-    sram_clk = 0;
-    #5;
-    
+    #10;
+      
     //Write 2 to addr2 using GPIO Pins
     gpio_scan = 1;
     gpio_sram_load = 0;
@@ -384,12 +367,13 @@
     end
 
     gpio_scan = 0;
+    global_csr = 0;
+    #10;
+    global_csr = 1;
     gpio_sram_load = 1;
-    sram_clk = 1;
-    #5;
-    sram_clk = 0;
-    #5;     
+    #10;     
     
+    #10;
     //Read addr1 and addr2
     gpio_scan = 1;
     gpio_sram_load = 0;
@@ -401,13 +385,14 @@
     end
 
     gpio_scan = 0;
-    gpio_sram_load = 1;
-    sram_clk = 1;
-    #5;
-    sram_clk = 0;
-    #5;  
-      
+    global_csr = 0;
     #10;
+    global_csr = 1;
+    gpio_sram_load = 1;
+    #10;
+    
+    #10
+    gpio_sram_load = 0;
     gpio_scan = 1;
     for(j = 0; j < 112; j = j + 1) begin
       out_data[111 - j] = gpio_out;
@@ -422,7 +407,6 @@
     sel = i;
       
     //Write 1 to addr1 using GPIO Pins
-    in_select = 1;
     gpio_scan = 1;
     gpio_sram_load = 0;
     in_data = {sel, 16'd1, 32'd1, 1'b0, 1'b0, 4'd15, 16'd0, 32'd0, 1'b0, 1'b0, 4'd0};
@@ -433,11 +417,11 @@
     end
     
     gpio_scan = 0;
+    global_csr = 0;
+    #10;
+    global_csr = 1;
     gpio_sram_load = 1;
-    sram_clk = 1;
-    #5;
-    sram_clk = 0;
-    #5;
+    #10;  
     
     //Read addr1
     gpio_scan = 1;
@@ -450,13 +434,14 @@
     end
 
     gpio_scan = 0;
+    global_csr = 0;
+    #10;
+    global_csr = 1;
     gpio_sram_load = 1;
-    sram_clk = 1;
-    #5;
-    sram_clk = 0;
-    #5;  
+    #10;    
       
     #10;
+    gpio_sram_load = 0;
     gpio_scan = 1;
     for(j = 0; j < 112; j = j + 1) begin
       out_data[111 - j] = gpio_out;
@@ -470,7 +455,6 @@
   sel = 11;
       
   //Write 1 to addr1 using GPIO Pins
-  in_select = 1;
   gpio_scan = 1;
   gpio_sram_load = 0;
   in_data = {sel, 16'd1, 32'd1, 1'b0, 1'b0, 4'd15, 16'd0, 32'd0, 1'b0, 1'b0, 4'd0};
@@ -481,11 +465,11 @@
   end
   
   gpio_scan = 0;
+  global_csr = 0;
+  #10;
+  global_csr = 1;
   gpio_sram_load = 1;
-  sram_clk = 1;
-  #5;
-  sram_clk = 0;
-  #5;
+  #10;  
   
   //Read addr1
   gpio_scan = 1;
@@ -498,13 +482,14 @@
   end
 
   gpio_scan = 0;
+  global_csr = 0;
+  #10;
+  global_csr = 1;
   gpio_sram_load = 1;
-  sram_clk = 1;
-  #5;
-  sram_clk = 0;
-  #5;  
+  #10;    
     
   #10;
+  gpio_sram_load = 0;
   gpio_scan = 1;
   for(j = 0; j < 112; j = j + 1) begin
     out_data[111 - j] = gpio_out;
@@ -520,5 +505,5 @@
 end
 
 always 
-    #5 gpio_clk = !gpio_clk;
+    #5 clk = !clk;
 endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 9e1fbee..90c187a 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -504,10 +504,10 @@
       end
    end
 
-   wire [`DATA_SIZE-1:0] sram8_dout1 = 0;
-   wire [`DATA_SIZE-1:0] sram9_dout1 = 0;
-   wire [`DATA_SIZE-1:0] sram10_dout1 = 0;
-   wire [`DATA_SIZE-1:0] sram11_dout1 = 0;
+   wire [`DATA_SIZE-1:0] sram8_data1 = 0;
+   wire [`DATA_SIZE-1:0] sram9_data1 = 0;
+   wire [`DATA_SIZE-1:0] sram10_data1 = 0;
+   wire [`DATA_SIZE-1:0] sram11_data1 = 0;
 
    wire [`DATA_SIZE-1:0] sram5_data0 = 0;
    wire [`DATA_SIZE-1:0] sram5_data1 = 0;