diff --git a/lef/sky130_sram_1kbyte_1rw1r_8x1024_8.lef b/lef/sky130_sram_1kbyte_1rw1r_8x1024_8.lef
index cf3d414..455fe40 100644
--- a/lef/sky130_sram_1kbyte_1rw1r_8x1024_8.lef
+++ b/lef/sky130_sram_1kbyte_1rw1r_8x1024_8.lef
@@ -240,13 +240,13 @@
          RECT  454.24 395.76 455.3 396.14 ;
       END
    END clk1
-   PIN wmask0[0]
+   PIN wmask0
       DIRECTION INPUT ;
       PORT
          LAYER met4 ;
          RECT  82.28 0.0 82.66 1.06 ;
       END
-   END wmask0[0]
+   END wmask0
    PIN dout0[0]
       DIRECTION OUTPUT ;
       PORT
diff --git a/verilog/rtl/sky130_sram_1kbyte_1rw1r_8x1024_8.v b/verilog/rtl/sky130_sram_1kbyte_1rw1r_8x1024_8.v
index ee2b1d6..15a1450 100644
--- a/verilog/rtl/sky130_sram_1kbyte_1rw1r_8x1024_8.v
+++ b/verilog/rtl/sky130_sram_1kbyte_1rw1r_8x1024_8.v
@@ -30,7 +30,7 @@
   input  clk0; // clock
   input   csb0; // active low chip select
   input  web0; // active low write control
-  input [NUM_WMASKS-1:0]   wmask0; // write mask
+  input wmask0; // write mask
   input [ADDR_WIDTH-1:0]  addr0;
   input [DATA_WIDTH-1:0]  din0;
   output [DATA_WIDTH-1:0] dout0;
@@ -41,7 +41,7 @@
 
   reg  csb0_reg;
   reg  web0_reg;
-  reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg wmask0_reg;
   reg [ADDR_WIDTH-1:0]  addr0_reg;
   reg [DATA_WIDTH-1:0]  din0_reg;
   reg [DATA_WIDTH-1:0]  dout0;
@@ -84,7 +84,7 @@
   always @ (negedge clk0)
   begin : MEM_WRITE0
     if ( !csb0_reg && !web0_reg ) begin
-        if (wmask0_reg[0])
+        if (wmask0_reg)
                 mem[addr0_reg][7:0] = din0_reg[7:0];
     end
   end