)]}'
{
  "commit": "cb196fa4fed3b4dafcb4e6bfde5318a489bc5028",
  "tree": "af7050d00ab9731a26186653ba9706192e9ad89b",
  "parents": [
    "954cb248a178a3c2a1548b5f81522e8ca4ad319a"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 17:05:28 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 17:05:28 2021 -0700"
  },
  "message": "Works for SRAM0\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e4322c62e0a5d8083c99484c63f2564522ba5dda",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip_tb.v",
      "new_id": "d39a2d2e801990bd19e096c20ef64ce823990154",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip_tb.v"
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}