commit c9fb6b0ac6e82f9d0e3a4da4035041653b576d2b
author mrg <mrg@ucsc.edu> Fri Jun 18 13:59:55 2021 -0700
committer mrg <mrg@ucsc.edu> Fri Jun 18 13:59:55 2021 -0700
tree acac87a2dec87824628c70eb112447959e2b2722
parent dfe137daf8e6e91ee34a15be5fa1695ef6ffcd0c

Make LA reset and cs active high for reset

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 8144416..431b187 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -123,7 +123,7 @@
 
    // global csb is low with either GPIO or LA csb
    // la_global_cs is low because default LA values are 0
-   wire global_csb = gpio_global_csb & la_global_cs;
+   wire global_csb = gpio_global_csb & ~la_global_cs;
    // rstn is low with either GPIO or LA reset
    // la_reset is not active low because default LA values are 0
    wire rstn = gpio_resetn & ~la_reset;