)]}'
{
  "commit": "c52702bcf560bd63a9bdcd1298915491ce4cb924",
  "tree": "d658d394c0ab4b54d58d355d3509d932d0ba2ca9",
  "parents": [
    "ff1d0fc3264d3f0ee530b30c30dcb03f3fa2c4ea"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 16:58:53 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 16:58:53 2021 -0700"
  },
  "message": "Fixed read_data bit width\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "279ec49765b5e2f5a620d94b317989d7424c2b95",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "2f1b9303dab6b54a43d3f66d393073b5d61fed9f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
    }
  ]
}