)]}'
{
  "commit": "b76334ad0533b8cd4b05b4a5dc2348f4b261da93",
  "tree": "f19897107816d57601bf4584a7f9d4006935798c",
  "parents": [
    "da4b9cfb72fa2e044c64a6777ed8b9af138cc987"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon May 17 19:17:59 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon May 17 19:17:59 2021 -0700"
  },
  "message": "Modified SRAM read logic\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ce3a07236386184efa5920e1703b1b20e67188f6",
      "old_mode": 33188,
      "old_path": "verilog/rtl/testchip/control_logic.v",
      "new_id": "c7719e35d6f9c24979d58ffd955a49170fd27a2d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/testchip/control_logic.v"
    }
  ]
}