)]}'
{
  "commit": "b40bbc7f0ae8cb88f533451e97b7e5c926211d1f",
  "tree": "0d89a1e6f9df2d3669ac0be0cd8f5ea46d51033d",
  "parents": [
    "a976e9e05f22843896842f196a9ec56fdecf35ac"
  ],
  "author": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Sun Jun 13 13:54:57 2021 -0700"
  },
  "committer": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Sun Jun 13 13:54:57 2021 -0700"
  },
  "message": "Update for max of 16 SRAMs\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "33fa3ec89e3a2aa9cdfcbdaba7e16a0a2876ae5e",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "ee6d6c6ee99ffaa74810fcf1ec6073ff8b3c871b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
    }
  ]
}