)]}'
{
  "commit": "af01516d9ad272c99ee91001710fa1411d1eeee9",
  "tree": "6d92ba0783d8003a4986b4c1e06d44a78cab768b",
  "parents": [
    "37e8d43a515cd3f5e5caa5f000a514012850e381"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Wed Jun 16 09:01:42 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Wed Jun 16 09:01:42 2021 -0700"
  },
  "message": "Working simulation over GPIO interface\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "98d69175f4c127a3b15c51c775673dfa44ff79e3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip_gpio_tb.v"
    }
  ]
}