)]}'
{
  "commit": "a976e9e05f22843896842f196a9ec56fdecf35ac",
  "tree": "cbccb49d312d15d6075737dde665363ca8313c56",
  "parents": [
    "737be464725f7e54f37f5737e1a62d5e5a261ffc"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 22:50:42 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 22:50:42 2021 -0700"
  },
  "message": "Sent sram_clk to each SRAM from within Control module\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "db1b1e5620d3f4b4f7a650328a172941735ae54b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "33fa3ec89e3a2aa9cdfcbdaba7e16a0a2876ae5e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
    },
    {
      "type": "modify",
      "old_id": "a6ce1d4a2a19d22680e7624fff74309b6d09b43d",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip_tb.v",
      "new_id": "4b43c1d534da8695d0de76bb241d5ab8a8578353",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip_tb.v"
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}