)]}'
{
  "commit": "a0c12abcb1b30755fc9e5fec8230eab0ebc4aa8b",
  "tree": "f4d6f817aa879d7c51325b13888d90ba1985929d",
  "parents": [
    "f9a9f3a3e0232ab12cc0b118665d434435d11535"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat May 08 22:44:34 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat May 08 22:44:34 2021 -0700"
  },
  "message": "Wrote all connections, set packet bits and confirm sensitivity lists\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "21233a86c5bc5efc01e8c507279ca314855f6f53",
      "old_mode": 33188,
      "old_path": "verilog/rtl/testchip/control_logic.v",
      "new_id": "030b06730f53027ca0650f1c0f7656293ffb6182",
      "new_mode": 33188,
      "new_path": "verilog/rtl/testchip/control_logic.v"
    }
  ]
}