)]}'
{
  "commit": "9e6146a4871ac4b222fe87e188a0126a45c5f120",
  "tree": "4d7fc1ea0d5b5fffab29f0ae07ba65e60cede377",
  "parents": [
    "48dbc1e9376950c1df953f6c1e5f442b91d1bbda"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon Jun 14 15:47:17 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon Jun 14 15:47:17 2021 -0700"
  },
  "message": "New port connections\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4b43c1d534da8695d0de76bb241d5ab8a8578353",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip_tb.v",
      "new_id": "c7803a0271089d541edef8cab9a8818bed5ab937",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip_tb.v"
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}