)]}'
{
  "commit": "937732718d3174d1b03e70fcb6531843209df05d",
  "tree": "fb380e523cd0a440557d48b06c035ff47e85a44a",
  "parents": [
    "71dedcda544349449f10903ab83f61c18c1c8320"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Fri Jun 18 12:07:33 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Fri Jun 18 12:07:33 2021 -0700"
  },
  "message": "Adding makefile\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "bbb93d64bd28367a834fcec5726ac49cba869561",
      "new_mode": 33188,
      "new_path": "verilog/dv/gpio_test/Makefile"
    }
  ]
}