)]}'
{
  "commit": "809053906ca98531e388b32b752ca6c9c554e20a",
  "tree": "39ee699bc07c2adbf2e927af8586ddeb1deffef2",
  "parents": [
    "988bba95b3c20fd37149c341848c8f858daffe9f"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon May 17 10:42:16 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon May 17 10:42:16 2021 -0700"
  },
  "message": "Changed paths to verilog dir\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e8164413eab6bbc8ea2d3b383853daa400e665fb",
      "old_mode": 33188,
      "old_path": "openlane/openram_testchip/config.tcl",
      "new_id": "ebb217c72d1c55492b43e0f722bf1407476cad50",
      "new_mode": 33188,
      "new_path": "openlane/openram_testchip/config.tcl"
    }
  ]
}