)]}'
{
  "commit": "7e4a9fd504b492e531174a454b03cf841d69b9fe",
  "tree": "96c989c9e325efe2a2b6281e0647314c370b6f14",
  "parents": [
    "5d91038d46b355c4e137e9f6caf23f94a8711071"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sun May 30 23:12:28 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sun May 30 23:12:28 2021 -0700"
  },
  "message": "Updated wrapper to include new memory instances\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1a32bc55739b8af02cc3b29c458ddb76375efb2b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "22d4e463159cd0b0f788a76dc26cc8fa319e0152",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}