)]}'
{
  "commit": "7a68107e5da719153a4a7c3fbcab557f0e662a0f",
  "tree": "66e70601323978a9da4cd171149ddcc873dd4b0e",
  "parents": [
    "5d991a9b00bb98cb998102b1922efddd991ac4bc"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 12:15:18 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 12:15:18 2021 -0700"
  },
  "message": "Set dout inputs to 32 bits\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b86c2f7d5287f9918b73aff44b276a9674c54a7b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "baad2da403f33fa88f2cb2a128aefef6bf235d46",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
    }
  ]
}