)]}'
{
  "commit": "73a59ccb753e4b9c6b75350a5834215ea772a13f",
  "tree": "325a86cfd288a24eee15d2f0acf8fa4cde1e91bd",
  "parents": [
    "8411fd268b91b25f5594d49b4a1af43c52cedaff"
  ],
  "author": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Fri Jun 25 14:39:40 2021 -0700"
  },
  "committer": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Fri Jun 25 14:39:40 2021 -0700"
  },
  "message": "Add gpio_clk back and it is sync with clock\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "9bb2c8200c6bb183616755451c9b9c8efefe91e5",
      "old_mode": 33188,
      "old_path": "verilog/dv/gpio_test/gpio_test_tb.v",
      "new_id": "bf043b43e4900cee29c6c82527146ace2af80560",
      "new_mode": 33188,
      "new_path": "verilog/dv/gpio_test/gpio_test_tb.v"
    }
  ]
}