)]}'
{
  "commit": "737be464725f7e54f37f5737e1a62d5e5a261ffc",
  "tree": "0331b9dfc902939f8d1e9e7600fb388b1040cb6b",
  "parents": [
    "cb196fa4fed3b4dafcb4e6bfde5318a489bc5028"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 22:34:43 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 22:34:43 2021 -0700"
  },
  "message": "Single port for gpio scanning, connected out_data to MSB\n",
  "tree_diff": [
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      "new_path": "verilog/rtl/openram_testchip.v"
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}