Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main
diff --git a/verilog/dv/gpio_test/gpio_test.c b/verilog/dv/gpio_test/gpio_test.c
index fa53b87..f071539 100644
--- a/verilog/dv/gpio_test/gpio_test.c
+++ b/verilog/dv/gpio_test/gpio_test.c
@@ -20,9 +20,9 @@
#include "verilog/dv/caravel/stub.c"
/*
- GPIO Test:
- - Configures MPRJ pin 21 as outputs
- - Observes gpio out value (in the testbench)
+ IO Test:
+ - Configures MPRJ lower 8-IO pins as outputs
+ - Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
*/
void main()
@@ -53,10 +53,17 @@
// so that the CSB line is not left floating. This allows
// all of the GPIO pins to be used for user functions.
- // Configure IO pin 21 as user output
- // Observe value in the testbench
+ // Configure Pin 22 as user output
+ // Observe counter value in the testbench
reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_INPUT_NOPULL;
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
diff --git a/verilog/dv/gpio_test/gpio_test_tb.v b/verilog/dv/gpio_test/gpio_test_tb.v
index 522ef0b..8249637 100644
--- a/verilog/dv/gpio_test/gpio_test_tb.v
+++ b/verilog/dv/gpio_test/gpio_test_tb.v
@@ -32,9 +32,6 @@
wire [37:0] mprj_io;
wire mprj_io_22;
- reg gpio_clk;
- assign gpio_clk = mprj_io[17];
-
assign mprj_io_22 = mprj_io[22];
// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
@@ -45,43 +42,127 @@
// simulation. Normally this would be a slow clock and the digital PLL
// would be the fast clock.
- always #5 clock <= (clock === 1'b0);
+ always #12.5 clock <= (clock === 1'b0);
initial begin
clock = 0;
end
+
+ reg gpio_clk;
+ reg gpio_scan;
+ reg gpio_sram_load;
+ reg global_csb;
+ reg gpio_in;
+ assign mprj_io[15] = 1;
+ assign mprj_io[16] = 1;
+ assign mprj_io[17] = gpio_clk;
+ assign mprj_io[18] = gpio_in;
+ assign mprj_io[20] = gpio_scan;
+ assign mprj_io[21] = gpio_sram_load;
+
+ always #12.5 gpio_clk = !gpio_clk;
+
initial begin
$dumpfile("gpio_test.vcd");
$dumpvars(0, gpio_test_tb);
-
- //mprj_io[15] = 1;
- //mprj_io[21] = 1;
- //mprj_io[17] = 1;
-
- /*
+
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (25) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
- $display("%c[1;31m",27);
`ifdef GL
- $display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
+ $display ("Monitor: Timeout, Test GPIO Full Chip Sim (GL) Failed");
`else
- $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
+ $display ("Monitor: Timeout, Test GPIO Full Chip Sim (RTL) Failed");
`endif
- $display("%c[0m",27);
$finish;
- */
end
- always #5 assign gpio_clk = !gpio_clk;
+ integer i, j;
+ reg [3:0] sel;
+ reg [111:0] in_data;
+ reg [111:0] out_data;
initial begin
- // Observe Output pins [22]
- //wait(mprj_io_22 == 8'h00);
+ gpio_clk = 1;
+ global_csb = 1;
+
+ //Testing 32B Dual Port Memories
+ for(i = 0; i < 5; i = i + 1) begin
+ sel = i;
+
+ //Write 1 to addr1 using GPIO Pins
+ gpio_scan = 1;
+ gpio_sram_load = 0;
+ in_data = {sel, 16'd1, 32'd1, 1'b0, 1'b0, 4'd15, 16'd0, 32'd0, 1'b1, 1'b1, 4'd0};
+
+ for(j = 0; j < 112; j = j + 1) begin
+ gpio_in = in_data[111 - j];
+ #10;
+ end
+
+ gpio_scan = 0;
+ global_csb = 0;
+ #10;
+ global_csb = 1;
+ gpio_sram_load = 1;
+ #10;
+
+ //Write 2 to addr2 using GPIO Pins
+ gpio_scan = 1;
+ gpio_sram_load = 0;
+ in_data = {sel, 16'd2, 32'd2, 1'b0, 1'b0, 4'd15, 16'd0, 32'd0, 1'b1, 1'b1, 4'd0};
+
+ for(j = 0; j < 112; j = j + 1) begin
+ gpio_in = in_data[111 - j];
+ #10;
+ end
+
+ gpio_scan = 0;
+ global_csb = 0;
+ #10;
+ global_csb = 1;
+ gpio_sram_load = 1;
+ #10;
+
+ #10;
+ //Read addr1 and addr2
+ gpio_scan = 1;
+ gpio_sram_load = 0;
+ in_data = {sel, 16'd1, 32'd0, 1'b0, 1'b1, 4'd0, 16'd2, 32'd0, 1'b0, 1'b1, 4'd0};
+
+ for(j = 0; j < 112; j = j + 1) begin
+ gpio_in = in_data[111 - j];
+ #10;
+ end
+
+ gpio_scan = 0;
+ global_csb = 0;
+ #10;
+ global_csb = 1;
+ gpio_sram_load = 1;
+ #10;
+
+ #10
+ gpio_sram_load = 0;
+ gpio_scan = 1;
+ for(j = 0; j < 112; j = j + 1) begin
+ out_data[111 - j] = mprj_io_22;
+ #10;
+ end
+ #10;
+ //`assert(out_data, {sel, 16'd1, 32'd1, 1'b0, 1'b1, 4'd0, 16'd2, 32'd2, 1'b0, 1'b1, 4'd0});
+ end
+
+ #10; $finish;
+ end
+
+ initial begin
+ // Observe Output pin 22
+ wait(mprj_io_22 == 8'h01);
/*
`ifdef GL
@@ -90,11 +171,9 @@
$display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
`endif
*/
- //$finish;
+ $finish;
end
-
-
initial begin
RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
@@ -120,7 +199,7 @@
end
always @(mprj_io) begin
- #1 $display("MPRJ-IO state = %b ", mprj_io[22]);
+ //#1 $display("MPRJ-IO state = %b ", mprj_io[22]);
end
wire flash_csb;
diff --git a/verilog/rtl/openram_testchip_gpio_tb.v b/verilog/rtl/openram_testchip_gpio_tb.v
index d8f0116..df152e8 100644
--- a/verilog/rtl/openram_testchip_gpio_tb.v
+++ b/verilog/rtl/openram_testchip_gpio_tb.v
@@ -28,7 +28,7 @@
reg gpio_in;
reg gpio_scan;
reg gpio_sram_load;
- reg global_csr;
+ reg global_csb;
wire [`ADDR_SIZE-1:0] addr0;
wire [`DATA_SIZE-1:0] din0;
@@ -86,7 +86,7 @@
.gpio_in(gpio_in),
.gpio_scan(gpio_scan),
.gpio_sram_load(gpio_sram_load),
- .global_csr(global_csr),
+ .global_csb(global_csb),
.sram0_data0(sram0_data0),
.sram0_data1(sram0_data1),
.sram1_data0(sram1_data0),
@@ -332,7 +332,7 @@
la_sram_load = 0;
la_data_in = 0;
resetn = 1;
- global_csr = 1;
+ global_csb = 1;
clk = 1;
//Testing 32B Dual Port Memories
@@ -350,9 +350,9 @@
end
gpio_scan = 0;
- global_csr = 0;
+ global_csb = 0;
#10;
- global_csr = 1;
+ global_csb = 1;
gpio_sram_load = 1;
#10;
@@ -367,9 +367,9 @@
end
gpio_scan = 0;
- global_csr = 0;
+ global_csb = 0;
#10;
- global_csr = 1;
+ global_csb = 1;
gpio_sram_load = 1;
#10;
@@ -385,9 +385,9 @@
end
gpio_scan = 0;
- global_csr = 0;
+ global_csb = 0;
#10;
- global_csr = 1;
+ global_csb = 1;
gpio_sram_load = 1;
#10;
@@ -417,9 +417,9 @@
end
gpio_scan = 0;
- global_csr = 0;
+ global_csb = 0;
#10;
- global_csr = 1;
+ global_csb = 1;
gpio_sram_load = 1;
#10;
@@ -434,9 +434,9 @@
end
gpio_scan = 0;
- global_csr = 0;
+ global_csb = 0;
#10;
- global_csr = 1;
+ global_csb = 1;
gpio_sram_load = 1;
#10;
@@ -465,9 +465,9 @@
end
gpio_scan = 0;
- global_csr = 0;
+ global_csb = 0;
#10;
- global_csr = 1;
+ global_csb = 1;
gpio_sram_load = 1;
#10;
@@ -482,9 +482,9 @@
end
gpio_scan = 0;
- global_csr = 0;
+ global_csb = 0;
#10;
- global_csr = 1;
+ global_csb = 1;
gpio_sram_load = 1;
#10;
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index a958105..b87ab89 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -98,11 +98,10 @@
wire in_select = io_in[16];
wire resetn = io_in[15];
wire gpio_clk = io_in[17];
- wire gpio_sram_clk = io_in[18];
wire gpio_scan = io_in[19];
wire gpio_sram_load = io_in[20];
wire global_csb = io_in[21];
- wire gpio_in = io_in[22];
+ wire gpio_in = io_in[18];
wire la_clk = la_data_in[127];
wire la_in_load = la_data_in[125];
wire la_sram_load = la_data_in[124];
