diff --git a/gds/sram_1rw0r0w_32_1024_sky130.gds b/gds/sram_1rw0r0w_32_1024_sky130.gds
index 12809dd..a16a24b 100644
--- a/gds/sram_1rw0r0w_32_1024_sky130.gds
+++ b/gds/sram_1rw0r0w_32_1024_sky130.gds
Binary files differ
diff --git a/gds/sram_1rw0r0w_32_256_sky130.gds b/gds/sram_1rw0r0w_32_256_sky130.gds
index 517adc2..691c94b 100644
--- a/gds/sram_1rw0r0w_32_256_sky130.gds
+++ b/gds/sram_1rw0r0w_32_256_sky130.gds
Binary files differ
diff --git a/gds/sram_1rw0r0w_32_512_sky130.gds b/gds/sram_1rw0r0w_32_512_sky130.gds
index 89b5ad5..4ea2763 100644
--- a/gds/sram_1rw0r0w_32_512_sky130.gds
+++ b/gds/sram_1rw0r0w_32_512_sky130.gds
Binary files differ
diff --git a/gds/sram_1rw0r0w_64_512_sky130.gds b/gds/sram_1rw0r0w_64_512_sky130.gds
index 8183185..d516363 100644
--- a/gds/sram_1rw0r0w_64_512_sky130.gds
+++ b/gds/sram_1rw0r0w_64_512_sky130.gds
Binary files differ
diff --git a/lef/sram_1rw0r0w_32_1024_sky130.lef b/lef/sram_1rw0r0w_32_1024_sky130.lef
index eaf7652..0747d8d 100644
--- a/lef/sram_1rw0r0w_32_1024_sky130.lef
+++ b/lef/sram_1rw0r0w_32_1024_sky130.lef
@@ -359,13 +359,13 @@
          RECT  119.68 0.0 120.06 0.38 ;
       END
    END wmask0[3]
-   PIN spare_wen0[0]
+   PIN spare_wen0
       DIRECTION INPUT ;
       PORT
          LAYER met4 ;
          RECT  317.56 0.0 317.94 0.38 ;
       END
-   END spare_wen0[0]
+   END spare_wen0
    PIN dout0[0]
       DIRECTION OUTPUT ;
       PORT
diff --git a/lef/sram_1rw0r0w_32_256_sky130.lef b/lef/sram_1rw0r0w_32_256_sky130.lef
index 799258c..9db0792 100644
--- a/lef/sram_1rw0r0w_32_256_sky130.lef
+++ b/lef/sram_1rw0r0w_32_256_sky130.lef
@@ -345,13 +345,13 @@
          RECT  107.44 0.0 107.82 0.38 ;
       END
    END wmask0[3]
-   PIN spare_wen0[0]
+   PIN spare_wen0
       DIRECTION INPUT ;
       PORT
          LAYER met4 ;
          RECT  306.0 0.0 306.38 0.38 ;
       END
-   END spare_wen0[0]
+   END spare_wen0
    PIN dout0[0]
       DIRECTION OUTPUT ;
       PORT
diff --git a/lef/sram_1rw0r0w_32_512_sky130.lef b/lef/sram_1rw0r0w_32_512_sky130.lef
index d543cf1..0ca3ba1 100644
--- a/lef/sram_1rw0r0w_32_512_sky130.lef
+++ b/lef/sram_1rw0r0w_32_512_sky130.lef
@@ -352,13 +352,13 @@
          RECT  108.12 0.0 108.5 0.38 ;
       END
    END wmask0[3]
-   PIN spare_wen0[0]
+   PIN spare_wen0
       DIRECTION INPUT ;
       PORT
          LAYER met4 ;
          RECT  306.68 0.0 307.06 0.38 ;
       END
-   END spare_wen0[0]
+   END spare_wen0
    PIN dout0[0]
       DIRECTION OUTPUT ;
       PORT
diff --git a/lef/sram_1rw0r0w_64_512_sky130.lef b/lef/sram_1rw0r0w_64_512_sky130.lef
index 52b9509..d969802 100644
--- a/lef/sram_1rw0r0w_64_512_sky130.lef
+++ b/lef/sram_1rw0r0w_64_512_sky130.lef
@@ -604,13 +604,13 @@
          RECT  157.76 0.0 158.14 0.38 ;
       END
    END wmask0[7]
-   PIN spare_wen0[0]
+   PIN spare_wen0
       DIRECTION INPUT ;
       PORT
          LAYER met4 ;
          RECT  543.32 0.0 543.7 0.38 ;
       END
-   END spare_wen0[0]
+   END spare_wen0
    PIN dout0[0]
       DIRECTION OUTPUT ;
       PORT
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 4e2a110..1498604 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -53,6 +53,7 @@
 	$script_dir/../../verilog/rtl/sram_1rw0r0w_32_1024_sky130.v \
 	$script_dir/../../verilog/rtl/sram_1rw0r0w_32_256_sky130.v \
 	$script_dir/../../verilog/rtl/sram_1rw0r0w_32_512_sky130.v \
+	$script_dir/../../verilog/rtl/sram_1rw0r0w_32_512_sky130.v \
 	$script_dir/../../verilog/rtl/sram_1rw0r0w_64_512_sky130.v"
 #$script_dir/../../verilog/rtl/openram_testchip.v
 
@@ -101,7 +102,6 @@
 set ::env(RUN_KLAYOUT_XOR) 0
 
 # Spray diodes
-
 set ::env(DIODE_INSERTION_STRATEGY) 1
 # The following is because there are no std cells in the example wrapper project.
 #set ::env(SYNTH_TOP_LEVEL) 1
diff --git a/verilog/rtl/openram_defines.v b/verilog/rtl/openram_defines.v
index 67fc5f0..e7d34b1 100644
--- a/verilog/rtl/openram_defines.v
+++ b/verilog/rtl/openram_defines.v
@@ -11,11 +11,13 @@
 // packet order:
 
 // 4 chip_select
+
 // 16 addr0
 // 32 din0
 // 1 csb0
 // 1 web0
 // 4 wmask0
+
 // 16 addr1
 // 32 din1
 // 1 csb1
diff --git a/verilog/rtl/sram_1rw0r0w_32_1024_sky130.v b/verilog/rtl/sram_1rw0r0w_32_1024_sky130.v
index cabcde6..6b94771 100644
--- a/verilog/rtl/sram_1rw0r0w_32_1024_sky130.v
+++ b/verilog/rtl/sram_1rw0r0w_32_1024_sky130.v
@@ -9,11 +9,11 @@
     vssd1,
 `endif
 // Port 0: RW
-    clk0,csb0,web0,wmask0,addr0,din0,dout0
+    clk0,csb0,web0,wmask0,spare_wen0,addr0,din0,dout0
   );
 
   parameter NUM_WMASKS = 4 ;
-  parameter DATA_WIDTH = 32 ;
+  parameter DATA_WIDTH = 33 ;
   parameter ADDR_WIDTH = 10 ;
   parameter RAM_DEPTH = 1 << ADDR_WIDTH;
   // FIXME: This delay is arbitrary.
@@ -29,13 +29,15 @@
   input   csb0; // active low chip select
   input  web0; // active low write control
   input [NUM_WMASKS-1:0]   wmask0; // write mask
-  input [ADDR_WIDTH-1:0]  addr0;
+  input           spare_wen0; // spare mask
+   input [ADDR_WIDTH-1:0] addr0;
   input [DATA_WIDTH-1:0]  din0;
   output [DATA_WIDTH-1:0] dout0;
 
   reg  csb0_reg;
   reg  web0_reg;
   reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg spare_wen0_reg;
   reg [ADDR_WIDTH-1:0]  addr0_reg;
   reg [DATA_WIDTH-1:0]  din0_reg;
   reg [DATA_WIDTH-1:0]  dout0;
@@ -46,10 +48,11 @@
     csb0_reg = csb0;
     web0_reg = web0;
     wmask0_reg = wmask0;
+    spare_wen0_reg = spare_wen0;
     addr0_reg = addr0;
     din0_reg = din0;
     #(T_HOLD) dout0 = 32'bx;
-    if ( !csb0_reg && web0_reg && VERBOSE ) 
+    if ( !csb0_reg && web0_reg && VERBOSE )
       $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
     if ( !csb0_reg && !web0_reg && VERBOSE )
       $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
@@ -70,6 +73,8 @@
                 mem[addr0_reg][23:16] = din0_reg[23:16];
         if (wmask0_reg[3])
                 mem[addr0_reg][31:24] = din0_reg[31:24];
+        if (spare_wen0_reg)
+                mem[addr0_reg][32] = din0_reg[32];
     end
   end
 
diff --git a/verilog/rtl/sram_1rw0r0w_32_256_sky130.v b/verilog/rtl/sram_1rw0r0w_32_256_sky130.v
index 8af0030..1ec035a 100644
--- a/verilog/rtl/sram_1rw0r0w_32_256_sky130.v
+++ b/verilog/rtl/sram_1rw0r0w_32_256_sky130.v
@@ -9,11 +9,11 @@
     vssd1,
 `endif
 // Port 0: RW
-    clk0,csb0,web0,wmask0,addr0,din0,dout0
+    clk0,csb0,web0,wmask0,spare_wen0,addr0,din0,dout0
   );
 
   parameter NUM_WMASKS = 4 ;
-  parameter DATA_WIDTH = 32 ;
+  parameter DATA_WIDTH = 33 ;
   parameter ADDR_WIDTH = 8 ;
   parameter RAM_DEPTH = 1 << ADDR_WIDTH;
   // FIXME: This delay is arbitrary.
@@ -29,13 +29,15 @@
   input   csb0; // active low chip select
   input  web0; // active low write control
   input [NUM_WMASKS-1:0]   wmask0; // write mask
-  input [ADDR_WIDTH-1:0]  addr0;
+  input           spare_wen0; // spare mask
+   input [ADDR_WIDTH-1:0] addr0;
   input [DATA_WIDTH-1:0]  din0;
   output [DATA_WIDTH-1:0] dout0;
 
   reg  csb0_reg;
   reg  web0_reg;
   reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg spare_wen0_reg;
   reg [ADDR_WIDTH-1:0]  addr0_reg;
   reg [DATA_WIDTH-1:0]  din0_reg;
   reg [DATA_WIDTH-1:0]  dout0;
@@ -46,10 +48,11 @@
     csb0_reg = csb0;
     web0_reg = web0;
     wmask0_reg = wmask0;
+    spare_wen0_reg = spare_wen0;
     addr0_reg = addr0;
     din0_reg = din0;
     #(T_HOLD) dout0 = 32'bx;
-    if ( !csb0_reg && web0_reg && VERBOSE ) 
+    if ( !csb0_reg && web0_reg && VERBOSE )
       $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
     if ( !csb0_reg && !web0_reg && VERBOSE )
       $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
@@ -70,6 +73,8 @@
                 mem[addr0_reg][23:16] = din0_reg[23:16];
         if (wmask0_reg[3])
                 mem[addr0_reg][31:24] = din0_reg[31:24];
+        if (spare_wen0_reg)
+                mem[addr0_reg][32] = din0_reg[32];
     end
   end
 
diff --git a/verilog/rtl/sram_1rw0r0w_32_512_sky130.v b/verilog/rtl/sram_1rw0r0w_32_512_sky130.v
index a406b4f..138331b 100644
--- a/verilog/rtl/sram_1rw0r0w_32_512_sky130.v
+++ b/verilog/rtl/sram_1rw0r0w_32_512_sky130.v
@@ -9,11 +9,11 @@
     vssd1,
 `endif
 // Port 0: RW
-    clk0,csb0,web0,wmask0,addr0,din0,dout0
+    clk0,csb0,web0,wmask0,spare_wen0,addr0,din0,dout0
   );
 
   parameter NUM_WMASKS = 4 ;
-  parameter DATA_WIDTH = 32 ;
+  parameter DATA_WIDTH = 33 ;
   parameter ADDR_WIDTH = 9 ;
   parameter RAM_DEPTH = 1 << ADDR_WIDTH;
   // FIXME: This delay is arbitrary.
@@ -29,13 +29,15 @@
   input   csb0; // active low chip select
   input  web0; // active low write control
   input [NUM_WMASKS-1:0]   wmask0; // write mask
-  input [ADDR_WIDTH-1:0]  addr0;
+  input           spare_wen0; // spare mask
+   input [ADDR_WIDTH-1:0] addr0;
   input [DATA_WIDTH-1:0]  din0;
   output [DATA_WIDTH-1:0] dout0;
 
   reg  csb0_reg;
   reg  web0_reg;
   reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg spare_wen0_reg;
   reg [ADDR_WIDTH-1:0]  addr0_reg;
   reg [DATA_WIDTH-1:0]  din0_reg;
   reg [DATA_WIDTH-1:0]  dout0;
@@ -46,10 +48,11 @@
     csb0_reg = csb0;
     web0_reg = web0;
     wmask0_reg = wmask0;
+    spare_wen0_reg = spare_wen0;
     addr0_reg = addr0;
     din0_reg = din0;
     #(T_HOLD) dout0 = 32'bx;
-    if ( !csb0_reg && web0_reg && VERBOSE ) 
+    if ( !csb0_reg && web0_reg && VERBOSE )
       $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
     if ( !csb0_reg && !web0_reg && VERBOSE )
       $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
@@ -70,6 +73,8 @@
                 mem[addr0_reg][23:16] = din0_reg[23:16];
         if (wmask0_reg[3])
                 mem[addr0_reg][31:24] = din0_reg[31:24];
+        if (spare_wen0_reg)
+                mem[addr0_reg][32] = din0_reg[32];
     end
   end
 
diff --git a/verilog/rtl/sram_1rw0r0w_64_512_sky130.v b/verilog/rtl/sram_1rw0r0w_64_512_sky130.v
index 1fabb08..d36ca41 100644
--- a/verilog/rtl/sram_1rw0r0w_64_512_sky130.v
+++ b/verilog/rtl/sram_1rw0r0w_64_512_sky130.v
@@ -9,11 +9,11 @@
     vssd1,
 `endif
 // Port 0: RW
-    clk0,csb0,web0,wmask0,addr0,din0,dout0
+    clk0,csb0,web0,wmask0,spare_wen0,addr0,din0,dout0
   );
 
   parameter NUM_WMASKS = 8 ;
-  parameter DATA_WIDTH = 64 ;
+  parameter DATA_WIDTH = 65 ;
   parameter ADDR_WIDTH = 9 ;
   parameter RAM_DEPTH = 1 << ADDR_WIDTH;
   // FIXME: This delay is arbitrary.
@@ -29,13 +29,15 @@
   input   csb0; // active low chip select
   input  web0; // active low write control
   input [NUM_WMASKS-1:0]   wmask0; // write mask
-  input [ADDR_WIDTH-1:0]  addr0;
+  input           spare_wen0; // spare mask
+   input [ADDR_WIDTH-1:0] addr0;
   input [DATA_WIDTH-1:0]  din0;
   output [DATA_WIDTH-1:0] dout0;
 
   reg  csb0_reg;
   reg  web0_reg;
   reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg spare_wen0_reg;
   reg [ADDR_WIDTH-1:0]  addr0_reg;
   reg [DATA_WIDTH-1:0]  din0_reg;
   reg [DATA_WIDTH-1:0]  dout0;
@@ -46,10 +48,11 @@
     csb0_reg = csb0;
     web0_reg = web0;
     wmask0_reg = wmask0;
+    spare_wen0_reg = spare_wen0;
     addr0_reg = addr0;
     din0_reg = din0;
     #(T_HOLD) dout0 = 64'bx;
-    if ( !csb0_reg && web0_reg && VERBOSE ) 
+    if ( !csb0_reg && web0_reg && VERBOSE )
       $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
     if ( !csb0_reg && !web0_reg && VERBOSE )
       $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
@@ -78,6 +81,8 @@
                 mem[addr0_reg][55:48] = din0_reg[55:48];
         if (wmask0_reg[7])
                 mem[addr0_reg][63:56] = din0_reg[63:56];
+        if (spare_wen0_reg)
+                mem[addr0_reg][64] = din0_reg[64];
     end
   end
 
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index a220195..b87ab89 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -339,46 +339,49 @@
 sram_1rw0r0w_32_256_sky130 SRAM8
     (
       `ifdef USE_POWER_PINS
-      .vccd1(vccd1),
-      .vssd1(vssd1),
+     .vccd1(vccd1),
+     .vssd1(vssd1),
       `endif
-      .clk0   (clk),
-      .csb0   (csb0[8]),
-      .web0   (web0),
-      .wmask0 (wmask0),
-      .addr0  (addr0),
-      .din0   (din0),
-      .dout0  (sram8_dout0)
+     .clk0   (clk),
+     .csb0   (csb0[8]),
+     .web0   (web0),
+     .wmask0 (wmask0),
+     .addr0  (addr0),
+     .din0   (din0),
+     .dout0  (sram8_dout0),
+     .spare_wen0(1'b0)
      );
 
 sram_1rw0r0w_32_512_sky130 SRAM9
     (
       `ifdef USE_POWER_PINS
-      .vccd1(vccd1),
-      .vssd1(vssd1),
+     .vccd1(vccd1),
+     .vssd1(vssd1),
       `endif
-      .clk0   (clk),
-      .csb0   (csb0[9]),
-      .web0   (web0),
-      .wmask0 (wmask0),
-      .addr0  (addr0),
-      .din0   (din0),
-      .dout0  (sram9_dout0)
+     .clk0   (clk),
+     .csb0   (csb0[9]),
+     .web0   (web0),
+     .wmask0 (wmask0),
+     .addr0  (addr0),
+     .din0   (din0),
+     .dout0  (sram9_dout0),
+     .spare_wen0(1'b0)
      );
 
 sram_1rw0r0w_32_1024_sky130 SRAM10
     (
       `ifdef USE_POWER_PINS
-      .vccd1(vccd1),
-      .vssd1(vssd1),
+     .vccd1(vccd1),
+     .vssd1(vssd1),
       `endif
-      .clk0   (clk),
-      .csb0   (csb0[10]),
-      .web0   (web0),
-      .wmask0 (wmask0),
-      .addr0  (addr0),
-      .din0   (din0),
-      .dout0  (sram10_dout0)
+     .clk0   (clk),
+     .csb0   (csb0[10]),
+     .web0   (web0),
+     .wmask0 (wmask0),
+     .addr0  (addr0),
+     .din0   (din0),
+     .dout0  (sram10_dout0),
+     .spare_wen0(1'b0)
      );
 
 
@@ -386,16 +389,17 @@
 sram_1rw0r0w_64_512_sky130 SRAM11
     (
       `ifdef USE_POWER_PINS
-      .vccd1(vccd1),
-      .vssd1(vssd1),
+     .vccd1(vccd1),
+     .vssd1(vssd1),
       `endif
-      .clk0   (clk),
-      .csb0   (csb0[11]),
-      .web0   (web0),
-      .wmask0 (wmask0),
-      .addr0  (addr0),
-      .din0   ({din0[31:16], 32'd0, din0[15:0]}),
-      .dout0  (temp_sram11_dout0)
+     .clk0   (clk),
+     .csb0   (csb0[11]),
+     .web0   (web0),
+     .wmask0 (wmask0),
+     .addr0  (addr0),
+     .din0   ({din0[31:16], 32'd0, din0[15:0]}),
+     .dout0  (temp_sram11_dout0),
+     .spare_wen0(1'b0)
      );
    assign sram11_dout0 = {temp_sram11_dout0[63:49], temp_sram11_dout0[15:0]};