)]}'
{
  "commit": "66e1cb8f6dfc3b21d28c25adcb991e6cc29213f2",
  "tree": "6f24dae98c80206b112ed4df4996f1198c653959",
  "parents": [
    "78ec13740b868751b9b5e8b339210561efb5bfdb"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 16:03:15 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 16:03:15 2021 -0700"
  },
  "message": "Writes to SRAM0 correctly\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "7edbb9369b63ed24ec8db588c73f9c0f09bec07a",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip_tb.v",
      "new_id": "6c6dcfd63a430582743183bf839379d7da0b3ef0",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip_tb.v"
    }
  ]
}