)]}'
{
  "commit": "605185e26471636c930c3eb86f6c4ccfa3fd8404",
  "tree": "834f0f38f056ce85e165a5f90062a1e6959860a9",
  "parents": [
    "b40bbc7f0ae8cb88f533451e97b7e5c926211d1f"
  ],
  "author": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Sun Jun 13 16:02:06 2021 -0700"
  },
  "committer": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Sun Jun 13 16:02:06 2021 -0700"
  },
  "message": "Update wrapper for new control.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ee6d6c6ee99ffaa74810fcf1ec6073ff8b3c871b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "53691f2b7c390d8a1f4c0009d4a4b85f9126568c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
    },
    {
      "type": "modify",
      "old_id": "53ece045056c067f83ae7671097d3b45c156bb67",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "a79c29098bdb1d8dea8445b768376d637bd660c3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}