)]}'
{
  "commit": "5b5b2e76841ec0c2b8e2e1fd6a397933eb771c36",
  "tree": "c2414541007a969849a0b6bd87178e33f1479de4",
  "parents": [
    "43fb1ea94a65e1ee7a820a859cbe3d25353eff1a"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon Jun 14 16:49:34 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon Jun 14 16:49:34 2021 -0700"
  },
  "message": "Proper variable names for csb\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f8aa54e4aee4cbca5aeaf352316fac668708e10f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "c9125b513e6623847007029aef871b80062f8212",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
    }
  ]
}