)]}'
{
  "commit": "4602c4e09af94ca95cc3211f462bc90a4dbc4072",
  "tree": "0d6121d9cadd39e7468d41417c0a7539eceeb450",
  "parents": [
    "d6591e835f90e04c4cf1075199f64e3852859e1b"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Fri Jun 11 21:58:39 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Fri Jun 11 21:58:39 2021 -0700"
  },
  "message": "Added control signal inputs and loading sram register\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "10cf7e8f7d529577935ae032ba6b837d62f9256a",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "2024248fb7eff5b848f3b2470cd4db32a3a3d221",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
    }
  ]
}