)]}'
{
  "commit": "43fb1ea94a65e1ee7a820a859cbe3d25353eff1a",
  "tree": "396949324f60f25a64d2b868f8afc51e13fb9533",
  "parents": [
    "7c79b4db02f2750c23b03ee554d26c4167f4ac47"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon Jun 14 16:48:33 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon Jun 14 16:48:33 2021 -0700"
  },
  "message": "Fixed TOTAL_SIZE\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "13e9a657843196f6bd04f98e14bfd03fe9509e42",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_defines.v",
      "new_id": "4c65502f46645229385f13302d36656f965409f2",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_defines.v"
    }
  ]
}