diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 73c6c18..9b9d644 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -27,7 +27,8 @@
 ## Source Verilog Files
 set ::env(VERILOG_FILES) "\
 	$script_dir/../../caravel/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_project_wrapper.v"
+	$script_dir/../../verilog/rtl/user_project_wrapper.v \
+	$script_dir/../../verilog/rtl/testchip/openram_testchip.v"
 
 ## Clock configurations
 set ::env(CLOCK_PORT) "user_clock2"
@@ -42,19 +43,35 @@
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
 	$script_dir/../../caravel/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v \
-	$script_dir/../../verilog/rtl/testchip/openram_testchip.v"
+	$script_dir/../../verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v"
 
 set ::env(EXTRA_LEFS) "\
 	$script_dir/../../lef/user_project_wrapper.lef \
-	$script_dir/../../lef/openram_testchip.lef \
 	$script_dir/../../lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
 
 set ::env(EXTRA_GDS_FILES) "\
 	$script_dir/../../gds/user_project_wrapper.gds \
-	$script_dir/../../gds/openram_testchip.gds \
 	$script_dir/../../lef/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
 
-set ::env(GLB_RT_MAXLAYER) 5
+#set ::env(GLB_RT_MAXLAYER) 5
 
-set ::env(FP_PDN_CHECK_NODES) 0
+#set ::env(FP_PDN_CHECK_NODES) 0
+# Power config
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(FP_HORIZONTAL_HALO) 15
+set ::env(FP_VERTICAL_HALO) 15
+set ::env(FP_PDN_VOFFSET) 5
+set ::env(FP_PDN_VPITCH) 20
+set ::env(FP_PDN_HPITCH) 50
+
+# Placement config
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(PL_TARGET_DENSITY) 0.99
+
+set ::env(MAGIC_DRC_USE_GDS) 0
+
+set ::env(RUN_CVC) 0