)]}'
{
  "commit": "38954f19171c0e7ebbd4f10224abb97cd8d8abda",
  "tree": "d1f0f19295e0cfc6df3e9dd274e14075f872fca2",
  "parents": [
    "6a1c0986bded5e5e24a2bd40aabe180aa1065528"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Fri Jun 18 08:08:19 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Fri Jun 18 08:08:19 2021 -0700"
  },
  "message": "Up to date tb model\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d8f0116cede7152910834952efad240476efd405",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip_gpio_tb.v",
      "new_id": "df152e85a917aaa28b8c837b5f625772aa796477",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip_gpio_tb.v"
    }
  ]
}