)]}'
{
  "commit": "33eab506231cba8291e4a7dd4721a1c29452ebdf",
  "tree": "21fcace310ff82ba63d026a9347611ff41313352",
  "parents": [
    "b6ecf069896b3394566e78d37abe89c6ba399b03"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sun Jun 27 11:31:47 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sun Jun 27 11:31:47 2021 -0700"
  },
  "message": "Writes correctly to SRAM 0\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "153d82dbb2b9ce99f71ec74e574d388bd4ab6a04",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test/la_test.c",
      "new_id": "d3f5f28bef7e655db23a3f5b4d67c64c00874de2",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test/la_test.c"
    }
  ]
}