commit 31eb2d306d7238f60f14d4bbf86b2f329e8dd094
author AmoghLonkar <alonkar@ucsc.edu> Tue Jun 15 08:58:12 2021 -0700
committer AmoghLonkar <alonkar@ucsc.edu> Tue Jun 15 08:58:12 2021 -0700
tree a434e88fbd1b0c0f9eb5a88d575937594e5f3ccf
parent e8af1ae7e97c8effb684c65c0781df3bd711c283

Proper address wire connection

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index ec80590..aa559a2 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -284,7 +284,7 @@
       .dout0  (sram0_dout0[7:0]),
       .clk1   (sram_clk),
       .csb1   (left_csb1[0]),
-      .addr1  (left_addr0),
+      .addr1  (left_addr1),
       .dout1  (sram0_dout1[7:0])
       );
    assign sram0_dout0[`DATA_SIZE-1:8] = 0;