)]}'
{
  "commit": "2e70f512e02e4195a2a1400189d9631aab1f64bc",
  "tree": "5eae0cfa61f251184bda78f762d1250421c9cb1f",
  "parents": [
    "fc1a77401ddeb99607204e319ca11945715f0a0d"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Thu Jun 17 17:39:24 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Thu Jun 17 17:39:24 2021 -0700"
  },
  "message": "Resolved compile errors\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "87b870dc0923fa0b08739858daa2f02eb07a028b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "7bfa7e04d9cffc35199c0e147fc3e462345ed563",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}