)]}'
{
  "commit": "16df1c4fc5698ba91a14221ec2c9ba6ce8d2bd86",
  "tree": "7b58371594cfe71366b6e10b905c4d8d3e1a2286",
  "parents": [
    "cca863573f7dec6dcb91b3fff26cd9cd201aa33e"
  ],
  "author": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Fri Jul 09 12:07:18 2021 -0700"
  },
  "committer": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Fri Jul 09 12:07:18 2021 -0700"
  },
  "message": "Assign spare din/dout signals\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6b58e090318f6cbd5aab130725e3b80da6d6ac72",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "293c834336f4f8a448fd9cf5cc72891e626dd732",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}