)]}'
{
  "commit": "15b80b21d8a106878bd9c928d91dad671caef23b",
  "tree": "39ef5a1d54bdc50e4f9482615a46603e2ed633bb",
  "parents": [
    "66e1cb8f6dfc3b21d28c25adcb991e6cc29213f2"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 16:45:56 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 16:45:56 2021 -0700"
  },
  "message": "Fixed sram clock selection\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1195e633088696d653654386b04b9d8a0c06666a",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "279ec49765b5e2f5a620d94b317989d7424c2b95",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
    }
  ]
}