diff --git a/verilog/dv/gpio_test/gpio_test.c b/verilog/dv/gpio_test/gpio_test.c
index f071539..b595303 100644
--- a/verilog/dv/gpio_test/gpio_test.c
+++ b/verilog/dv/gpio_test/gpio_test.c
@@ -27,7 +27,7 @@
 
 void main()
 {
-	/* 
+	/*
 	IO Control Registers
 	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
 	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
@@ -35,8 +35,8 @@
 	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
 	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
 	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
-	
-	 
+
+
 	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
 	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
 	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
@@ -64,9 +64,19 @@
 	reg_mprj_io_19 =  GPIO_MODE_USER_STD_INPUT_NOPULL;
 	reg_mprj_io_20 =  GPIO_MODE_USER_STD_INPUT_NOPULL;
 	reg_mprj_io_21 =  GPIO_MODE_USER_STD_INPUT_NOPULL;
+
+	// Configure LA probes as outputs from the cpu
+	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]
+	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
+	reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
+	reg_la3_oenb = reg_la3_iena = 0x00000000;    // [127:96]
+	reg_la0_data = 0x00000000;
+	reg_la1_data = 0x00000000;
+	reg_la2_data = 0x00000000;
+	reg_la3_data = 0x00000000;
+
 	/* Apply configuration */
 	reg_mprj_xfer = 1;
 	while (reg_mprj_xfer == 1);
 
 }
-
diff --git a/verilog/dv/gpio_test/gpio_test_tb.v b/verilog/dv/gpio_test/gpio_test_tb.v
index 7730d88..8c387c3 100644
--- a/verilog/dv/gpio_test/gpio_test_tb.v
+++ b/verilog/dv/gpio_test/gpio_test_tb.v
@@ -47,7 +47,7 @@
 	initial begin
 		clock = 0;
 	end
-	
+
 	reg gpio_clk;
 	reg gpio_scan;
 	reg gpio_sram_load;
@@ -63,11 +63,11 @@
 	assign mprj_io[21] = global_csb;
 
 	always #12.5 gpio_clk = !gpio_clk;
-	
+
 	initial begin
 		//$dumpfile("gpio_test.vcd");
 		//$dumpvars(0, gpio_test_tb);
-		
+
 		/*
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
 		repeat (2) begin
@@ -90,16 +90,21 @@
 	reg [111:0] out_data;
 
 	initial begin
+
+	   // Wait until after the reset
+		#170000;
+
 		$dumpfile("gpio_test.vcd");
 		$dumpvars(0, gpio_test_tb);
-		
+
+
 		gpio_clk = 1;
 		global_csb = 1;
-		
+
 		//Testing 32B Dual Port Memories
-		for(i = 0; i < 1; i = i + 1) begin
+		for(i = 0; i < 4; i = i + 1) begin
 			sel = i;
-		
+
 			//Write 1 to addr1 using GPIO Pins
 			gpio_scan = 1;
 			gpio_sram_load = 0;
@@ -116,13 +121,12 @@
 			global_csb = 1;
 			gpio_sram_load = 1;
 			#25;
-			
-			/*
+
 			//Write 2 to addr2 using GPIO Pins
 			gpio_scan = 1;
 			gpio_sram_load = 0;
 			in_data = {sel, 16'd2, 32'd2, 1'b0, 1'b0, 4'd15, 16'd0, 32'd0, 1'b1, 1'b1, 4'd0};
-			
+
 			for(j = 0; j < 112; j = j + 1) begin
 			gpio_in = in_data[111 - j];
 			#25;
@@ -133,14 +137,14 @@
 			#25;
 			global_csb = 1;
 			gpio_sram_load = 1;
-			#25;     
-			
+			#25;
+
 			#25;
 			//Read addr1 and addr2
 			gpio_scan = 1;
 			gpio_sram_load = 0;
 			in_data = {sel, 16'd1, 32'd0, 1'b0, 1'b1, 4'd0, 16'd2, 32'd0, 1'b0, 1'b1, 4'd0};
-			
+
 			for(j = 0; j < 112; j = j + 1) begin
 			gpio_in = in_data[111 - j];
 			#25;
@@ -152,7 +156,7 @@
 			global_csb = 1;
 			gpio_sram_load = 1;
 			#25;
-			
+
 			#25;
 			gpio_sram_load = 0;
 			gpio_scan = 1;
@@ -162,7 +166,6 @@
 			end
 			#25;
 			//`assert(out_data, {sel, 16'd1, 32'd1, 1'b0, 1'b1, 4'd0, 16'd2, 32'd2, 1'b0, 1'b1, 4'd0});
-			*/
 		end
 		#25; $finish;
 	end
@@ -170,7 +173,7 @@
 	initial begin
 	    // Observe Output pin 22
 	    wait(mprj_io_22 == 8'h01);
-		
+
 		/*
 		`ifdef GL
 	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");