)]}'
{
  "commit": "0c951e161605c444662a9d9ae9634863286e5cce",
  "tree": "ddf8c376b92a1596c44b403a081ed0d9b796a311",
  "parents": [
    "763d54621a5f567db102abddb9e901a6757d92e2"
  ],
  "author": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Sun Jun 13 17:02:00 2021 -0700"
  },
  "committer": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Sun Jun 13 17:02:00 2021 -0700"
  },
  "message": "Use defines in the design\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1bc29dfaf9d587ea309b5e81123a0b8d14d30016",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "d3638741561d69f22cd8fda769ad56289e9b5b20",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
    }
  ]
}