diff --git a/verilog/rtl/digital_core/filelist_rtl.f b/verilog/rtl/digital_core/filelist_rtl.f
index 6b23b18..d22f12e 100755
--- a/verilog/rtl/digital_core/filelist_rtl.f
+++ b/verilog/rtl/digital_core/filelist_rtl.f
@@ -20,6 +20,9 @@
 ../sdram_ctrl/src/core/sdrc_xfr_ctl.v 
 
 ../lib/wb_crossbar.v
+../lib/registers.v
+../lib/clk_ctl.v
+./src/glbl_cfg.sv
 ./src/digital_core.sv
 
 
diff --git a/verilog/rtl/digital_core/src/digital_core.sv b/verilog/rtl/digital_core/src/digital_core.sv
index bc5721a..44448ff 100644
--- a/verilog/rtl/digital_core/src/digital_core.sv
+++ b/verilog/rtl/digital_core/src/digital_core.sv
@@ -62,77 +62,44 @@
         parameter      SDR_BW   = 1,  // SDR Byte Width
 	parameter      WB_WIDTH = 32  // WB ADDRESS/DARA WIDTH
  ) (
-    input   logic                      clk,              // System clock
-    input   logic                      rtc_clk,          // Real-time clock
-    input   logic                      pwrup_rst_n,      // Power-Up Reset
-    input   logic                      cpu_rst_n,        // CPU Reset (Core Reset)
-    input logic                        rst_n,            // Regular Reset signal
+`ifdef USE_POWER_PINS
+    inout vdda1,	// User area 1 3.3V supply
+    inout vdda2,	// User area 2 3.3V supply
+    inout vssa1,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vccd2,	// User area 2 1.8v supply
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+`endif
+    input   logic                       clk             ,  // System clock
+    input   logic                       rtc_clk         ,  // Real-time clock
+    input   logic                       rst_n           ,  // Regular Reset signal
 
-`ifdef SCR1_DBG_EN
-    output  logic                      sys_rst_n_o,      // External System Reset output
-                                                         //   (for the processor cluster's components or
-                                                         //    external SOC (could be useful in small
-                                                         //    SCR-core-centric SOCs))
-    output  logic                      sys_rdc_qlfy_o,   // System-to-External SOC Reset Domain Crossing Qualifier
-`endif // SCR1_DBG_EN
-    // Fuses
-    input   logic [`SCR1_XLEN-1:0]     fuse_mhartid,     // Hart ID
+    input   logic                       wbd_ext_cyc_i   ,  // strobe/request
+    input   logic                       wbd_ext_stb_i   ,  // strobe/request
+    input   logic [WB_WIDTH-1:0]        wbd_ext_adr_i   ,  // address
+    input   logic                       wbd_ext_we_i    ,  // write
+    input   logic [WB_WIDTH-1:0]        wbd_ext_dat_i   ,  // data output
+    input   logic [3:0]                 wbd_ext_sel_i   ,  // byte enable
+    output  logic [WB_WIDTH-1:0]        wbd_ext_dat_o   ,  // data input
+    output  logic                       wbd_ext_ack_o   ,  // acknowlegement
+    output  logic                       wbd_ext_err_o   ,  // error
 
-`ifdef SCR1_DBG_EN
-    input   logic [31:0]               fuse_idcode,            // TAPC IDCODE
-`endif // SCR1_DBG_EN
-    // IRQ
-`ifdef SCR1_IPIC_EN
-    input   logic [SCR1_IRQ_LINES_NUM-1:0]          irq_lines,              // IRQ lines to IPIC
-`else // SCR1_IPIC_EN
-    input   logic                     ext_irq,                // External IRQ input
-`endif // SCR1_IPIC_EN
-    input   logic                     soft_irq,               // Software IRQ input
+ 
+    // Logic Analyzer Signals
+    input  logic [127:0]                la_data_in      ,
+    output logic [127:0]                la_data_out     ,
+    input  logic [127:0]                la_oenb         ,
+ 
 
-`ifdef SCR1_DBG_EN
-    // -- JTAG I/F
-    input   logic                       trst_n,
-    input   logic                       tck,
-    input   logic                       tms,
-    input   logic                       tdi,
-    output  logic                       tdo,
-    output  logic                       tdo_en,
-`endif // SCR1_DBG_EN
-    input   logic                       wbd_ext_stb_i, // strobe/request
-    input   logic [WB_WIDTH-1:0]        wbd_ext_adr_i, // address
-    input   logic                       wbd_ext_we_i,  // write
-    input   logic [WB_WIDTH-1:0]        wbd_ext_dat_i, // data output
-    input   logic [3:0]                 wbd_ext_sel_i, // byte enable
-    output  logic [WB_WIDTH-1:0]        wbd_ext_dat_o, // data input
-    output  logic                       wbd_ext_ack_o, // acknowlegement
-    output  logic                       wbd_ext_err_o,  // error
+    // IOs
+    input  logic  [37:0]                io_in           ,
+    output logic  [37:0]                io_out          ,
+    output logic  [37:0]                io_oeb          ,
 
-    /* Interface to SDRAMs */
-    output  logic                       sdr_cke,      // SDRAM CKE
-    output  logic			sdr_cs_n,     // SDRAM Chip Select
-    output  logic                       sdr_ras_n,    // SDRAM ras
-    output  logic                       sdr_cas_n,    // SDRAM cas
-    output  logic			sdr_we_n,     // SDRAM write enable
-    output  logic [SDR_BW-1:0] 	        sdr_dqm,      // SDRAM Data Mask
-    output  logic [1:0] 		sdr_ba,       // SDRAM Bank Enable
-    output  logic [12:0] 		sdr_addr,     // SDRAM Address
-    input   logic [SDR_DW-1:0] 	        pad_sdr_din,  // SDRA Data Input
-    output  logic [SDR_DW-1:0] 	        sdr_dout,     // SDRA Data output
-    output  logic [SDR_BW-1:0] 	        sdr_den_n,    // SDRAM Data Output enable
-    input                               sdram_pad_clk,// Sdram clock loop back from pad
+    output logic  [2:0]                 irq             
 
-    // SPI Master I/F
-    output logic                        spim_clk,
-    output logic                        spim_csn0,
-    output logic                        spim_csn1,
-    output logic                        spim_csn2,
-    output logic                        spim_csn3,
-    output logic       [1:0]            spim_mode,
-    input logic        [3:0]            spim_sdi, // SPI Master out
-    output logic       [3:0]            spim_sdo,  // SPI Master out
-    output logic                        spi_en_tx // SPI Pad directional control
-
-    //inout tri        [3:0]              spim_sdio // SPI Master in/out
 );
 
 //---------------------------------------------------
@@ -181,7 +148,7 @@
 //    SPI Master Wishbone Interface
 //---------------------------------------------------------------------
 logic                           wbd_sdram_stb_o ;
-logic [WB_WIDTH-1:0]            wbd_sdram_addr_o;
+logic [WB_WIDTH-1:0]            wbd_sdram_adr_o ;
 logic                           wbd_sdram_we_o  ; // 1 - Write, 0 - Read
 logic [WB_WIDTH-1:0]            wbd_sdram_dat_o ;
 logic [WB_WIDTH/8-1:0]          wbd_sdram_sel_o ; // Byte enable
@@ -194,7 +161,7 @@
 //    Global Register Wishbone Interface
 //---------------------------------------------------------------------
 logic                           wbd_glbl_stb_o; // strobe/request
-logic   [WB_WIDTH-1:0]          wbd_glbl_addr_o; // address
+logic   [WB_WIDTH-1:0]          wbd_glbl_adr_o; // address
 logic                           wbd_glbl_we_o;  // write
 logic   [WB_WIDTH-1:0]          wbd_glbl_dat_o; // data output
 logic   [3:0]                   wbd_glbl_sel_o; // byte enable
@@ -202,6 +169,19 @@
 logic   [WB_WIDTH-1:0]          wbd_glbl_dat_i; // data input
 logic                           wbd_glbl_ack_i; // acknowlegement
 logic                           wbd_glbl_err_i;  // error
+
+
+//----------------------------------------------------
+//  CPU Configuration
+//----------------------------------------------------
+logic                              cpu_rst_n     ;
+logic                              spi_rst_n     ;
+logic                              sdram_rst_n   ;
+
+logic [31:0]                       fuse_mhartid  ;
+logic [15:0]                       irq_lines     ;
+logic                              soft_irq      ;
+
 //------------------------------------------------
 // Configuration Parameter
 //------------------------------------------------
@@ -220,6 +200,50 @@
 logic [`SDR_RFSH_TIMER_W-1 : 0]    cfg_sdr_rfsh        ;
 logic [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax       ;
 
+//----------------------------------------------------------------------
+// Interface to SDRAMs 
+//--------------------------------------------------------------------------
+logic                              sdr_cke             ;  // SDRAM CKE
+logic			           sdr_cs_n            ;  // SDRAM Chip Select
+logic                              sdr_ras_n           ;  // SDRAM ras
+logic                              sdr_cas_n           ;  // SDRAM cas
+logic			           sdr_we_n            ;  // SDRAM write enable
+logic [SDR_BW-1:0] 	           sdr_dqm             ;  // SDRAM Data Mask
+logic [1:0] 		           sdr_ba              ;  // SDRAM Bank Enable
+logic [12:0] 		           sdr_addr            ;  // SDRAM Address
+logic [SDR_DW-1:0] 	           pad_sdr_din         ;  // SDRA Data Input
+logic [SDR_DW-1:0] 	           sdr_dout            ;  // SDRA Data output
+logic [SDR_BW-1:0] 	           sdr_den_n           ;  // SDRAM Data Output enable
+logic                              sdram_clk           ;  // Sdram clock loop back from pad
+logic                              pad_sdram_clk       ;  // Sdram clock loop back from pad
+
+
+assign pad_sdr_din[7:0]      =      io_in[7:0]         ;
+assign io_out     [7:0]      =      sdr_dout[7:0]      ;
+assign io_out     [20:8]     =      sdr_addr[12:0]     ;
+assign io_out     [22:21]    =      sdr_ba[1:0]        ;
+assign io_out     [23]       =      sdr_dqm[0]         ;
+assign io_out     [24]       =      sdr_we_n           ;
+assign io_out     [25]       =      sdr_cas_n          ;
+assign io_out     [26]       =      sdr_ras_n          ;
+assign io_out     [27]       =      sdr_cs_n           ;
+assign io_out     [28]       =      sdr_cke            ;
+assign io_out     [29]       =      sdram_clk          ;
+assign pad_sdram_clk         =      io_in[29]          ;
+
+assign io_oeb     [7:0]      =      sdr_den_n         ;
+assign io_oeb     [20:8]     =      {(13) {1'b0}}      ;
+assign io_oeb     [22:21]    =      {(2) {1'b0}}       ;
+assign io_oeb     [23]       =      1'b0               ;
+assign io_oeb     [24]       =      1'b0               ;
+assign io_oeb     [25]       =      1'b0               ;
+assign io_oeb     [26]       =      1'b0               ;
+assign io_oeb     [27]       =      1'b0               ;
+assign io_oeb     [28]       =      1'b0               ;
+assign io_oeb     [29]       =      1'b0               ;
+
+
+
 //-----------------------------------------------------------
 //  SPI I/F
 //  ////////////////////////////////////////////////////
@@ -231,32 +255,42 @@
 logic                          spim_sdi1               ; // SPI Master Data In[1]
 logic                          spim_sdi2               ; // SPI Master Data In[2]
 logic                          spim_sdi3               ; // SPI Master Data In[3]
+logic                          spim_clk                ;
+logic                          spim_csn                ;
+logic                          spi_en_tx               ;
 
-//`ifdef VERILATOR // Verilator has limited support for bi-di pad
-   assign  spim_sdi0 =   spim_sdi[0];
-   assign  spim_sdi1 =   spim_sdi[1];
-   assign  spim_sdi2 =   spim_sdi[2];
-   assign  spim_sdi3 =   spim_sdi[3];
+assign  spim_sdi0  =  io_in[32];
+assign  spim_sdi1  =  io_in[33];
+assign  spim_sdi2  =  io_in[34];
+assign  spim_sdi3  =  io_in[35];
+
+assign  io_out[30] =  spim_clk;
+assign  io_out[31] =  spim_csn;
+assign  io_out[32] =  spim_sdo0;
+assign  io_out[33] =  spim_sdo1;
+assign  io_out[34] =  spim_sdo2;
+assign  io_out[35] =  spim_sdo3;
    
-   assign  spim_sdo  =   {spim_sdo3,spim_sdo2,spim_sdo1,spim_sdo0};
-//`else 
-//   assign  spim_sdi0 =   spim_sdio[0];
-//   assign  spim_sdi1 =   spim_sdio[1];
-//   assign  spim_sdi2 =   spim_sdio[2];
-//   assign  spim_sdi3 =   spim_sdio[3];
-//
-//   assign  spim_sdio[0]  =  (spi_en_tx) ? spim_sdo0 : 1'bz;
-//   assign  spim_sdio[1]  =  (spi_en_tx) ? spim_sdo1 : 1'bz;
-//   assign  spim_sdio[2]  =  (spi_en_tx) ? spim_sdo2 : 1'bz;
-//   assign  spim_sdio[3]  =  (spi_en_tx) ? spim_sdo3 : 1'bz;
-//
-//`endif
+assign  io_oeb[30] =  1'b0;         // spi_clk
+assign  io_oeb[31] =  1'b0;         // spi_csn
+assign  io_oeb[32] =  !spi_en_tx;   // spi_dio0
+assign  io_oeb[33] =  !spi_en_tx;   // spi_dio1
+assign  io_oeb[34] =  !spi_en_tx;   // spi_dio2
+assign  io_oeb[35] =  !spi_en_tx;   // spi_dio3
+
+
+// for uart
+assign  io_oeb[36] =  1'b1; // Unused
+assign  io_oeb[37] =  1'b1; // Unused
+
+
+
 //------------------------------------------------------------------------------
 // RISC V Core instance
 //------------------------------------------------------------------------------
 scr1_top_wb u_riscv_top (
     // Reset
-    .pwrup_rst_n            (pwrup_rst_n               ),
+    .pwrup_rst_n            (rst_n                     ),
     .rst_n                  (rst_n                     ),
     .cpu_rst_n              (cpu_rst_n                 ),
 `ifdef SCR1_DBG_EN
@@ -276,11 +310,11 @@
 
     // IRQ
 `ifdef SCR1_IPIC_EN
-    .irq_lines              ('0                        ), // TODO - Interrupts
+    .irq_lines              (irq_lines                 ), 
 `else // SCR1_IPIC_EN
-    .ext_irq                ('0                        ), // TODO - Interrupts
+    .ext_irq                (ext_irq                   ), // TODO - Interrupts
 `endif // SCR1_IPIC_EN
-    .soft_irq               ('0                        ), // TODO - Interrupts
+    .soft_irq               (soft_irq                  ), // TODO - Interrupts
 
     // DFT
     .test_mode              (1'b0                      ),
@@ -332,7 +366,7 @@
 ) u_spi_master
 (
     .mclk                   (clk                       ),
-    .rst_n                  (rst_n                     ),
+    .rst_n                  (spi_rst_n                 ),
 
     .wbd_stb_i              (wbd_spim_stb_o            ),
     .wbd_adr_i              (wbd_spim_adr_o            ),
@@ -346,11 +380,11 @@
     .events_o               (                          ), // TODO - Need to connect to intr ?
 
     .spi_clk                (spim_clk                  ),
-    .spi_csn0               (spim_csn0                 ),
-    .spi_csn1               (spim_csn1                 ),
-    .spi_csn2               (spim_csn2                 ),
-    .spi_csn3               (spim_csn3                 ),
-    .spi_mode               (spim_mode                 ),
+    .spi_csn0               (spim_csn                  ),
+    .spi_csn1               (                          ),
+    .spi_csn2               (                          ),
+    .spi_csn3               (                          ),
+    .spi_mode               (                          ),
     .spi_sdo0               (spim_sdo0                 ),
     .spi_sdo1               (spim_sdo1                 ),
     .spi_sdo2               (spim_sdo2                 ),
@@ -373,11 +407,11 @@
     .cfg_colbits            (cfg_colbits               ),
                     
     // WB bus
-    .wb_rst_i               (rst_n                     ),
+    .wb_rst_i               (!rst_n                    ),
     .wb_clk_i               (clk                       ),
     
     .wb_stb_i               (wbd_sdram_stb_o            ),
-    .wb_addr_i              (wbd_sdram_addr_o           ),
+    .wb_addr_i              (wbd_sdram_adr_o            ),
     .wb_we_i                (wbd_sdram_we_o             ),
     .wb_dat_i               (wbd_sdram_dat_o            ),
     .wb_sel_i               (wbd_sdram_sel_o            ),
@@ -389,7 +423,7 @@
 		
     /* Interface to SDRAMs */
     .sdram_clk              (sdram_clk                 ),
-    .sdram_resetn           (sdram_resetn              ),
+    .sdram_resetn           (sdram_rst_n               ),
     .sdr_cs_n               (sdr_cs_n                  ),
     .sdr_cke                (sdr_cke                   ),
     .sdr_ras_n              (sdr_ras_n                 ),
@@ -401,7 +435,7 @@
     .pad_sdr_din            (pad_sdr_din               ), 
     .sdr_dout               (sdr_dout                  ), 
     .sdr_den_n              (sdr_den_n                 ),
-    .sdram_pad_clk          (sdram_pad_clk             ),
+    .sdram_pad_clk          (pad_sdram_clk             ),
                     
     /* Parameters */
     .sdr_init_done          (sdr_init_done             ),
@@ -427,94 +461,154 @@
 // 0x3000_0000 to 0x3000_00FF  - GLOBAL REGISTER
 //-----------------------------
 // 
-wire [3:0] wbd_riscv_imem_tar_id     = (wbd_riscv_imem_adr_i[31:28] == 4'b0000 ) ? 4'b0001 :
-                                       (wbd_riscv_imem_adr_i[31:28] == 4'b0001 ) ? 4'b0001 :
-                                       (wbd_riscv_imem_adr_i[31:28] == 4'b0010 ) ? 4'b0010 :
-                                       (wbd_riscv_imem_adr_i[31:28] == 4'b0011 ) ? 4'b0011 : 4'b0001;
+wire [3:0] wbd_riscv_imem_tar_id     = (wbd_riscv_imem_adr_i[31:16] == 16'h0000 ) ? 4'b0000 :
+                                       (wbd_riscv_imem_adr_i[31:16] == 16'h0041 ) ? 4'b0000 :
+                                       (wbd_riscv_imem_adr_i[31:16] == 16'h0048 ) ? 4'b0001 :// Todo: Temp fix for SDRAM
+                                       (wbd_riscv_imem_adr_i[31:16] == 16'h3000 ) ? 4'b0010 : 4'b0000;
 
-wire [3:0] wbd_riscv_dmem_tar_id     = (wbd_riscv_dmem_adr_i[31:28] == 4'b0000 ) ? 4'b0001 :
-                                       (wbd_riscv_dmem_adr_i[31:28] == 4'b0001 ) ? 4'b0001 :
-                                       (wbd_riscv_dmem_adr_i[31:28] == 4'b0010 ) ? 4'b0010 :
-                                       (wbd_riscv_dmem_adr_i[31:28] == 4'b0011 ) ? 4'b0011 : 4'b0001;
-
-wire [3:0] wbd_ext_tar_id            = (wbd_ext_adr_i[31:28] == 4'b0000 ) ? 4'b0001 :
-                                       (wbd_ext_adr_i[31:28] == 4'b0001 ) ? 4'b0001 :
-                                       (wbd_ext_adr_i[31:28] == 4'b0010 ) ? 4'b0010 :
-                                       (wbd_ext_adr_i[31:28] == 4'b0011 ) ? 4'b0011 : 4'b0001;
-wb_crossbar #(
-    .WB_SLAVE(3),
-    .WB_MASTER(3),
-    .D_WD(32),
-    .BE_WD(4),
-    .ADR_WD(32),
-    .TAR_WD(4)
-   ) u_wb_crossbar(
-
-    .rst_n               (rst_n               ), 
-    .clk                 (clk                 ),
+wire [3:0] wbd_riscv_dmem_tar_id     = (wbd_riscv_dmem_adr_i[31:16] == 16'h0000 ) ? 4'b0000 :
+                                       (wbd_riscv_dmem_adr_i[31:16] == 16'h0041 ) ? 4'b0000 :
+                                       (wbd_riscv_dmem_adr_i[31:16] == 16'h0048 ) ? 4'b0001 : // todo: Temp fix for SDRAM
+                                       (wbd_riscv_dmem_adr_i[31:16] == 16'h3000 ) ? 4'b0010 : 4'b0000;
 
 
-    // Master Interface Signal
-    .wbd_taddr_master    ({wbd_ext_tar_id,
-                           wbd_riscv_dmem_tar_id,
-	                   wbd_riscv_imem_tar_id}),
-    .wbd_din_master      ({wbd_ext_dat_i,
-                          wbd_riscv_dmem_dat_i,
-                          wbd_riscv_imem_dat_i}),
-    .wbd_dout_master     ({wbd_ext_dat_o,
-                          wbd_riscv_dmem_dat_o,
-                          wbd_riscv_imem_dat_o}),
-    .wbd_adr_master      ({wbd_ext_adr_i,
-                          wbd_riscv_dmem_adr_i,
-                          wbd_riscv_imem_adr_i}      ), 
-    .wbd_be_master       ({wbd_ext_sel_i,
-                          wbd_riscv_dmem_sel_i,
-                          wbd_riscv_imem_sel_i}), 
-    .wbd_we_master       ({wbd_ext_we_i,
-                          wbd_riscv_dmem_we_i,
-                          wbd_riscv_imem_we_i}), 
-    .wbd_ack_master      ({wbd_ext_ack_o,
-                          wbd_riscv_dmem_ack_o,
-                          wbd_riscv_imem_ack_o}),
-    .wbd_stb_master      ({wbd_ext_stb_i,
-                           wbd_riscv_dmem_stb_i,
-                           wbd_riscv_imem_stb_i}), 
-    .wbd_cyc_master      ({wbd_ext_stb_i,
-                          wbd_riscv_dmem_stb_i,
-	                  wbd_riscv_imem_stb_i}), 
-    .wbd_err_master      ({wbd_ext_err_o,
-                          wbd_riscv_dmem_err_o,
-                          wbd_riscv_imem_err_o}),
-    .wbd_rty_master      (                    ),
- 
-    // Slave Interface Signal
-    .wbd_din_slave       ({wbd_glbl_dat_o,
-	                  wbd_sdram_dat_o,
-                          wbd_spim_dat_o}     ), 
-    .wbd_dout_slave      ({wbd_glbl_dat_i,
-                          wbd_sdram_dat_i,
-                          wbd_spim_dat_i}     ),
-    .wbd_adr_slave       ({wbd_glbl_addr_o,
-                          wbd_sdram_addr_o,
-                          wbd_spim_adr_o}     ), 
-    .wbd_be_slave        ({wbd_glbl_sel_o,
-                          wbd_sdram_sel_o,
-                          wbd_spim_sel_o}     ), 
-    .wbd_we_slave        ({wbd_glbl_we_o,
-                          wbd_sdram_we_o,
-                          wbd_spim_we_o}      ), 
-    .wbd_ack_slave       ({wbd_glbl_ack_i,
-                          wbd_sdram_ack_i,
-                          wbd_spim_ack_i}     ),
-    .wbd_stb_slave       ({wbd_glbl_stb_o,
-                          wbd_sdram_stb_o,
-                          wbd_spim_stb_o}     ), 
-    .wbd_cyc_slave       ({wbd_glbl_cyc_o,
-                          wbd_sdram_cyc_o,
-                          wbd_spim_cyc_o}      ), 
-    .wbd_err_slave       (3'b0                ),
-    .wbd_rty_slave       (3'b0                )
-         );
+//-------------------------------------------------------------------
+// EXTERNAL MEMORY MAP
+// 0x3000_0000 to 0x3000_00FF -  GLOBAL REGISTER
+// 0x4000_0000 to 0x4FFF_FFFF -  SPI FLASH MEMORY
+// 0x5000_0000 to 0x5000_00FF -  SPI REGISTER
+// 0x6000_0000 to 0x6FFF_FFFF -  SDRAM
+//
+wire [3:0] wbd_ext_tar_id            = (wbd_ext_adr_i[31:28] == 4'b0100 ) ? 4'b0000 :
+                                       (wbd_ext_adr_i[31:28] == 4'b0101 ) ? 4'b0000 :
+                                       (wbd_ext_adr_i[31:28] == 4'b0110 ) ? 4'b0001 :
+                                       (wbd_ext_adr_i[31:28] == 4'b0011 ) ? 4'b0010 : 4'b0000;
+wb_interconnect  u_intercon (
+         .clk_i         (clk), 
+         .rst_n         (rst_n),
+         
+         // Master 0 Interface
+         .m0_wbd_dat_i  (wbd_riscv_imem_dat_i  ),
+         .m0_wbd_adr_i  (wbd_riscv_imem_adr_i  ),
+         .m0_wbd_sel_i  (wbd_riscv_imem_sel_i  ),
+         .m0_wbd_we_i   (wbd_riscv_imem_we_i   ),
+         .m0_wbd_cyc_i  (wbd_riscv_imem_stb_i  ),
+         .m0_wbd_stb_i  (wbd_riscv_imem_stb_i  ),
+         .m0_wbd_tid_i  (wbd_riscv_imem_tar_id ), // target id
+         .m0_wbd_dat_o  (wbd_riscv_imem_dat_o  ),
+         .m0_wbd_ack_o  (wbd_riscv_imem_ack_o  ),
+         .m0_wbd_err_o  (wbd_riscv_imem_err_o  ),
+         
+         // Master 1 Interface
+         .m1_wbd_dat_i  (wbd_riscv_dmem_dat_i  ),
+         .m1_wbd_adr_i  (wbd_riscv_dmem_adr_i  ),
+         .m1_wbd_sel_i  (wbd_riscv_dmem_sel_i  ),
+         .m1_wbd_we_i   (wbd_riscv_dmem_we_i   ),
+         .m1_wbd_cyc_i  (wbd_riscv_dmem_stb_i  ),
+         .m1_wbd_stb_i  (wbd_riscv_dmem_stb_i  ),
+         .m1_wbd_tid_i  (wbd_riscv_dmem_tar_id ), // target id
+         .m1_wbd_dat_o  (wbd_riscv_dmem_dat_o  ),
+         .m1_wbd_ack_o  (wbd_riscv_dmem_ack_o  ),
+         .m1_wbd_err_o  (wbd_riscv_dmem_err_o  ),
+         
+         // Master 2 Interface
+         .m2_wbd_dat_i  (wbd_ext_dat_i  ),
+         .m2_wbd_adr_i  (wbd_ext_adr_i  ),
+         .m2_wbd_sel_i  (wbd_ext_sel_i  ),
+         .m2_wbd_we_i   (wbd_ext_we_i   ),
+         .m2_wbd_cyc_i  (wbd_ext_cyc_i  ),
+         .m2_wbd_stb_i  (wbd_ext_stb_i  ),
+         .m2_wbd_tid_i  (wbd_ext_tar_id ), // target id
+         .m2_wbd_dat_o  (wbd_ext_dat_o  ),
+         .m2_wbd_ack_o  (wbd_ext_ack_o  ),
+         .m2_wbd_err_o  (wbd_ext_err_o  ),
+         
+         
+         // Slave 0 Interface
+         .s0_wbd_err_i  (1'b0           ),
+         .s0_wbd_dat_i  (wbd_spim_dat_i ),
+         .s0_wbd_ack_i  (wbd_spim_ack_i ),
+         .s0_wbd_dat_o  (wbd_spim_dat_o ),
+         .s0_wbd_adr_o  (wbd_spim_adr_o ),
+         .s0_wbd_sel_o  (wbd_spim_sel_o ),
+         .s0_wbd_we_o   (wbd_spim_we_o  ),  
+         .s0_wbd_cyc_o  (wbd_spim_cyc_o ),
+         .s0_wbd_stb_o  (wbd_spim_stb_o ),
+         
+         // Slave 1 Interface
+         .s1_wbd_err_i  (1'b0           ),
+         .s1_wbd_dat_i  (wbd_sdram_dat_i ),
+         .s1_wbd_ack_i  (wbd_sdram_ack_i ),
+         .s1_wbd_dat_o  (wbd_sdram_dat_o ),
+         .s1_wbd_adr_o  (wbd_sdram_adr_o ),
+         .s1_wbd_sel_o  (wbd_sdram_sel_o ),
+         .s1_wbd_we_o   (wbd_sdram_we_o  ),  
+         .s1_wbd_cyc_o  (wbd_sdram_cyc_o ),
+         .s1_wbd_stb_o  (wbd_sdram_stb_o ),
+         
+         // Slave 2 Interface
+         .s2_wbd_err_i  (1'b0           ),
+         .s2_wbd_dat_i  (wbd_glbl_dat_i ),
+         .s2_wbd_ack_i  (wbd_glbl_ack_i ),
+         .s2_wbd_dat_o  (wbd_glbl_dat_o ),
+         .s2_wbd_adr_o  (wbd_glbl_adr_o ),
+         .s2_wbd_sel_o  (wbd_glbl_sel_o ),
+         .s2_wbd_we_o   (wbd_glbl_we_o  ),  
+         .s2_wbd_cyc_o  (wbd_glbl_cyc_o ),
+         .s2_wbd_stb_o  (wbd_glbl_stb_o )
+	);
+
+glbl_cfg   u_glbl_cfg (
+
+       .mclk                   (clk                       ),
+       .reset_n                (rst_n                     ),
+       .device_idcode          (                          ),
+
+        // Reg Bus Interface Signal
+       .reg_cs                 (wbd_glbl_stb_o            ),
+       .reg_wr                 (wbd_glbl_we_o             ),
+       .reg_addr               (wbd_glbl_adr_o[5:2]       ),
+       .reg_wdata              (wbd_glbl_dat_o            ),
+       .reg_be                 (wbd_glbl_sel_o            ),
+
+       // Outputs
+       .reg_rdata              (wbd_glbl_dat_i            ),
+       .reg_ack                (wbd_glbl_ack_i            ),
+
+       // SDRAM Clock
+
+       .sdram_clk              (sdram_clk                 ),
+
+       // reset
+       .cpu_rst_n              (cpu_rst_n                 ),
+       .spi_rst_n              (spi_rst_n                 ),
+       .sdram_rst_n            (sdram_rst_n               ),
+
+       // Risc configuration
+       .fuse_mhartid           (fuse_mhartid              ),
+       .irq_lines              (irq_lines                 ), 
+       .soft_irq               (soft_irq                  ),
+
+       // SDRAM Config
+       .cfg_sdr_width          (cfg_sdr_width             ),
+       .cfg_colbits            (cfg_colbits               ),
+
+	/* Parameters */
+       .sdr_init_done          (sdr_init_done             ),
+       .cfg_req_depth          (cfg_req_depth             ), //how many req. buffer should hold
+       .cfg_sdr_en             (cfg_sdr_en                ),
+       .cfg_sdr_mode_reg       (cfg_sdr_mode_reg          ),
+       .cfg_sdr_tras_d         (cfg_sdr_tras_d            ),
+       .cfg_sdr_trp_d          (cfg_sdr_trp_d             ),
+       .cfg_sdr_trcd_d         (cfg_sdr_trcd_d            ),
+       .cfg_sdr_cas            (cfg_sdr_cas               ),
+       .cfg_sdr_trcar_d        (cfg_sdr_trcar_d           ),
+       .cfg_sdr_twr_d          (cfg_sdr_twr_d             ),
+       .cfg_sdr_rfsh           (cfg_sdr_rfsh              ),
+       .cfg_sdr_rfmax          (cfg_sdr_rfmax             )
+
+
+        );
 
 
 
diff --git a/verilog/rtl/lib/wb_crossbar.v b/verilog/rtl/lib/wb_crossbar.v
index ed7a5ae..76b9981 100644
--- a/verilog/rtl/lib/wb_crossbar.v
+++ b/verilog/rtl/lib/wb_crossbar.v
@@ -361,8 +361,9 @@
       for(i = 0; i < WB_MASTER; i = i + 1) begin
          if(master_busy[i] == 0) begin
             if(wbd_stb_master[i] & slave_busy[wbd_taddr_master_t[i]] == 0) begin
-               slave_busy[wbd_taddr_master_t[i]]   <= 1;
-               master_busy[i]              <= 1;
+	       $display("Locking Master Id: %d for tar_master: %d, Total Master: %x ", i, wbd_taddr_master_t[i], wbd_taddr_master);
+               slave_busy[wbd_taddr_master_t[i]]   = 1;
+               master_busy[i]              = 1;
             end
          end else if(wbd_cyc_master[i] == 0) begin
             master_busy[i]            <= 0;
@@ -380,13 +381,13 @@
                master_mx_id[n] <= wbd_taddr_master_t[n];
                slave_mx_id [wbd_taddr_master_t[n]] <= n;
                // synopsys translate_off
-               // $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]);
+                $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]);
                // synopsys translate_on
             end
          end else if(wbd_cyc_master[n] == 0) begin
 	    if(master_busy[n] == 1) begin
             // synopsys translate_off
-            //  $display("%m:%t: Releasing Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]);
+              $display("%m:%t: Releasing Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]);
             // synopsys translate_on
             end
          end
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v
index 82381d1..d4d9941 100755
--- a/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v
+++ b/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v
@@ -200,6 +200,30 @@
 // Internal Nets
    
 // SDR_REQ_GEN
+wire                    x2a_rdstart;
+wire                    x2a_wrstart;
+wire                    x2a_rdlast;
+wire                    x2a_wrlast;
+wire                    x2a_rdok;
+wire                    x2a_wrnext;
+wire                    x2b_ack;
+wire                    x2b_refresh;
+wire                    x2b_act_ok;
+wire                    x2b_rdok;
+wire                    x2b_wrok;
+wire                    b2x_idle;
+wire                    b2x_req;
+wire                    b2x_start;
+wire                    b2x_last;
+wire                    b2x_wrap;
+wire                    b2x_tras_ok;
+wire                    b2r_ack;
+wire                    b2r_arb_ok;
+wire                    r2b_req;
+wire                    r2b_start;
+wire                    r2b_last;
+wire                    r2b_wrap;
+wire                    r2b_write;
 wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
 wire [1:0] 		r2b_ba;
 wire [12:0] 		r2b_raddr;
@@ -236,6 +260,8 @@
 wire [APP_BW-1:0]        app_wr_en_n;
 wire [SDR_BW-1:0]        a2x_wren_n;
 
+wire                     r2x_idle;
+
 //wire [31:0] app_rd_data;
 wire [SDR_DW-1:0]        x2a_rddt;
 
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v
index af7b506..3d9edf6 100755
--- a/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v
+++ b/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v
@@ -267,7 +267,7 @@
       r2b_req     = 1'b0;
       next_req_st = `REQ_IDLE;
 
-      case (req_st)      // synopsys full_case parallel_case
+      case (req_st)      
 
 	`REQ_IDLE : begin
 	   r2x_idle = ~req;
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v
index cd87d26..ef01b9d 100755
--- a/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v
+++ b/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v
@@ -638,7 +638,7 @@
 	     cntr1_tc or trcar_delay or rfsh_row_cnt or ref_req or sdr_init_done
 	     or precharge_ok or sdram_mode_reg) begin 
 
-      case (mgmt_st)          // synopsys full_case parallel_case
+      case (mgmt_st)         
 
 	`MGM_POWERUP : begin
 	   mgmt_idle = 1'b0;
diff --git a/verilog/rtl/spi_master/src/spim_clkgen.sv b/verilog/rtl/spi_master/src/spim_clkgen.sv
index 022b300..2c6b236 100644
--- a/verilog/rtl/spi_master/src/spim_clkgen.sv
+++ b/verilog/rtl/spi_master/src/spim_clkgen.sv
@@ -85,31 +85,46 @@
     	      if(clk_cnt == sck_half_period) 
     	      begin
     		 spi_clk    <= 1'b0;
+    	      end // if (clk_cnt == sck_half_period)
+    	      else if(clk_cnt == cfg_sck_period) begin
+    		    spi_clk    <= 1'b1;
+    	      end 
+    	   end else begin
+    	      spi_clk    <= 1'b1;
+    	   end // else: !if(en)
+    	end // else: !if(!reset_n)
+    end // always @ (posedge clk or negedge reset_n)
+
+    // Generate Free runnng spi_fall and rise pulse
+    // after en is asserted
+    always @(posedge clk or negedge rstn) begin
+    	if(!rstn) begin
+    	   clk_cnt    <= 'h1;
+	   spi_fall   <= 1'b0;
+	   spi_rise   <= 1'b0;
+    	end // if (!reset_n)
+    	else 
+    	begin
+    	   if(clk_cnt == sck_half_period) 
+    	   begin
+	      spi_fall   <= 1'b0;
+	      spi_rise   <= 1'b1;
+    	      clk_cnt    <= clk_cnt + 1'b1;
+    	   end // if (clk_cnt == sck_half_period)
+    	   else begin
+    	      if(clk_cnt == cfg_sck_period) 
+    	      begin
 	         spi_fall   <= 1'b1;
 	         spi_rise   <= 1'b0;
-    		 clk_cnt    <= clk_cnt + 1'b1;
-    	      end // if (clk_cnt == sck_half_period)
-    	      else begin
-    		 if(clk_cnt == cfg_sck_period) 
-    		 begin
-    		    spi_clk    <= 1'b1;
-	            spi_fall   <= 1'b0;
-	            spi_rise   <= 1'b1;
-    		    clk_cnt    <= 'h1;
-    		 end // if (clk_cnt == cfg_sck_period)
-    		 else 
-    		 begin
-    		    clk_cnt    <= clk_cnt + 1'b1;
-	            spi_fall   <= 1'b0;
-	            spi_rise   <= 1'b0;
-    		  end // else: !if(clk_cnt == cfg_sck_period)
-    	      end // else: !if(clk_cnt == sck_half_period)
-    	   end // if (en)
-    	   else begin
-    	      clk_cnt    <= 'h1;
-	      spi_fall   <= 1'b0; 
-	      spi_rise   <= 1'b0;
-    	   end // else: !if(en)
+    	         clk_cnt    <= 'h1;
+    	      end // if (clk_cnt == cfg_sck_period)
+    	      else 
+    	      begin
+    	         clk_cnt    <= clk_cnt + 1'b1;
+	         spi_fall   <= 1'b0;
+	         spi_rise   <= 1'b0;
+    	       end // else: !if(clk_cnt == cfg_sck_period)
+    	   end // else: !if(clk_cnt == sck_half_period)
     	end // else: !if(!reset_n)
     end // always @ (posedge clk or negedge reset_n)
 
diff --git a/verilog/rtl/spi_master/src/spim_ctrl.sv b/verilog/rtl/spi_master/src/spim_ctrl.sv
index 20d2515..95e3dd7 100644
--- a/verilog/rtl/spi_master/src/spim_ctrl.sv
+++ b/verilog/rtl/spi_master/src/spim_ctrl.sv
@@ -51,7 +51,7 @@
 
     input  logic                    [7:0] spi_clk_div,
     input  logic                          spi_clk_div_valid,
-    output logic                    [7:0] spi_status,
+    output logic                    [8:0] spi_status,
 
 
     input  logic                          spi_req,
@@ -133,7 +133,7 @@
 
   enum logic [2:0] {DATA_NULL,DATA_EMPTY,DATA_CMD,DATA_ADDR,DATA_MODE,DATA_FIFO} ctrl_data_mux;
 
-  enum logic [4:0] {IDLE,CMD,ADDR,MODE,DUMMY,DATA_TX,DATA_RX,WAIT_EDGE} state,state_next;
+  enum logic [4:0] {IDLE,CMD,ADDR,MODE,DUMMY_RX,DUMMY_TX,DATA_TX,DATA_RX,WAIT_EDGE} state,state_next;
 
   assign en_quad = spi_qrd | spi_qwr | en_quad_int;
   
@@ -169,7 +169,6 @@
     .data_ready     (                  ),
     .clk_en_o       ( tx_clk_en        )
   );
-
   spim_rx u_rxreg
   (
     .clk            ( clk                    ),
@@ -190,7 +189,6 @@
     .clk_en_o       ( rx_clk_en              )
   );
 
-
   
   always_comb
   begin
@@ -256,7 +254,7 @@
       begin
         spi_status[0] = 1'b1;
         s_spi_mode = SPI_QUAD_RX;
-        if (spi_req)
+        if (spi_req && spi_fall)
         begin
           spi_cs       = 1'b0;
           spi_clock_en = 1'b1;
@@ -299,17 +297,19 @@
                 s_spi_mode = (spi_qrd) ? SPI_QUAD_RX : SPI_STD;
                 if(spi_dummy_rd_len != 0)
                 begin
-                  counter_tx       = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
-                  counter_tx_valid = 1'b1;
-                  spi_en_tx        = 1'b1;
+                  counter_rx       = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
+                  counter_rx_valid = 1'b1;
+                  spi_en_rx        = 1'b1;
                   ctrl_data_mux    = DATA_EMPTY;
-                  state_next       = DUMMY;
+                  spi_clock_en     = rx_clk_en;
+                  state_next       = DUMMY_RX;
                 end
                 else
                 begin
                    counter_rx       = spi_data_len;
                    counter_rx_valid = 1'b1;
                    spi_en_rx        = 1'b1;
+                   spi_clock_en     = rx_clk_en;
                    state_next       = DATA_RX;
                 end
              end
@@ -322,7 +322,8 @@
                    counter_tx_valid = 1'b1;
                    ctrl_data_mux    = DATA_EMPTY;
                    spi_en_tx        = 1'b1;
-                   state_next       = DUMMY;
+                   spi_clock_en     = tx_clk_en;
+                   state_next       = DUMMY_TX;
                 end
                 else
                 begin
@@ -331,6 +332,7 @@
                    ctrl_data_mux    = DATA_FIFO;
                    ctrl_data_valid  = 1'b0;
                    spi_en_tx        = 1'b1;
+                   spi_clock_en     = tx_clk_en;
                    state_next       = DATA_TX;
                 end
              end
@@ -350,7 +352,7 @@
         spi_clock_en = 1'b1;
 //      s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
         s_spi_mode = SPI_STD; // Command is always Standard Mode ?
-        if (tx_done)
+        if (tx_done && spi_fall)
         begin
           if (spi_addr_len != 0)
           begin
@@ -379,17 +381,19 @@
               s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
               if(spi_dummy_rd_len != 0)
               begin
-                counter_tx       = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
-                counter_tx_valid = 1'b1;
-                spi_en_tx        = 1'b1;
+                counter_rx       = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
+                counter_rx_valid = 1'b1;
+                spi_en_rx        = 1'b1;
                 ctrl_data_mux    = DATA_EMPTY;
-                state_next       = DUMMY;
+                spi_clock_en     = rx_clk_en;
+                state_next       = DUMMY_RX;
               end
               else
               begin
                 counter_rx       = spi_data_len;
                 counter_rx_valid = 1'b1;
                 spi_en_rx        = 1'b1;
+                spi_clock_en     = rx_clk_en;
                 state_next       = DATA_RX;
               end
             end
@@ -402,7 +406,8 @@
                 counter_tx_valid = 1'b1;
                 ctrl_data_mux    = DATA_EMPTY;
                 spi_en_tx        = 1'b1;
-                state_next       = DUMMY;
+                spi_clock_en     = tx_clk_en;
+                state_next       = DUMMY_TX;
               end
               else
               begin
@@ -411,6 +416,7 @@
                 ctrl_data_mux    = DATA_FIFO;
                 ctrl_data_valid  = 1'b1;
                 spi_en_tx        = 1'b1;
+                spi_clock_en     = tx_clk_en;
                 state_next       = DATA_TX;
               end
             end
@@ -436,7 +442,7 @@
         spi_clock_en  = 1'b1;
         s_spi_mode    = (en_quad) ? SPI_QUAD_TX : SPI_STD;
 
-        if (tx_done)
+        if (tx_done && spi_fall)
         begin
           if (spi_mode_cmd_enb != 0)
           begin
@@ -455,17 +461,19 @@
               s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
               if(spi_dummy_rd_len != 0)
               begin
-                counter_tx       = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
-                counter_tx_valid = 1'b1;
-                spi_en_tx        = 1'b1;
+                counter_rx       = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
+                counter_rx_valid = 1'b1;
+                spi_en_rx        = 1'b1;
                 ctrl_data_mux    = DATA_EMPTY;
-                state_next       = DUMMY;
+                spi_clock_en     = rx_clk_en;
+                state_next       = DUMMY_RX;
               end
               else
               begin
                 counter_rx       = spi_data_len;
                 counter_rx_valid = 1'b1;
                 spi_en_rx        = 1'b1;
+                spi_clock_en     = rx_clk_en;
                 state_next       = DATA_RX;
               end
             end
@@ -478,12 +486,14 @@
                 counter_tx       = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
                 counter_tx_valid = 1'b1;
                 ctrl_data_mux    = DATA_EMPTY;
-                state_next       = DUMMY;
+                spi_clock_en     = tx_clk_en;
+                state_next       = DUMMY_TX;
               end else begin
                 counter_tx       = spi_data_len;
                 counter_tx_valid = 1'b1;
                 ctrl_data_mux    = DATA_FIFO;
                 ctrl_data_valid  = 1'b1;
+                spi_clock_en     = tx_clk_en;
                 state_next       = DATA_TX;
               end
             end
@@ -502,7 +512,7 @@
         spi_cs        = 1'b0;
         spi_clock_en  = 1'b1;
         s_spi_mode    = (en_quad) ? SPI_QUAD_TX : SPI_STD;
-        if (tx_done)
+        if (tx_done && spi_fall)
         begin
           if (spi_data_len != 0)
           begin
@@ -511,17 +521,19 @@
               s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
               if(spi_dummy_rd_len != 0)
               begin
-                counter_tx       = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
-                counter_tx_valid = 1'b1;
-                spi_en_tx        = 1'b1;
+                counter_rx       = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
+                counter_rx_valid = 1'b1;
+                spi_en_rx        = 1'b1;
                 ctrl_data_mux    = DATA_EMPTY;
-                state_next       = DUMMY;
+                spi_clock_en     = rx_clk_en;
+                state_next       = DUMMY_RX;
               end
               else
               begin
                 counter_rx       = spi_data_len;
                 counter_rx_valid = 1'b1;
                 spi_en_rx        = 1'b1;
+                spi_clock_en     = rx_clk_en;
                 state_next       = DATA_RX;
               end
             end
@@ -534,12 +546,14 @@
                 counter_tx       = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
                 counter_tx_valid = 1'b1;
                 ctrl_data_mux    = DATA_EMPTY;
-                state_next       = DUMMY;
+                spi_clock_en     = tx_clk_en;
+                state_next       = DUMMY_TX;
               end else begin
                 counter_tx       = spi_data_len;
                 counter_tx_valid = 1'b1;
                 ctrl_data_mux    = DATA_FIFO;
                 ctrl_data_valid  = 1'b1;
+                spi_clock_en     = tx_clk_en;
                 state_next       = DATA_TX;
               end
             end
@@ -551,7 +565,7 @@
         end
       end
 
-      DUMMY:
+      DUMMY_TX:
       begin
         spi_en_tx     = 1'b1;
         spi_status[4] = 1'b1;
@@ -559,12 +573,13 @@
         spi_clock_en  = 1'b1;
         s_spi_mode    = (en_quad) ? SPI_QUAD_RX : SPI_STD;
 
-        if (tx_done) begin
+        if (tx_done && spi_fall) begin
           if (spi_data_len != 0) begin
             if (do_rx) begin
               counter_rx       = spi_data_len;
               counter_rx_valid = 1'b1;
               spi_en_rx        = 1'b1;
+              spi_clock_en     = rx_clk_en;
               state_next       = DATA_RX;
             end else begin
               counter_tx       = spi_data_len;
@@ -586,21 +601,60 @@
         begin
           ctrl_data_mux = DATA_EMPTY;
           spi_en_tx     = 1'b1;
-          state_next    = DUMMY;
+          state_next    = DUMMY_TX;
         end
       end
 
+      DUMMY_RX:
+      begin
+        spi_en_rx     = 1'b1;
+        spi_status[5] = 1'b1;
+        spi_cs        = 1'b0;
+        spi_clock_en  = 1'b1;
+        s_spi_mode    = (en_quad) ? SPI_QUAD_RX : SPI_STD;
+
+        if (rx_done && spi_rise) begin
+          if (spi_data_len != 0) begin
+            if (do_rx) begin
+              counter_rx       = spi_data_len;
+              counter_rx_valid = 1'b1;
+              spi_en_rx        = 1'b1;
+              spi_clock_en     = rx_clk_en;
+              state_next       = DATA_RX;
+            end else begin
+              counter_tx       = spi_data_len;
+              counter_tx_valid = 1'b1;
+              s_spi_mode       = (en_quad) ? SPI_QUAD_TX : SPI_STD;
+
+              spi_clock_en     = tx_clk_en;
+              spi_en_tx        = 1'b1;
+              state_next       = DATA_TX;
+            end
+          end
+          else
+          begin
+            eot        = 1'b1;
+            state_next = WAIT_EDGE;
+          end
+        end
+        else
+        begin
+          ctrl_data_mux = DATA_EMPTY;
+          spi_en_tx     = 1'b1;
+          spi_clock_en  = rx_clk_en;
+          state_next    = DUMMY_RX;
+        end
+      end
       DATA_TX:
       begin
-        spi_status[5]    = 1'b1;
+        spi_status[6]    = 1'b1;
         spi_cs           = 1'b0;
         spi_clock_en     = tx_clk_en;
         ctrl_data_mux    = DATA_FIFO;
-        ctrl_data_valid  = 1'b1;
         spi_en_tx        = 1'b1;
         s_spi_mode       = (en_quad) ? SPI_QUAD_TX : SPI_STD;
 
-        if (tx_done) begin
+        if (tx_done && spi_fall) begin
           eot          = 1'b1;
           state_next   = WAIT_EDGE;
           spi_clock_en = 1'b0;
@@ -611,12 +665,12 @@
 
       DATA_RX:
       begin
-        spi_status[6] = 1'b1;
+        spi_status[7] = 1'b1;
         spi_cs        = 1'b0;
         spi_clock_en  = rx_clk_en;
         s_spi_mode    = (en_quad) ? SPI_QUAD_RX : SPI_STD;
 
-        if (rx_done) begin
+        if (rx_done && spi_rise) begin
           state_next = WAIT_EDGE;
         end else begin
           spi_en_rx  = 1'b1;
@@ -625,7 +679,7 @@
       end
       WAIT_EDGE:
       begin
-        spi_status[7] = 1'b1;
+        spi_status[8] = 1'b1;
         spi_cs        = 1'b0;
         spi_clock_en  = 1'b0;
         s_spi_mode    = (en_quad) ? SPI_QUAD_RX : SPI_STD;
@@ -635,7 +689,7 @@
     endcase
   end
 
-assign  spi_ack = ((spi_req ==1) && (state_next == WAIT_EDGE)) ? 1'b1 : 1'b0;
+assign  spi_ack = ((spi_req ==1) && (state == WAIT_EDGE)) ? 1'b1 : 1'b0;
 
 
   always_ff @(posedge clk, negedge rstn)
diff --git a/verilog/rtl/spi_master/src/spim_regs.sv b/verilog/rtl/spi_master/src/spim_regs.sv
index 7d06f3e..7e826b6 100644
--- a/verilog/rtl/spi_master/src/spim_regs.sv
+++ b/verilog/rtl/spi_master/src/spim_regs.sv
@@ -66,7 +66,7 @@
 
     output logic                   [7:0] spi_clk_div,
     output logic                         spi_clk_div_valid,
-    input logic                    [7:0] spi_status,
+    input logic                    [8:0] spi_status,
 
     // Towards SPI TX/RX FSM
 
@@ -107,10 +107,12 @@
 parameter REG_STATUS   = 4'b1000;
 
 // Init FSM
-parameter SPI_INIT_IDLE     = 3'b000;
-parameter SPI_INIT_CMD_WAIT = 3'b001;
-parameter SPI_INIT_WRR_CMD  = 3'b010;
-parameter SPI_INIT_WRR_WAIT = 3'b011;
+parameter SPI_INIT_IDLE      = 3'b000;
+parameter SPI_INIT_CMD_WAIT  = 3'b001;
+parameter SPI_INIT_WREN_CMD  = 3'b010;
+parameter SPI_INIT_WREN_WAIT = 3'b011;
+parameter SPI_INIT_WRR_CMD   = 3'b100;
+parameter SPI_INIT_WRR_WAIT  = 3'b101;
 
 //---------------------------------------------------------
 // Variable declartion
@@ -161,8 +163,8 @@
     assign  spi_mode_cmd      =  (spim_mem_req && !spim_wb_we) ? 8'h00                          : reg2spi_mode;       
     assign  spi_mode_cmd_enb  =  (spim_mem_req && !spim_wb_we) ? 1                              : reg2spi_mode_enb;   
     assign  spi_csreg         =  (spim_mem_req && !spim_wb_we) ? '1                             : reg2spi_csreg;     
-    assign  spi_data_len      =  (spim_mem_req && !spim_wb_we) ? 'h10                           : reg2spi_data_len;  
-    assign  spi_dummy_rd_len  =  (spim_mem_req && !spim_wb_we) ? 16                             : reg2spi_dummy_rd_len;  
+    assign  spi_data_len      =  (spim_mem_req && !spim_wb_we) ? 'h20                           : reg2spi_data_len;  
+    assign  spi_dummy_rd_len  =  (spim_mem_req && !spim_wb_we) ? 'h20                           : reg2spi_dummy_rd_len;  
     assign  spi_dummy_wr_len  =  (spim_mem_req && !spim_wb_we) ? 0                              : reg2spi_dummy_wr_len;  
     assign  spi_swrst         =  (spim_mem_req && !spim_wb_we) ? 0                              : reg2spi_swrst;     
     assign  spi_rd            =  (spim_mem_req && !spim_wb_we) ? 0                              : reg2spi_rd;        
@@ -200,27 +202,29 @@
         spim_wb_we    <= '0;
         spim_wb_ack   <= '0;
    end else begin
-        spim_wb_req   <= wbd_stb_i;
-        spim_wb_req_l <= spim_wb_req;
-        spim_wb_wdata <= wbd_dat_i;
-        spim_wb_addr  <= wbd_adr_i;
-        spim_wb_be    <= wbd_sel_i;
-        spim_wb_we    <= wbd_we_i;
-
-
-	// If there is Reg2Spi read Access, Register the Read Data
-	if(reg2spi_req && (reg2spi_rd || reg2spi_qrd ) && spi_ack) 
-             spim_reg_rdata <= spi_rdata;
-
-	if(!spim_wb_we && spim_wb_req && spi_ack) 
-           spim_wb_rdata <= spi_rdata;
-        else
-           spim_wb_rdata <= reg_rdata;
-
+	if(spi_init_done) begin // Wait for internal SPI Init Done
+            spim_wb_req   <= wbd_stb_i && (spi_ack == 0) && (spim_wb_ack==0);
+            spim_wb_req_l <= spim_wb_req;
+            spim_wb_wdata <= wbd_dat_i;
+            spim_wb_addr  <= wbd_adr_i;
+            spim_wb_be    <= wbd_sel_i;
+            spim_wb_we    <= wbd_we_i;
+    
+    
+    	// If there is Reg2Spi read Access, Register the Read Data
+    	if(reg2spi_req && (reg2spi_rd || reg2spi_qrd ) && spi_ack) 
+                 spim_reg_rdata <= spi_rdata;
+    
+    	if(!spim_wb_we && spim_wb_req && spi_ack) 
+               spim_wb_rdata <= spi_rdata;
+            else if (spim_reg_req)
+               spim_wb_rdata <= reg_rdata;
+    
         // For safer design, we have generated ack after 2 cycle latter to 
-	// cross-check current request is towards SPI or not
-        spim_wb_ack   <= (spi_req) ? spi_ack :
-		         ((spim_wb_ack==0) && spim_wb_req && spim_wb_req_l) ;
+    	// cross-check current request is towards SPI or not
+            spim_wb_ack   <= (spi_req && spim_wb_req) ? spi_ack :
+    		         ((spim_wb_ack==0) && spim_wb_req && spim_wb_req_l) ;
+       end
    end
 end
 
@@ -259,7 +263,7 @@
               reg2spi_qwr       <= 'h0;
               reg2spi_swrst     <= 'h0;
               reg2spi_csreg     <= 'h1;
-              reg2spi_cmd[7:0]  <= 'h6; // WREN command
+              reg2spi_cmd[7:0]  <= 'hAB; // POWER UP command
               reg2spi_mode[7:0] <= 'h0;
               reg2spi_cmd_len   <= 'h8;
               reg2spi_addr_len  <= 'h0;
@@ -272,6 +276,30 @@
 	   begin
 	      if(spi_ack)   begin
 	         reg2spi_req      <= 1'b0;
+                 spi_init_state    <=  SPI_INIT_WREN_CMD;
+	      end
+           end
+	   SPI_INIT_WREN_CMD:
+	   begin
+              reg2spi_rd        <= 'h0;
+              reg2spi_wr        <= 'h1; // SPI Write Req
+              reg2spi_qrd       <= 'h0;
+              reg2spi_qwr       <= 'h0;
+              reg2spi_swrst     <= 'h0;
+              reg2spi_csreg     <= 'h1;
+              reg2spi_cmd[7:0]  <= 'h6; // WREN command
+              reg2spi_mode[7:0] <= 'h0;
+              reg2spi_cmd_len   <= 'h8;
+              reg2spi_addr_len  <= 'h0;
+              reg2spi_data_len  <= 'h0;
+              reg2spi_wdata     <= 'h0;
+	      reg2spi_req       <= 'h1;
+              spi_init_state    <=  SPI_INIT_WREN_WAIT;
+	   end
+	   SPI_INIT_WREN_WAIT:
+	   begin
+	      if(spi_ack)   begin
+	         reg2spi_req      <= 1'b0;
                  spi_init_state    <=  SPI_INIT_WRR_CMD;
 	      end
 	   end
@@ -372,38 +400,43 @@
   end 
 
 
+
+  wire [3:0] reg_addr = spim_wb_addr[7:4];
+
   // implement slave model register read mux
   always_comb
     begin
       reg_rdata = '0;
-      case(spim_wb_addr[7:4])
-        REG_CTRL:
-                reg_rdata[31:0] =  { 20'h0, 
-		                     reg2spi_csreg,
-		                     3'b0,
-		                     reg2spi_swrst,
-		                     reg2spi_qwr,
-		                     reg2spi_qrd,
-		                     reg2spi_wr,
-		                     reg2spi_rd};
+      if(spim_reg_req) begin
+          case(reg_addr)
+            REG_CTRL:
+                    reg_rdata[31:0] =  { 20'h0, 
+            	                     reg2spi_csreg,
+            	                     3'b0,
+            	                     reg2spi_swrst,
+            	                     reg2spi_qwr,
+            	                     reg2spi_qrd,
+            	                     reg2spi_wr,
+            	                     reg2spi_rd};
 
-        REG_CLKDIV:
-                reg_rdata[31:0] = {24'h0,spi_clk_div};
-        REG_SPICMD:
-                reg_rdata[31:0] = {16'h0,reg2spi_mode,reg2spi_cmd};
-        REG_SPIADR:
-                reg_rdata[31:0] = reg2spi_addr;
-        REG_SPILEN:
-                reg_rdata[31:0] = {reg2spi_data_len,2'b00,reg2spi_addr_len,1'b0,reg2spi_mode_enb,reg2spi_cmd_len};
-        REG_SPIDUM:
-                reg_rdata[31:0] = {reg2spi_dummy_wr_len,reg2spi_dummy_rd_len};
-        REG_SPIWDATA:
-                reg_rdata[31:0] = reg2spi_wdata;
-        REG_SPIRDATA:
-                reg_rdata[31:0] = spim_reg_rdata;
-        REG_STATUS:
-                reg_rdata[31:0] = {24'h0,spi_status};
-      endcase
+            REG_CLKDIV:
+                    reg_rdata[31:0] = {24'h0,spi_clk_div};
+            REG_SPICMD:
+                    reg_rdata[31:0] = {16'h0,reg2spi_mode,reg2spi_cmd};
+            REG_SPIADR:
+                    reg_rdata[31:0] = reg2spi_addr;
+            REG_SPILEN:
+                    reg_rdata[31:0] = {reg2spi_data_len,2'b00,reg2spi_addr_len,1'b0,reg2spi_mode_enb,reg2spi_cmd_len};
+            REG_SPIDUM:
+                    reg_rdata[31:0] = {reg2spi_dummy_wr_len,reg2spi_dummy_rd_len};
+            REG_SPIWDATA:
+                    reg_rdata[31:0] = reg2spi_wdata;
+            REG_SPIRDATA:
+                    reg_rdata[31:0] = spim_reg_rdata;
+            REG_STATUS:
+                    reg_rdata[31:0] = {23'h0,spi_status};
+          endcase
+       end
     end 
 
 
diff --git a/verilog/rtl/spi_master/src/spim_rx.sv b/verilog/rtl/spi_master/src/spim_rx.sv
index f11c16b..ea0d8a9 100644
--- a/verilog/rtl/spi_master/src/spim_rx.sv
+++ b/verilog/rtl/spi_master/src/spim_rx.sv
@@ -72,7 +72,6 @@
   logic [15:0] counter;
   logic [15:0] counter_trgt;
   logic [15:0] counter_next;
-  logic [15:0] counter_trgt_next;
   logic        reg_done;
   enum logic [1:0] { IDLE, RECEIVE, WAIT_FIFO, WAIT_FIFO_DONE } rx_CS, rx_NS;
 
@@ -81,27 +80,17 @@
 
   // RISV is little endian, so data is converted to little endian format
   assign data = (ENDIEAN) ? data_int_next : {data_int_next[7:0],data_int_next[15:8],data_int_next[23:16],data_int_next[31:24]};
-  assign rx_done = (counter == (counter_trgt-1)) &  rx_edge;
 
-  always_comb
-  begin
-    if (counter_in_upd)
-      counter_trgt_next = (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;
-    else
-      counter_trgt_next = counter_trgt;
-  end
 
   always_comb
   begin
     rx_NS         = rx_CS;
-    clk_en_o      = 1'b0;
     data_int_next = data_int;
     data_valid    = 1'b0;
     counter_next  = counter;
 
     case (rx_CS)
       IDLE: begin
-        clk_en_o = 1'b0;
 
         // check first if there is available space instead of later
         if (en) begin
@@ -110,7 +99,6 @@
       end
 
       RECEIVE: begin
-        clk_en_o = 1'b1;
 
         if (rx_edge) begin
           counter_next = counter + 1;
@@ -132,7 +120,6 @@
 
             if (~data_ready) begin
               // no space in the FIFO, wait for free space
-              clk_en_o = 1'b0;
               rx_NS    = WAIT_FIFO;
             end
           end
@@ -161,14 +148,22 @@
       counter      <= 0;
       counter_trgt <= 'h8;
       data_int     <= '0;
+      rx_done      <= '0;
+      clk_en_o     <= '0;
       rx_CS        <= IDLE;
     end
     else
     begin
-      counter      <= counter_next;
-      counter_trgt <= counter_trgt_next;
-      data_int     <= data_int_next;
-      rx_CS        <= rx_NS;
+      if (rx_edge) begin
+         counter      <= counter_next;
+         data_int     <= data_int_next;
+         rx_CS        <= rx_NS;
+         rx_done      <= (counter_next == (counter_trgt-1)) && (rx_NS == RECEIVE);
+         clk_en_o     <= (rx_NS == RECEIVE);
+      end
+       if (en && counter_in_upd) begin
+          counter_trgt <= (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;
+	end
     end
   end
 
diff --git a/verilog/rtl/spi_master/src/spim_top.sv b/verilog/rtl/spi_master/src/spim_top.sv
index 079c7e9..67d09de 100644
--- a/verilog/rtl/spi_master/src/spim_top.sv
+++ b/verilog/rtl/spi_master/src/spim_top.sv
@@ -85,7 +85,8 @@
 
     logic   [7:0] spi_clk_div;
     logic         spi_clk_div_valid;
-    logic   [7:0] spi_status;
+    logic         spi_req;
+    logic         spi_ack;
     logic  [31:0] spi_addr;
     logic   [5:0] spi_addr_len;
     logic  [7:0]  spi_cmd;
@@ -109,7 +110,7 @@
     logic  [31:0] spi_data_rx;
     logic         spi_data_rx_valid;
     logic         spi_data_rx_ready;
-    logic   [7:0] spi_ctrl_status;
+    logic   [8:0] spi_ctrl_status;
     logic  [31:0] spi_ctrl_data_tx;
     logic         spi_ctrl_data_tx_valid;
     logic         spi_ctrl_data_tx_ready;
@@ -144,7 +145,7 @@
 
         .spi_clk_div                    (spi_clk_div                  ),
         .spi_clk_div_valid              (spi_clk_div_valid            ),
-        .spi_status                     (spi_status                   ),
+        .spi_status                     (spi_ctrl_status              ),
 
 
         .spi_req                        (spi_req                     ),
diff --git a/verilog/rtl/spi_master/src/spim_tx.sv b/verilog/rtl/spi_master/src/spim_tx.sv
index d3fd332..db6516e 100644
--- a/verilog/rtl/spi_master/src/spim_tx.sv
+++ b/verilog/rtl/spi_master/src/spim_tx.sv
@@ -80,15 +80,6 @@
 
   enum logic [0:0] { IDLE, TRANSMIT } tx_CS, tx_NS;
 
-  // Counter Exit condition, quad mode div-4 , else actual counter
-  always_comb
-  begin
-     counter_trgt = (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;
-  end
-
-  //Indicate end of transmission of all the bytes
-  assign tx_done = (counter == counter_trgt) && tx_edge;
-
 
   // Indicate 32 bit data done, usefull for readining next 32b from txfifo
   assign tx32b_done  = (!en_quad && (counter[4:0] == 5'b11111)) || (en_quad && (counter[2:0] == 3'b111)) && tx_edge;
@@ -98,15 +89,14 @@
   always_comb
   begin
     tx_NS         = tx_CS;
-    clk_en_o      = 1'b0;
     data_int_next = data_int;
     data_ready    = 1'b0;
     counter_next  = counter;
 
     case (tx_CS)
       IDLE: begin
-        clk_en_o = 1'b0;
         data_int_next = txdata;
+        counter_next  = '0;
 
         if (en && data_valid) begin
           data_ready    = 1'b1;
@@ -115,27 +105,24 @@
       end
 
       TRANSMIT: begin
-        clk_en_o = 1'b1;
-        counter_next = counter + 1;
-        data_int_next = (en_quad) ? {data_int[27:0],4'b0000} : {data_int[30:0],1'b0};
+       counter_next = counter + 1;
+       data_int_next = (en_quad) ? {data_int[27:0],4'b0000} : {data_int[30:0],1'b0};
 
-        if (tx_done) begin
+      if (tx_done) begin
             counter_next = 0;
-	    // Check if there is next data
+            // Check if there is next data
             if (en && data_valid) begin 
               data_int_next = txdata;
               data_ready    = 1'b1;
               tx_NS         = TRANSMIT;
             end else begin
-              clk_en_o = 1'b0;
               tx_NS    = IDLE;
             end
-        end else if (tx32b_done) begin
+      end else if (tx32b_done) begin
             if (data_valid) begin
               data_int_next = txdata;
               data_ready    = 1'b1;
             end else begin
-              clk_en_o = 1'b0;
               tx_NS    = IDLE;
             end
         end
@@ -151,6 +138,13 @@
       data_int     <= 'h0;
       tx_CS        <= IDLE;
       en_quad      <= 0;
+      tx_done      <= '0;
+      clk_en_o     <= '0;
+      sdo0         <= '0;
+      sdo1         <= '0;
+      sdo2         <= '0;
+      sdo3         <= '0;
+      counter_trgt <= '0;
     end
     else
     begin
@@ -158,12 +152,18 @@
           counter      <= counter_next;
           data_int     <= data_int_next;
           sdo0         <= (en_quad_in) ? data_int_next[28] : data_int_next[31];
-          sdo1         <= (en_quad_in) ? data_int_next[29] : 1'b1;
-          sdo2         <= (en_quad_in) ? data_int_next[30] : 1'b1;
-          sdo3         <= (en_quad_in) ? data_int_next[31] : 1'b1;
+          sdo1         <= (en_quad_in) ? data_int_next[29] : 1'b0;
+          sdo2         <= (en_quad_in) ? data_int_next[30] : 1'b0;
+          sdo3         <= (en_quad_in) ? data_int_next[31] : 1'b0;
           tx_CS        <= tx_NS;
 	  en_quad      <= en_quad_in;
+          tx_done      <= (counter_next == (counter_trgt -1)) && (tx_NS == TRANSMIT);
+          clk_en_o     <= (tx_NS == TRANSMIT);
        end
-    end
+       // Counter Exit condition, quad mode div-4 , else actual counter
+       if (en && data_valid) begin
+          counter_trgt <= (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;
+       end
+    end      
   end
 endmodule
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv
index b587fa0..9c76c7d 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv
@@ -104,7 +104,7 @@
     // EXU <-> DMEM interface
     output  logic                               exu2dmem_req_o,             // Data memory request
     output  logic                               exu2dmem_cmd_o,             // Data memory command - cp.7
-    output  type_scr1_mem_width_e               exu2dmem_width_o,           // Data memory width
+    output  logic [1:0]                         exu2dmem_width_o,           // Data memory width
     output  logic [`SCR1_DMEM_AWIDTH-1:0]       exu2dmem_addr_o,            // Data memory address
     output  logic [`SCR1_DMEM_DWIDTH-1:0]       exu2dmem_wdata_o,           // Data memory write data
     input   logic                               dmem2exu_req_ack_i,         // Data memory request acknowledge
@@ -167,10 +167,10 @@
 // Local types declaration
 //------------------------------------------------------------------------------
 
-typedef enum logic {
-    SCR1_CSR_INIT,
-    SCR1_CSR_RDY
-} scr1_csr_access_e;
+//typedef enum logic {
+parameter     SCR1_CSR_INIT = 1'b0;
+parameter     SCR1_CSR_RDY  = 1'b1;
+//} scr1_csr_access_e;
 
 //------------------------------------------------------------------------------
 // Local signals declaration
@@ -280,8 +280,8 @@
 // CSR signals
 //------------------------------------------------------------------------------
 // CSR access register
-scr1_csr_access_e                   csr_access_ff;
-scr1_csr_access_e                   csr_access_next;
+logic                               csr_access_ff;
+logic                               csr_access_next;
 logic                               csr_access_init;
 
 //------------------------------------------------------------------------------
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
index 393541d..0cc18e6 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
@@ -80,17 +80,17 @@
 } type_scr1_ialu_flags_s;
 
  `ifdef SCR1_RVM_EXT
-typedef enum logic [1:0] {
-    SCR1_IALU_MDU_FSM_IDLE,
-    SCR1_IALU_MDU_FSM_ITER,
-    SCR1_IALU_MDU_FSM_CORR
-} type_scr1_ialu_fsm_state;
+//typedef enum logic [1:0] {
+parameter    SCR1_IALU_MDU_FSM_IDLE  = 2'b00;
+parameter    SCR1_IALU_MDU_FSM_ITER  = 2'b01;
+parameter    SCR1_IALU_MDU_FSM_CORR  = 2'b10;
+//} type_scr1_ialu_fsm_state;
 
-typedef enum logic [1:0] {
-   SCR1_IALU_MDU_NONE,
-   SCR1_IALU_MDU_MUL,
-   SCR1_IALU_MDU_DIV
-} type_scr1_ialu_mdu_cmd;
+//typedef enum logic [1:0] {
+parameter   SCR1_IALU_MDU_NONE       = 2'b00;
+parameter   SCR1_IALU_MDU_MUL        = 2'b01;
+parameter   SCR1_IALU_MDU_DIV        = 2'b10;
+//} type_scr1_ialu_mdu_cmd;
  `endif // SCR1_RVM_EXT
 
 //-------------------------------------------------------------------------------
@@ -123,8 +123,8 @@
 logic                                       rem_corr_req;       // Correction request for REM(U) operations
 
 // MUL/DIV FSM signals
-type_scr1_ialu_fsm_state                    mdu_fsm_ff;         // Current FSM state
-type_scr1_ialu_fsm_state                    mdu_fsm_next;       // Next FSM state
+logic [1:0]                                 mdu_fsm_ff;         // Current FSM state
+logic [1:0]                                 mdu_fsm_next;       // Next FSM state
 logic                                       mdu_fsm_idle;       // MDU FSM is in IDLE state
 `ifdef SCR1_TRGT_SIMULATION
 logic                                       mdu_fsm_iter;       // MDU FSM is in ITER state
@@ -132,7 +132,7 @@
 logic                                       mdu_fsm_corr;       // MDU FSM is in CORR state
 
 // MDU command signals
-type_scr1_ialu_mdu_cmd                      mdu_cmd;            // MDU command: 00 - NONE, 01 - MUL,  10 - DIV
+logic [1:0]                                 mdu_cmd;            // MDU command: 00 - NONE, 01 - MUL,  10 - DIV
 logic                                       mdu_cmd_mul;        // MDU command is MUL(HSU)
 logic                                       mdu_cmd_div;        // MDU command is DIV(U)/REM(U)
 logic        [1:0]                          mul_cmd;            // MUL command: 00 - MUL,  01 - MULH, 10 - MULHSU, 11 - MULHU
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv
index 86b4d41..8b4ae76 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv
@@ -57,8 +57,8 @@
 //-------------------------------------------------------------------------------
 
 logic [`SCR1_IMEM_DWIDTH-1:0]       instr;
-type_scr1_instr_type_e              instr_type;
-type_scr1_rvi_opcode_e              rvi_opcode;
+logic [1:0]                         instr_type;
+logic [6:2]                         rvi_opcode;
 logic                               rvi_illegal;
 logic [2:0]                         funct3;
 logic [6:0]                         funct7;
@@ -80,19 +80,10 @@
 assign instr          = ifu2idu_instr_i;
 
 // RVI / RVC
-`ifdef YOSYS
-assign instr_type   = 2'(instr[1:0]);
-`else 
-
-assign instr_type   = type_scr1_instr_type_e'(instr[1:0]);
-`endif
+assign instr_type   = instr[1:0];
 
 // RVI / RVC fields
-`ifdef YOSYS
-assign rvi_opcode   = 5'(instr[6:2]);                          // RVI
-`else 
-assign rvi_opcode   = type_scr1_rvi_opcode_e'(instr[6:2]);                          // RVI
-`endif
+assign rvi_opcode   = instr[6:2];                          // RVI
 assign funct3       = (instr_type == SCR1_INSTR_RVI) ? instr[14:12] : instr[15:13]; // RVI / RVC
 assign funct7       = instr[31:25];                                                 // RVI
 assign funct12      = instr[31:20];                                                 // RVI (SYSTEM)
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv
index c8f562b..98b5496 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv
@@ -40,10 +40,10 @@
     // IFU <-> IMEM interface
     input   logic                                   imem2ifu_req_ack_i,         // Instruction memory request acknowledgement
     output  logic                                   ifu2imem_req_o,             // Instruction memory request
-    output  type_scr1_mem_cmd_e                     ifu2imem_cmd_o,             // Instruction memory command (READ/WRITE)
+    output  logic                                   ifu2imem_cmd_o,             // Instruction memory command (READ/WRITE)
     output  logic [`SCR1_IMEM_AWIDTH-1:0]           ifu2imem_addr_o,            // Instruction memory address
     input   logic [`SCR1_IMEM_DWIDTH-1:0]           imem2ifu_rdata_i,           // Instruction memory read data
-    input   type_scr1_mem_resp_e                    imem2ifu_resp_i,            // Instruction memory response
+    input   logic [1:0]                             imem2ifu_resp_i,            // Instruction memory response
 
     // IFU <-> EXU New PC interface
     input   logic                                   exu2ifu_pc_new_req_i,       // New PC request (jumps, branches, traps etc)
@@ -88,22 +88,22 @@
 // Local types declaration
 //------------------------------------------------------------------------------
 
-typedef enum logic {
-    SCR1_IFU_FSM_IDLE,
-    SCR1_IFU_FSM_FETCH
-} type_scr1_ifu_fsm_e;
+//typedef enum logic {
+parameter    SCR1_IFU_FSM_IDLE    = 1'b0;
+parameter    SCR1_IFU_FSM_FETCH   = 1'b1;
+//} type_scr1_ifu_fsm_e;
 
-typedef enum logic[1:0] {
-    SCR1_IFU_QUEUE_WR_NONE,      // No write to queue
-    SCR1_IFU_QUEUE_WR_FULL,      // Write 32 rdata bits to queue
-    SCR1_IFU_QUEUE_WR_HI         // Write 16 upper rdata bits to queue
-} type_scr1_ifu_queue_wr_e;
+//typedef enum logic[1:0] {
+parameter    SCR1_IFU_QUEUE_WR_NONE = 2'b00;  // No write to queue
+parameter    SCR1_IFU_QUEUE_WR_FULL = 2'b01;  // Write 32 rdata bits to queue
+parameter    SCR1_IFU_QUEUE_WR_HI   = 2'b10;  // Write 16 upper rdata bits to queue
+//} type_scr1_ifu_queue_wr_e;
 
-typedef enum logic[1:0] {
-    SCR1_IFU_QUEUE_RD_NONE,      // No queue read
-    SCR1_IFU_QUEUE_RD_HWORD,     // Read halfword
-    SCR1_IFU_QUEUE_RD_WORD       // Read word
-} type_scr1_ifu_queue_rd_e;
+//typedef enum logic[1:0] {
+parameter    SCR1_IFU_QUEUE_RD_NONE  = 2'b00; // No queue read
+parameter    SCR1_IFU_QUEUE_RD_HWORD = 2'b01; // Read halfword
+parameter    SCR1_IFU_QUEUE_RD_WORD  = 2'b10; // Read word
+//} type_scr1_ifu_queue_rd_e;
 
 `ifdef SCR1_NO_DEC_STAGE
 typedef enum logic[1:0] {
@@ -114,17 +114,17 @@
 } type_scr1_bypass_e;
 `endif // SCR1_NO_DEC_STAGE
 
-typedef enum logic [2:0] {
+//typedef enum logic [2:0] {
     // SCR1_IFU_INSTR_<UPPER_16_BITS>_<LOWER_16_BITS>
-    SCR1_IFU_INSTR_NONE,                // No valid instruction
-    SCR1_IFU_INSTR_RVI_HI_RVI_LO,       // Full RV32I instruction
-    SCR1_IFU_INSTR_RVC_RVC,
-    SCR1_IFU_INSTR_RVI_LO_RVC,
-    SCR1_IFU_INSTR_RVC_RVI_HI,
-    SCR1_IFU_INSTR_RVI_LO_RVI_HI,
-    SCR1_IFU_INSTR_RVC_NV,              // Instruction after unaligned new_pc
-    SCR1_IFU_INSTR_RVI_LO_NV            // Instruction after unaligned new_pc
-} type_scr1_ifu_instr_e;
+parameter     SCR1_IFU_INSTR_NONE           = 3'b000 ; // No valid instruction
+parameter     SCR1_IFU_INSTR_RVI_HI_RVI_LO  = 3'b001 ; // Full RV32I instruction
+parameter     SCR1_IFU_INSTR_RVC_RVC        = 3'b010 ;
+parameter     SCR1_IFU_INSTR_RVI_LO_RVC     = 3'b011 ;
+parameter     SCR1_IFU_INSTR_RVC_RVI_HI     = 3'b100 ;
+parameter     SCR1_IFU_INSTR_RVI_LO_RVI_HI  = 3'b101 ;
+parameter     SCR1_IFU_INSTR_RVC_NV         = 3'b110 ;  // Instruction after unaligned new_pc
+parameter     SCR1_IFU_INSTR_RVI_LO_NV      = 3'b111 ;  // Instruction after unaligned new_pc
+//} type_scr1_ifu_instr_e;
 
 //------------------------------------------------------------------------------
 // Local signals declaration
@@ -141,7 +141,7 @@
 // IMEM instruction type decoder
 logic                               instr_hi_is_rvi;
 logic                               instr_lo_is_rvi;
-type_scr1_ifu_instr_e               instr_type;
+logic [2:0]                         instr_type;
 
 // Register to store if the previous IMEM instruction had low part of RVI instruction
 // in its high part
@@ -149,11 +149,11 @@
 logic                               instr_hi_rvi_lo_next;
 
 // Queue read/write size decoders
-type_scr1_ifu_queue_rd_e            q_rd_size;
+logic [1:0]                         q_rd_size;
 logic                               q_rd_vd;
 logic                               q_rd_none;
 logic                               q_rd_hword;
-type_scr1_ifu_queue_wr_e            q_wr_size;
+logic [1:0]                         q_wr_size;
 logic                               q_wr_none;
 logic                               q_wr_full;
 
@@ -196,8 +196,8 @@
 logic                               ifu_fetch_req;
 logic                               ifu_stop_req;
 
-type_scr1_ifu_fsm_e                 ifu_fsm_curr;
-type_scr1_ifu_fsm_e                 ifu_fsm_next;
+logic                               ifu_fsm_curr;
+logic                               ifu_fsm_next;
 logic                               ifu_fsm_fetch;
 
 // IMEM signals
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv
index cb87993..3d75570 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv
@@ -51,31 +51,31 @@
 
     // LSU <-> DMEM interface
     output  logic                               lsu2dmem_req_o,             // Data memory request
-    output  type_scr1_mem_cmd_e                 lsu2dmem_cmd_o,             // Data memory command (READ/WRITE)
-    output  type_scr1_mem_width_e               lsu2dmem_width_o,           // Data memory data width
+    output  logic                               lsu2dmem_cmd_o,             // Data memory command (READ/WRITE)
+    output  logic [1:0]                         lsu2dmem_width_o,           // Data memory data width
     output  logic [`SCR1_DMEM_AWIDTH-1:0]       lsu2dmem_addr_o,            // Data memory address
     output  logic [`SCR1_DMEM_DWIDTH-1:0]       lsu2dmem_wdata_o,           // Data memory write data
     input   logic                               dmem2lsu_req_ack_i,         // Data memory request acknowledge
     input   logic [`SCR1_DMEM_DWIDTH-1:0]       dmem2lsu_rdata_i,           // Data memory read data
-    input   type_scr1_mem_resp_e                dmem2lsu_resp_i             // Data memory response
+    input   logic [1:0]                         dmem2lsu_resp_i             // Data memory response
 );
 
 //------------------------------------------------------------------------------
 // Local types declaration
 //------------------------------------------------------------------------------
 
-typedef enum logic {
-    SCR1_LSU_FSM_IDLE,
-    SCR1_LSU_FSM_BUSY
-} type_scr1_lsu_fsm_e;
+//typedef enum logic {
+parameter  SCR1_LSU_FSM_IDLE = 1'b0;
+parameter  SCR1_LSU_FSM_BUSY = 1'b1;
+//} type_scr1_lsu_fsm_e;
 
 //------------------------------------------------------------------------------
 // Local signals declaration
 //------------------------------------------------------------------------------
 
 // LSU FSM signals
-type_scr1_lsu_fsm_e         lsu_fsm_curr;       // LSU FSM current state
-type_scr1_lsu_fsm_e         lsu_fsm_next;       // LSU FSM next state
+logic                       lsu_fsm_curr;       // LSU FSM current state
+logic                       lsu_fsm_next;       // LSU FSM next state
 logic                       lsu_fsm_idle;       // LSU FSM is in IDLE state
 
 // LSU Command register signals
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv
index 6cb2a34..89c0b3e 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv
@@ -60,7 +60,7 @@
 logic   [`SCR1_XLEN-1:0]    mprf_int2  [1:`SCR1_MPRF_SIZE-1];
  `endif
 `else  // distributed logic implementation
-type_scr1_mprf_v [1:`SCR1_MPRF_SIZE-1]                  mprf_int;
+logic [`SCR1_XLEN-1:0]      mprf_int [1:`SCR1_MPRF_SIZE-1];
 `endif
 
 //------------------------------------------------------------------------------
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv
index 69ea0d1..4678a9a 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv
@@ -3,6 +3,14 @@
 /// @brief      SCR1 pipeline top
 ///
 
+//----------------------------------------------------------------------------------
+//  project : YiFive
+// Rev: June 10, 2021, Dinesh A
+//           Bugfix- reset correction for scr1_pipe_tdu when debug is not enabled
+//           Note: previously reset rst_n is floating at simulation is failing
+//           when SCR1_DBG_EN is disabled
+//---------------------------------------------------------------------------------
+
 `include "scr1_arch_description.svh"
 `include "scr1_memif.svh"
 `include "scr1_riscv_isa_decoding.svh"
@@ -31,21 +39,21 @@
 
     // Instruction Memory Interface
     output  logic                                       pipe2imem_req_o,            // IMEM request
-    output  type_scr1_mem_cmd_e                         pipe2imem_cmd_o,            // IMEM command
+    output  logic                                       pipe2imem_cmd_o,            // IMEM command
     output  logic [`SCR1_IMEM_AWIDTH-1:0]               pipe2imem_addr_o,           // IMEM address
     input   logic                                       imem2pipe_req_ack_i,        // IMEM request acknowledge
     input   logic [`SCR1_IMEM_DWIDTH-1:0]               imem2pipe_rdata_i,          // IMEM read data
-    input   type_scr1_mem_resp_e                        imem2pipe_resp_i,           // IMEM response
+    input   logic [1:0]                                 imem2pipe_resp_i,           // IMEM response
 
     // Data Memory Interface
     output  logic                                       pipe2dmem_req_o,            // DMEM request
-    output  type_scr1_mem_cmd_e                         pipe2dmem_cmd_o,            // DMEM command
-    output  type_scr1_mem_width_e                       pipe2dmem_width_o,          // DMEM data width
+    output  logic                                       pipe2dmem_cmd_o,            // DMEM command
+    output  logic [1:0]                                 pipe2dmem_width_o,          // DMEM data width
     output  logic [`SCR1_DMEM_AWIDTH-1:0]               pipe2dmem_addr_o,           // DMEM address
     output  logic [`SCR1_DMEM_DWIDTH-1:0]               pipe2dmem_wdata_o,          // DMEM write data
     input   logic                                       dmem2pipe_req_ack_i,        // DMEM request acknowledge
     input   logic [`SCR1_DMEM_DWIDTH-1:0]               dmem2pipe_rdata_i,          // DMEM read data
-    input   type_scr1_mem_resp_e                        dmem2pipe_resp_i,           // DMEM response
+    input   logic [1:0]                                 dmem2pipe_resp_i,           // DMEM response
 
 `ifdef SCR1_DBG_EN
     // Debug interface:
@@ -167,7 +175,7 @@
 logic                                       exu2csr_take_exc;       // Take exception trap
 logic                                       exu2csr_mret_update;    // MRET update CSR
 logic                                       exu2csr_mret_instr;     // MRET instruction
-type_scr1_exc_code_e                        exu2csr_exc_code;       // Exception code (see scr1_arch_types.svh)
+logic [SCR1_EXC_CODE_WIDTH_E-1:0]           exu2csr_exc_code;       // Exception code (see scr1_arch_types.svh)
 logic [`SCR1_XLEN-1:0]                      exu2csr_trap_val;       // Trap value
 logic [`SCR1_XLEN-1:0]                      csr2exu_new_pc;         // Exception/IRQ/MRET new PC
 logic                                       csr2exu_irq;            // IRQ request
@@ -589,7 +597,7 @@
  `ifdef SCR1_DBG_EN
     .rst_n                      (dbg_rst_n             ),
  `else
-    .rst_n                      (rst_n                 ),
+    .rst_n                      (pipe_rst_n            ), // dinesh-a: Bugfix- reset correction when debug is not enabled
  `endif // SCR1_DBG_EN
     .clk                        (clk                   ),
     .clk_en                     (1'b1                  ),
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv
index 1d86001..5682cee 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv
@@ -18,7 +18,7 @@
 `ifdef  SCR1_MPRF_RAM
     input   logic   [`SCR1_XLEN-1:0]            mprf2trace_int_i   [1:`SCR1_MPRF_SIZE-1], // MPRF registers content
 `else // SCR1_MPRF_RAM
-    input   type_scr1_mprf_v [1:`SCR1_MPRF_SIZE-1] mprf2trace_int_i,             // MPRF registers content
+    logic [`SCR1_XLEN-1:0]                      mprf2trace_int_i[1:`SCR1_MPRF_SIZE-1],             // MPRF registers content
 `endif // SCR1_MPRF_RAM
     input   logic                                 mprf2trace_wr_en_i,           // MPRF write enable
     input   logic [`SCR1_MPRF_AWIDTH-1:0]         mprf2trace_wr_addr_i,         // MPRF write address
@@ -48,7 +48,7 @@
     input   logic [`SCR1_XLEN-1:2]                csr2trace_mepc_i,             // CSR MEPC register
  `endif // SCR1_RVC_EXT
     input   logic                                 csr2trace_mcause_irq_i,       // CSR MCAUSE.interrupt bit
-    input   type_scr1_exc_code_e                  csr2trace_mcause_ec_i,        // CSR MCAUSE.exception_code bit
+    input   [SCR1_EXC_CODE_WIDTH_E-1:0]           csr2trace_mcause_ec_i,        // CSR MCAUSE.exception_code bit
     input   logic [`SCR1_XLEN-1:0]                csr2trace_mtval_i,            // CSR MTVAL register
     input   logic                                 csr2trace_mstatus_mie_up_i,   // CSR MSTATUS.mie update flag
 
@@ -430,7 +430,7 @@
 `else // SCR1_RVC_EXT
                               {csr2trace_mepc_i, 2'b00};
 `endif // SCR1_RVC_EXT
-    csr_trace1.mcause       = {csr2trace_mcause_irq_i, type_scr1_csr_mcause_ec_v'(csr2trace_mcause_ec_i)};
+    csr_trace1.mcause       = {csr2trace_mcause_irq_i, csr2trace_mcause_ec_i};
     csr_trace1.mtval        = csr2trace_mtval_i;
 
     csr_trace1.mstatus      = '0;
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv
index 582e4bb..ba156f3 100644
--- a/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv
@@ -63,20 +63,20 @@
     // Instruction Memory Interface
     input   logic                                   imem2core_req_ack_i,        // IMEM request acknowledge
     output  logic                                   core2imem_req_o,            // IMEM request
-    output  type_scr1_mem_cmd_e                     core2imem_cmd_o,            // IMEM command
+    output  logic                                   core2imem_cmd_o,            // IMEM command
     output  logic [`SCR1_IMEM_AWIDTH-1:0]           core2imem_addr_o,           // IMEM address
     input   logic [`SCR1_IMEM_DWIDTH-1:0]           imem2core_rdata_i,          // IMEM read data
-    input   type_scr1_mem_resp_e                    imem2core_resp_i,           // IMEM response
+    input   logic [1:0]                             imem2core_resp_i,           // IMEM response
 
     // Data Memory Interface
     input   logic                                   dmem2core_req_ack_i,        // DMEM request acknowledge
     output  logic                                   core2dmem_req_o,            // DMEM request
-    output  type_scr1_mem_cmd_e                     core2dmem_cmd_o,            // DMEM command
-    output  type_scr1_mem_width_e                   core2dmem_width_o,          // DMEM data width
+    output  logic                                   core2dmem_cmd_o,            // DMEM command
+    output  logic[1:0]                             core2dmem_width_o,          // DMEM data width
     output  logic [`SCR1_DMEM_AWIDTH-1:0]           core2dmem_addr_o,           // DMEM address
     output  logic [`SCR1_DMEM_DWIDTH-1:0]           core2dmem_wdata_o,          // DMEM write data
     input   logic [`SCR1_DMEM_DWIDTH-1:0]           dmem2core_rdata_i,          // DMEM read data
-    input   type_scr1_mem_resp_e                    dmem2core_resp_i            // DMEM response
+    input   logic [1:0]                             dmem2core_resp_i            // DMEM response
 );
 
 //-------------------------------------------------------------------------------
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv
index 642dd53..724d98d 100644
--- a/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv
@@ -113,13 +113,13 @@
     DHI_STATE_RESUME_RUN
 } type_scr1_dhi_fsm_e;
 
-typedef enum logic [SCR1_DBG_ABSTRACTCS_CMDERR_WDTH:0] {
-    ABS_ERR_NONE      = (SCR1_DBG_ABSTRACTCS_CMDERR_WDTH+1)'('d0),
-    ABS_ERR_BUSY      = (SCR1_DBG_ABSTRACTCS_CMDERR_WDTH+1)'('d1),
-    ABS_ERR_CMD       = (SCR1_DBG_ABSTRACTCS_CMDERR_WDTH+1)'('d2),
-    ABS_ERR_EXCEPTION = (SCR1_DBG_ABSTRACTCS_CMDERR_WDTH+1)'('d3),
-    ABS_ERR_NOHALT    = (SCR1_DBG_ABSTRACTCS_CMDERR_WDTH+1)'('d4)
-} type_scr1_abs_err_e;
+//typedef enum logic [SCR1_DBG_ABSTRACTCS_CMDERR_WDTH:0] {
+parameter    ABS_ERR_NONE      = (SCR1_DBG_ABSTRACTCS_CMDERR_WDTH+1)'('d0);
+parameter    ABS_ERR_BUSY      = (SCR1_DBG_ABSTRACTCS_CMDERR_WDTH+1)'('d1);
+parameter    ABS_ERR_CMD       = (SCR1_DBG_ABSTRACTCS_CMDERR_WDTH+1)'('d2);
+parameter    ABS_ERR_EXCEPTION = (SCR1_DBG_ABSTRACTCS_CMDERR_WDTH+1)'('d3);
+parameter    ABS_ERR_NOHALT    = (SCR1_DBG_ABSTRACTCS_CMDERR_WDTH+1)'('d4);
+//} type_scr1_abs_err_e;
 
 
 //------------------------------------------------------------------------------
@@ -362,8 +362,8 @@
 logic                                             abs_err_acc_busy_ff;
 logic                                             abs_err_acc_busy_next;
 
-type_scr1_abs_err_e                               abstractcs_cmderr_ff;
-type_scr1_abs_err_e                               abstractcs_cmderr_next;
+logic [SCR1_DBG_ABSTRACTCS_CMDERR_WDTH:0]         abstractcs_cmderr_ff;
+logic [SCR1_DBG_ABSTRACTCS_CMDERR_WDTH:0]         abstractcs_cmderr_next;
 
 // Abstract instruction signals
 //------------------------------------------------------------------------------
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh
index 62f1037..6f76889 100644
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh
+++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh
@@ -20,8 +20,9 @@
   `define SCR1_MPRF_SIZE      32
 `endif // SCR1_RVE_EXT
 
-typedef logic [`SCR1_XLEN-1:0]  type_scr1_mprf_v;
-typedef logic [`SCR1_XLEN-1:0]  type_scr1_pc_v;
+// Masked due to iverilog issue
+//typedef logic [`SCR1_XLEN-1:0]  type_scr1_mprf_v;
+//typedef logic [`SCR1_XLEN-1:0]  type_scr1_pc_v;
 
 parameter int unsigned  SCR1_CSR_ADDR_WIDTH             = 12;
 parameter int unsigned  SCR1_CSR_MTVEC_BASE_ZERO_BITS   = 6;
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh
index 7235d1d..395403e 100644
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh
+++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh
@@ -11,39 +11,39 @@
 //-------------------------------------------------------------------------------
 // Memory command enum
 //-------------------------------------------------------------------------------
-typedef enum logic {
-    SCR1_MEM_CMD_RD     = 1'b0,
-    SCR1_MEM_CMD_WR     = 1'b1
-`ifdef SCR1_XPROP_EN
-    ,
-    SCR1_MEM_CMD_ERROR  = 'x
-`endif // SCR1_XPROP_EN
-} type_scr1_mem_cmd_e;
+//typedef enum logic {
+parameter    SCR1_MEM_CMD_RD     = 1'b0;
+parameter    SCR1_MEM_CMD_WR     = 1'b1;
+//`ifdef SCR1_XPROP_EN
+//    ,
+parameter     SCR1_MEM_CMD_ERROR  = 'x;
+//`endif // SCR1_XPROP_EN
+//} type_scr1_mem_cmd_e;
 
 //-------------------------------------------------------------------------------
 // Memory data width enum
 //-------------------------------------------------------------------------------
-typedef enum logic[1:0] {
-    SCR1_MEM_WIDTH_BYTE     = 2'b00,
-    SCR1_MEM_WIDTH_HWORD    = 2'b01,
-    SCR1_MEM_WIDTH_WORD     = 2'b10
-`ifdef SCR1_XPROP_EN
-    ,
-    SCR1_MEM_WIDTH_ERROR    = 'x
-`endif // SCR1_XPROP_EN
-} type_scr1_mem_width_e;
+//typedef enum logic[1:0] {
+parameter    SCR1_MEM_WIDTH_BYTE     = 2'b00;
+parameter    SCR1_MEM_WIDTH_HWORD    = 2'b01;
+parameter    SCR1_MEM_WIDTH_WORD     = 2'b10;
+//`ifdef SCR1_XPROP_EN
+//    ,
+parameter    SCR1_MEM_WIDTH_ERROR    = 'x;
+//`endif // SCR1_XPROP_EN
+//} type_scr1_mem_width_e;
 
 //-------------------------------------------------------------------------------
 // Memory response enum
 //-------------------------------------------------------------------------------
-typedef enum logic[1:0] {
-    SCR1_MEM_RESP_NOTRDY    = 2'b00,
-    SCR1_MEM_RESP_RDY_OK    = 2'b01,
-    SCR1_MEM_RESP_RDY_ER    = 2'b10
-`ifdef SCR1_XPROP_EN
-    ,
-    SCR1_MEM_RESP_ERROR     = 'x
-`endif // SCR1_XPROP_EN
-} type_scr1_mem_resp_e;
+//typedef enum logic[1:0] {
+parameter    SCR1_MEM_RESP_NOTRDY    = 2'b00;
+parameter    SCR1_MEM_RESP_RDY_OK    = 2'b01;
+parameter    SCR1_MEM_RESP_RDY_ER    = 2'b10;
+//`ifdef SCR1_XPROP_EN
+//    ,
+parameter    SCR1_MEM_RESP_ERROR     = 'x;
+//`endif // SCR1_XPROP_EN
+//} type_scr1_mem_resp_e;
 
 `endif // SCR1_MEMIF_SVH
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh
index e143d89..890807a 100644
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh
+++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh
@@ -12,29 +12,29 @@
 //-------------------------------------------------------------------------------
 // Instruction types
 //-------------------------------------------------------------------------------
-typedef enum logic [1:0] {
-    SCR1_INSTR_RVC0     = 2'b00,
-    SCR1_INSTR_RVC1     = 2'b01,
-    SCR1_INSTR_RVC2     = 2'b10,
-    SCR1_INSTR_RVI      = 2'b11
-} type_scr1_instr_type_e;
+//typedef enum logic [1:0] {
+parameter    SCR1_INSTR_RVC0     = 2'b00;
+parameter    SCR1_INSTR_RVC1     = 2'b01;
+parameter    SCR1_INSTR_RVC2     = 2'b10;
+parameter    SCR1_INSTR_RVI      = 2'b11;
+//} type_scr1_instr_type_e;
 
 //-------------------------------------------------------------------------------
 // RV32I opcodes (bits 6:2)
 //-------------------------------------------------------------------------------
-typedef enum logic [6:2] {
-    SCR1_OPCODE_LOAD        = 5'b00000,
-    SCR1_OPCODE_MISC_MEM    = 5'b00011,
-    SCR1_OPCODE_OP_IMM      = 5'b00100,
-    SCR1_OPCODE_AUIPC       = 5'b00101,
-    SCR1_OPCODE_STORE       = 5'b01000,
-    SCR1_OPCODE_OP          = 5'b01100,
-    SCR1_OPCODE_LUI         = 5'b01101,
-    SCR1_OPCODE_BRANCH      = 5'b11000,
-    SCR1_OPCODE_JALR        = 5'b11001,
-    SCR1_OPCODE_JAL         = 5'b11011,
-    SCR1_OPCODE_SYSTEM      = 5'b11100
-} type_scr1_rvi_opcode_e;
+//typedef enum logic [6:2] {
+parameter    SCR1_OPCODE_LOAD        = 5'b00000;
+parameter    SCR1_OPCODE_MISC_MEM    = 5'b00011;
+parameter    SCR1_OPCODE_OP_IMM      = 5'b00100;
+parameter    SCR1_OPCODE_AUIPC       = 5'b00101;
+parameter    SCR1_OPCODE_STORE       = 5'b01000;
+parameter    SCR1_OPCODE_OP          = 5'b01100;
+parameter    SCR1_OPCODE_LUI         = 5'b01101;
+parameter    SCR1_OPCODE_BRANCH      = 5'b11000;
+parameter    SCR1_OPCODE_JALR        = 5'b11001;
+parameter    SCR1_OPCODE_JAL         = 5'b11011;
+parameter    SCR1_OPCODE_SYSTEM      = 5'b11100;
+//} type_scr1_rvi_opcode_e;
 
 
 //-------------------------------------------------------------------------------
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh
index ab19386..35659d5 100644
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh
+++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh
@@ -16,6 +16,7 @@
 localparam int unsigned         SCR1_SCU_DR_SYSCTRL_OP_WIDTH        = 2;
 localparam int unsigned         SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH      = 2;
 localparam int unsigned         SCR1_SCU_DR_SYSCTRL_DATA_WIDTH      = 4;
+localparam int unsigned         SCR1_SCU_DR_SYSCTRL_WIDTH      = SCR1_SCU_DR_SYSCTRL_OP_WIDTH+SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH+SCR1_SCU_DR_SYSCTRL_DATA_WIDTH; // cp.3
 
 //==============================================================================
 // Types
@@ -73,6 +74,7 @@
     logic                                           dm_rst_bhv;
 } type_scr1_scu_sysctrl_mode_reg_s;
 
+localparam bit [31:0]    SCR1_SCU_SYSCTRL_STATUS_REG_WIDTH        = 4; // cp.3
 typedef struct packed {
     logic                                           hdu_reset;
     logic                                           dm_reset;
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv
index 5b06660..f1a8f00 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv
@@ -14,12 +14,12 @@
     // Core Interface
     output  logic                           dmem_req_ack,
     input   logic                           dmem_req,
-    input   type_scr1_mem_cmd_e             dmem_cmd,
-    input   type_scr1_mem_width_e           dmem_width,
+    input   logic                           dmem_cmd,
+    input   logic [1:0]                     dmem_width,
     input   logic   [SCR1_AHB_WIDTH-1:0]    dmem_addr,
     input   logic   [SCR1_AHB_WIDTH-1:0]    dmem_wdata,
     output  logic   [SCR1_AHB_WIDTH-1:0]    dmem_rdata,
-    output  type_scr1_mem_resp_e            dmem_resp,
+    output  logic [1:0]                     dmem_resp,
 
     // AHB Interface
     output  logic   [3:0]                   hprot,
@@ -78,7 +78,7 @@
 // Local functions
 //-------------------------------------------------------------------------------
 function automatic logic   [2:0] scr1_conv_mem2ahb_width (
-    input   type_scr1_mem_width_e    dmem_width
+    input   logic [1:0]              dmem_width
 );
     logic   [2:0]   tmp;
 begin
@@ -102,7 +102,7 @@
 
 function automatic logic[SCR1_AHB_WIDTH-1:0] scr1_conv_mem2ahb_wdata (
     input   logic   [1:0]                   dmem_addr,
-    input   type_scr1_mem_width_e           dmem_width,
+    input   logic [1:0]                     dmem_width,
     input   logic   [SCR1_AHB_WIDTH-1:0]    dmem_wdata
 );
     logic   [SCR1_AHB_WIDTH-1:0]  tmp;
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv
index afef729..badd8cd 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv
@@ -20,42 +20,42 @@
     // Core interface
     output  logic                           dmem_req_ack,
     input   logic                           dmem_req,
-    input   type_scr1_mem_cmd_e             dmem_cmd,
-    input   type_scr1_mem_width_e           dmem_width,
+    input   logic                           dmem_cmd,
+    input   logic [1:0]                     dmem_width,
     input   logic [`SCR1_DMEM_AWIDTH-1:0]   dmem_addr,
     input   logic [`SCR1_DMEM_DWIDTH-1:0]   dmem_wdata,
     output  logic [`SCR1_DMEM_DWIDTH-1:0]   dmem_rdata,
-    output  type_scr1_mem_resp_e            dmem_resp,
+    output  logic [1:0]                     dmem_resp,
 
     // PORT0 interface
     input   logic                           port0_req_ack,
     output  logic                           port0_req,
-    output  type_scr1_mem_cmd_e             port0_cmd,
-    output  type_scr1_mem_width_e           port0_width,
+    output  logic                           port0_cmd,
+    output  logic [1:0]                     port0_width,
     output  logic [`SCR1_DMEM_AWIDTH-1:0]   port0_addr,
     output  logic [`SCR1_DMEM_DWIDTH-1:0]   port0_wdata,
     input   logic [`SCR1_DMEM_DWIDTH-1:0]   port0_rdata,
-    input   type_scr1_mem_resp_e            port0_resp,
+    input   logic [1:0]                     port0_resp,
 
     // PORT1 interface
     input   logic                           port1_req_ack,
     output  logic                           port1_req,
-    output  type_scr1_mem_cmd_e             port1_cmd,
-    output  type_scr1_mem_width_e           port1_width,
+    output  logic                           port1_cmd,
+    output  logic [1:0]                     port1_width,
     output  logic [`SCR1_DMEM_AWIDTH-1:0]   port1_addr,
     output  logic [`SCR1_DMEM_DWIDTH-1:0]   port1_wdata,
     input   logic [`SCR1_DMEM_DWIDTH-1:0]   port1_rdata,
-    input   type_scr1_mem_resp_e            port1_resp,
+    input   logic [1:0]                     port1_resp,
 
     // PORT2 interface
     input   logic                           port2_req_ack,
     output  logic                           port2_req,
-    output  type_scr1_mem_cmd_e             port2_cmd,
-    output  type_scr1_mem_width_e           port2_width,
+    output  logic                           port2_cmd,
+    output  logic [1:0]                     port2_width,
     output  logic [`SCR1_DMEM_AWIDTH-1:0]   port2_addr,
     output  logic [`SCR1_DMEM_DWIDTH-1:0]   port2_wdata,
     input   logic [`SCR1_DMEM_DWIDTH-1:0]   port2_rdata,
-    input   type_scr1_mem_resp_e            port2_resp
+    input   logic [1:0]                     port2_resp
 );
 
 //-------------------------------------------------------------------------------
@@ -79,7 +79,7 @@
 type_scr1_sel_e                 port_sel;
 type_scr1_sel_e                 port_sel_r;
 logic [`SCR1_DMEM_DWIDTH-1:0]   sel_rdata;
-type_scr1_mem_resp_e            sel_resp;
+logic [1:0]                     sel_resp;
 logic                           sel_req_ack;
 
 //-------------------------------------------------------------------------------
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv
index 24691d4..85a0c5c 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv
@@ -17,6 +17,10 @@
 ////  Revision :                                                  ////
 ////     v0:    June 7, 2021, Dinesh A                            ////
 ////             wishbone integration                             ////
+////     v1:    June 9, 2021, Dinesh A                            ////
+////              On power up, wishbone output are unkown as it   ////
+////              driven from fifo output. To avoid unknown       ////
+////              propgation, we are driving 'h0 when fifo empty  ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -62,12 +66,12 @@
     // Core Interface
     output  logic                           dmem_req_ack,
     input   logic                           dmem_req,
-    input   type_scr1_mem_cmd_e             dmem_cmd,
-    input   type_scr1_mem_width_e           dmem_width,
+    input   logic                           dmem_cmd,
+    input   logic [1:0]                     dmem_width,
     input   logic   [SCR1_WB_WIDTH-1:0]     dmem_addr,
     input   logic   [SCR1_WB_WIDTH-1:0]     dmem_wdata,
     output  logic   [SCR1_WB_WIDTH-1:0]     dmem_rdata,
-    output  type_scr1_mem_resp_e            dmem_resp,
+    output  logic [1:0]                     dmem_resp,
 
     // WB Interface
     output  logic                           wbd_stb_o, // strobe/request
@@ -106,7 +110,6 @@
 } type_scr1_req_fifo_s;
 
 typedef struct packed {
-    logic                           hwrite;
     logic   [2:0]                   hwidth;
     logic   [1:0]                   haddr;
 } type_scr1_data_fifo_s;
@@ -122,7 +125,7 @@
 // Local functions
 //-------------------------------------------------------------------------------
 function automatic logic   [2:0] scr1_conv_mem2wb_width (
-    input   type_scr1_mem_width_e    dmem_width
+    input   logic [1:0]              dmem_width
 );
     logic   [2:0]   tmp;
 begin
@@ -146,7 +149,7 @@
 
 function automatic logic[SCR1_WB_WIDTH-1:0] scr1_conv_mem2wb_wdata (
     input   logic   [1:0]                   dmem_addr,
-    input   type_scr1_mem_width_e           dmem_width,
+    input   logic [1:0]                     dmem_width,
     input   logic   [SCR1_WB_WIDTH-1:0]    dmem_wdata
 );
     logic   [SCR1_WB_WIDTH-1:0]  tmp;
@@ -259,7 +262,7 @@
 assign dmem_req_ack = ~req_fifo_full;
 assign req_fifo_wr  = ~req_fifo_full & dmem_req;
 
-assign dmem_rdata = scr1_conv_wb2mem_rdata(resp_fifo.hwidth, resp_fifo.haddr, resp_fifo.hrdata);
+assign dmem_rdata = (resp_fifo_hready) ? scr1_conv_wb2mem_rdata(resp_fifo.hwidth, resp_fifo.haddr, resp_fifo.hrdata) : 'h0;
 
 assign dmem_resp = (resp_fifo_hready)
                     ? (resp_fifo.hresp == 1'b1)
@@ -429,18 +432,20 @@
 always_ff @(posedge clk) begin
     if (wbd_ack_i) begin
         resp_fifo.hresp  <= (wbd_err_i) ? 1'b0 : 1'b1;
-        resp_fifo.hwidth <= data_fifo.hwidth;
-        resp_fifo.haddr  <= data_fifo.haddr;
-        resp_fifo.hrdata <= wbd_dat_i;
+        resp_fifo.hwidth <= hwidth_out;
+        resp_fifo.haddr  <= haddr_out[1:0];
+        resp_fifo.hrdata <= (wbd_we_o) ? 'h0: wbd_dat_i;
     end
 end
 
 
 assign wbd_stb_o    = ~req_fifo_empty;
-assign wbd_adr_o    = haddr_out;
-assign wbd_we_o     = hwrite_out;
-assign wbd_dat_o    = hwdata_out;
-assign wbd_sel_o    = hbel_out;
+
+// To avoid unknown progating the design, driven zero when fifo is empty
+assign wbd_adr_o    = (req_fifo_empty) ? 'h0 : haddr_out;
+assign wbd_we_o     = (req_fifo_empty) ? 'h0 : hwrite_out;
+assign wbd_dat_o    = (req_fifo_empty) ? 'h0 : hwdata_out;
+assign wbd_sel_o    = (req_fifo_empty) ? 'h0 : hbel_out;
 
 `endif // SCR1_DMEM_WB_IN_BP
 
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv
index e749f9d..47ad399 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv
@@ -16,7 +16,7 @@
     input   logic                           imem_req,
     input   logic   [SCR1_AHB_WIDTH-1:0]    imem_addr,
     output  logic   [SCR1_AHB_WIDTH-1:0]    imem_rdata,
-    output  type_scr1_mem_resp_e            imem_resp,
+    output  logic [1:0]                     imem_resp,
 
     // AHB Interface
     output  logic   [3:0]                   hprot,
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv
index dd76f25..7652201 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv
@@ -18,26 +18,26 @@
     // Core interface
     output  logic                           imem_req_ack,
     input   logic                           imem_req,
-    input   type_scr1_mem_cmd_e             imem_cmd,
+    input   logic                           imem_cmd,
     input   logic [`SCR1_IMEM_AWIDTH-1:0]   imem_addr,
     output  logic [`SCR1_IMEM_DWIDTH-1:0]   imem_rdata,
-    output  type_scr1_mem_resp_e            imem_resp,
+    output  logic [1:0]                     imem_resp,
 
     // PORT0 interface
     input   logic                           port0_req_ack,
     output  logic                           port0_req,
-    output  type_scr1_mem_cmd_e             port0_cmd,
+    output  logic                           port0_cmd,
     output  logic [`SCR1_IMEM_AWIDTH-1:0]   port0_addr,
     input   logic [`SCR1_IMEM_DWIDTH-1:0]   port0_rdata,
-    input   type_scr1_mem_resp_e            port0_resp,
+    input   logic [1:0]                     port0_resp,
 
     // PORT1 interface
     input   logic                           port1_req_ack,
     output  logic                           port1_req,
-    output  type_scr1_mem_cmd_e             port1_cmd,
+    output  logic                           port1_cmd,
     output  logic [`SCR1_IMEM_AWIDTH-1:0]   port1_addr,
     input   logic [`SCR1_IMEM_DWIDTH-1:0]   port1_rdata,
-    input   type_scr1_mem_resp_e            port1_resp
+    input   logic [1:0]                     port1_resp
 );
 
 //-------------------------------------------------------------------------------
@@ -55,7 +55,7 @@
 logic                           port_sel;
 logic                           port_sel_r;
 logic [`SCR1_IMEM_DWIDTH-1:0]   sel_rdata;
-type_scr1_mem_resp_e            sel_resp;
+logic [1:0]                     sel_resp;
 logic                           sel_req_ack;
 
 //-------------------------------------------------------------------------------
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv
index c2a5349..d91c9e3 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv
@@ -17,6 +17,10 @@
 ////  Revision :                                                  ////
 ////     v0:    June 7, 2021, Dinesh A                            ////
 ////             wishbone integration                             ////
+////     v1:    June 9, 2021, Dinesh A                            ////
+////              On power up, wishbone output are unkown as it   ////
+////              driven from fifo output. To avoid unknown       ////
+////              propgation, we are driving 'h0 when fifo empty  ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -64,7 +68,7 @@
     input   logic                           imem_req,
     input   logic   [SCR1_WB_WIDTH-1:0]     imem_addr,
     output  logic   [SCR1_WB_WIDTH-1:0]     imem_rdata,
-    output  type_scr1_mem_resp_e            imem_resp,
+    output  logic [1:0]                     imem_resp,
 
     // WB Interface
     output  logic                           wbd_stb_o, // strobe/request
@@ -227,7 +231,8 @@
 end
 
 assign wbd_stb_o    = ~req_fifo_empty;
-assign wbd_adr_o    = req_fifo_dout;
+// On Power, to avoid unknow propgating the value
+assign wbd_adr_o    = (req_fifo_empty) ? 'h0 : req_fifo_dout; 
 assign wbd_we_o     = 0; // Only Read supported
 assign wbd_dat_o    = 32'h0; // No Write
 assign wbd_sel_o    = 4'b1111; // Only Read allowed in imem i/f
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv
index f6bb7ea..1b9155d 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv
@@ -23,12 +23,12 @@
     output  logic                           core_idle,
     output  logic                           core_req_ack,
     input   logic                           core_req,
-    input   type_scr1_mem_cmd_e             core_cmd,
-    input   type_scr1_mem_width_e           core_width,
+    input   logic                           core_cmd,
+    input   logic [1:0]                     core_width,
     input   logic [SCR1_ADDR_WIDTH-1:0]     core_addr,
     input   logic [31:0]                    core_wdata,
     output  logic [31:0]                    core_rdata,
-    output  type_scr1_mem_resp_e            core_resp,
+    output  logic [1:0]                     core_resp,
 
     // AXI
     output  logic [SCR1_AXI_IDWIDTH-1:0]    awid,
@@ -80,7 +80,7 @@
 
 // Local functions
 function automatic logic [2:0] width2axsize (
-    input   type_scr1_mem_width_e    width );
+    input   logic [1:0]              width );
     logic [2:0] axsize;
 begin
     case (width)
@@ -95,7 +95,7 @@
 endfunction
 
 typedef struct packed {
-    type_scr1_mem_width_e                               axi_width;
+    logic [1:0]                                         axi_width;
     logic                    [SCR1_ADDR_WIDTH-1:0]      axi_addr;
     logic                                   [31:0]      axi_wdata;
 } type_scr1_request_s;
@@ -129,7 +129,7 @@
 logic               [$clog2(SCR1_REQ_BUF_SIZE)-1:0]     req_done_ptr;
 logic                                                   rresp_err;
 logic                                       [31:0]      rcvd_rdata;
-type_scr1_mem_resp_e                                    rcvd_resp;
+logic [1:0]                                             rcvd_resp;
 logic                                                   force_read;
 logic                                                   force_write;
 
@@ -308,6 +308,8 @@
 assign wdata = (force_write)?                       core_wdata << (8*                       core_addr[1:0]) :
                               req_fifo_axi_wdata[req_proc_ptr] << (8* bShift1);
 
+wire [SCR1_ADDR_WIDTH-1:0] CurAddr2 = req_fifo_axi_addr[req_done_ptr];
+wire [1:0]  bShift2 = CurAddr2[1:0];
 
 // Read data adaptation
 always_comb begin
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
index 97376cf..82a8b06 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
@@ -21,17 +21,17 @@
     input   logic                           imem_req,
     input   logic [`SCR1_IMEM_AWIDTH-1:0]   imem_addr,
     output  logic [`SCR1_IMEM_DWIDTH-1:0]   imem_rdata,
-    output  type_scr1_mem_resp_e            imem_resp,
+    output  logic [1:0]                     imem_resp,
 
     // Core data interface
     output  logic                           dmem_req_ack,
     input   logic                           dmem_req,
-    input   type_scr1_mem_cmd_e             dmem_cmd,
-    input   type_scr1_mem_width_e           dmem_width,
+    input   logic                           dmem_cmd,
+    input   logic [1:0]                     dmem_width,
     input   logic [`SCR1_DMEM_AWIDTH-1:0]   dmem_addr,
     input   logic [`SCR1_DMEM_DWIDTH-1:0]   dmem_wdata,
     output  logic [`SCR1_DMEM_DWIDTH-1:0]   dmem_rdata,
-    output  type_scr1_mem_resp_e            dmem_resp
+    output  logic [1:0]                     dmem_resp
 );
 
 //-------------------------------------------------------------------------------
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv
index 343a93a..6787754 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv
@@ -14,13 +14,13 @@
 
     // Memory interface
     input   logic                                   dmem_req,
-    input   type_scr1_mem_cmd_e                     dmem_cmd,
-    input   type_scr1_mem_width_e                   dmem_width,
+    input   logic                                   dmem_cmd,
+    input   logic [1:0]                             dmem_width,
     input   logic [`SCR1_DMEM_AWIDTH-1:0]           dmem_addr,
     input   logic [`SCR1_DMEM_DWIDTH-1:0]           dmem_wdata,
     output  logic                                   dmem_req_ack,
     output  logic [`SCR1_DMEM_DWIDTH-1:0]           dmem_rdata,
-    output  type_scr1_mem_resp_e                    dmem_resp,
+    output  logic [1:0]                             dmem_resp,
 
     // Timer interface
     output  logic [63:0]                            timer_val,
@@ -268,4 +268,4 @@
 //-------------------------------------------------------------------------------
 assign timer_val    = mtime_reg;
 
-endmodule : scr1_timer
\ No newline at end of file
+endmodule : scr1_timer
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv
index 2268a7d..288d15e 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv
@@ -100,68 +100,68 @@
 // Instruction memory interface from core to router
 logic                                               core_imem_req_ack;
 logic                                               core_imem_req;
-type_scr1_mem_cmd_e                                 core_imem_cmd;
+logic                                               core_imem_cmd;
 logic [`SCR1_IMEM_AWIDTH-1:0]                       core_imem_addr;
 logic [`SCR1_IMEM_DWIDTH-1:0]                       core_imem_rdata;
-type_scr1_mem_resp_e                                core_imem_resp;
+logic [1:0]                                         core_imem_resp;
 
 // Data memory interface from core to router
 logic                                               core_dmem_req_ack;
 logic                                               core_dmem_req;
-type_scr1_mem_cmd_e                                 core_dmem_cmd;
-type_scr1_mem_width_e                               core_dmem_width;
+logic                                               core_dmem_cmd;
+logic [1:0]                                         core_dmem_width;
 logic [`SCR1_DMEM_AWIDTH-1:0]                       core_dmem_addr;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       core_dmem_wdata;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       core_dmem_rdata;
-type_scr1_mem_resp_e                                core_dmem_resp;
+logic [1:0]                                         core_dmem_resp;
 
 // Instruction memory interface from router to AHB bridge
 logic                                               ahb_imem_req_ack;
 logic                                               ahb_imem_req;
-type_scr1_mem_cmd_e                                 ahb_imem_cmd;
+logic                                               ahb_imem_cmd;
 logic [`SCR1_IMEM_AWIDTH-1:0]                       ahb_imem_addr;
 logic [`SCR1_IMEM_DWIDTH-1:0]                       ahb_imem_rdata;
-type_scr1_mem_resp_e                                ahb_imem_resp;
+logic [1:0]                                         ahb_imem_resp;
 
 // Data memory interface from router to AHB bridge
 logic                                               ahb_dmem_req_ack;
 logic                                               ahb_dmem_req;
-type_scr1_mem_cmd_e                                 ahb_dmem_cmd;
-type_scr1_mem_width_e                               ahb_dmem_width;
+logic                                               ahb_dmem_cmd;
+logic [1:0]                                         ahb_dmem_width;
 logic [`SCR1_DMEM_AWIDTH-1:0]                       ahb_dmem_addr;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       ahb_dmem_wdata;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       ahb_dmem_rdata;
-type_scr1_mem_resp_e                                ahb_dmem_resp;
+logic [1:0]                                         ahb_dmem_resp;
 
 `ifdef SCR1_TCM_EN
 // Instruction memory interface from router to TCM
 logic                                               tcm_imem_req_ack;
 logic                                               tcm_imem_req;
-type_scr1_mem_cmd_e                                 tcm_imem_cmd;
+logic                                               tcm_imem_cmd;
 logic [`SCR1_IMEM_AWIDTH-1:0]                       tcm_imem_addr;
 logic [`SCR1_IMEM_DWIDTH-1:0]                       tcm_imem_rdata;
-type_scr1_mem_resp_e                                tcm_imem_resp;
+logic [1:0]                                         tcm_imem_resp;
 
 // Data memory interface from router to TCM
 logic                                               tcm_dmem_req_ack;
 logic                                               tcm_dmem_req;
-type_scr1_mem_cmd_e                                 tcm_dmem_cmd;
-type_scr1_mem_width_e                               tcm_dmem_width;
+logic                                               tcm_dmem_cmd;
+logic [1:0]                                         tcm_dmem_width;
 logic [`SCR1_DMEM_AWIDTH-1:0]                       tcm_dmem_addr;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       tcm_dmem_wdata;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       tcm_dmem_rdata;
-type_scr1_mem_resp_e                                tcm_dmem_resp;
+logic [1:0]                                         tcm_dmem_resp;
 `endif // SCR1_TCM_EN
 
 // Data memory interface from router to memory-mapped timer
 logic                                               timer_dmem_req_ack;
 logic                                               timer_dmem_req;
-type_scr1_mem_cmd_e                                 timer_dmem_cmd;
-type_scr1_mem_width_e                               timer_dmem_width;
+logic                                               timer_dmem_cmd;
+logic [1:0]                                         timer_dmem_width;
 logic [`SCR1_DMEM_AWIDTH-1:0]                       timer_dmem_addr;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       timer_dmem_wdata;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       timer_dmem_rdata;
-type_scr1_mem_resp_e                                timer_dmem_resp;
+logic [1:0]                                         timer_dmem_resp;
 
 logic                                               timer_irq;
 logic [63:0]                                        timer_val;
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv
index 735b902..bbcc30d 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv
@@ -168,68 +168,68 @@
 // Instruction memory interface from core to router
 logic                                               core_imem_req_ack;
 logic                                               core_imem_req;
-type_scr1_mem_cmd_e                                 core_imem_cmd;
+logic                                               core_imem_cmd;
 logic [`SCR1_IMEM_AWIDTH-1:0]                       core_imem_addr;
 logic [`SCR1_IMEM_DWIDTH-1:0]                       core_imem_rdata;
-type_scr1_mem_resp_e                                core_imem_resp;
+logic [1:0]                                         core_imem_resp;
 
 // Data memory interface from core to router
 logic                                               core_dmem_req_ack;
 logic                                               core_dmem_req;
-type_scr1_mem_cmd_e                                 core_dmem_cmd;
-type_scr1_mem_width_e                               core_dmem_width;
+logic                                               core_dmem_cmd;
+logic [1:0]                                         core_dmem_width;
 logic [`SCR1_DMEM_AWIDTH-1:0]                       core_dmem_addr;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       core_dmem_wdata;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       core_dmem_rdata;
-type_scr1_mem_resp_e                                core_dmem_resp;
+logic [1:0]                                         core_dmem_resp;
 
 // Instruction memory interface from router to AXI bridge
 logic                                               axi_imem_req_ack;
 logic                                               axi_imem_req;
-type_scr1_mem_cmd_e                                 axi_imem_cmd;
+logic                                               axi_imem_cmd;
 logic [`SCR1_IMEM_AWIDTH-1:0]                       axi_imem_addr;
 logic [`SCR1_IMEM_DWIDTH-1:0]                       axi_imem_rdata;
-type_scr1_mem_resp_e                                axi_imem_resp;
+logic [1:0]                                         axi_imem_resp;
 
 // Data memory interface from router to AXI bridge
 logic                                               axi_dmem_req_ack;
 logic                                               axi_dmem_req;
-type_scr1_mem_cmd_e                                 axi_dmem_cmd;
-type_scr1_mem_width_e                               axi_dmem_width;
+logic                                               axi_dmem_cmd;
+logic [1:0]                                         axi_dmem_width;
 logic [`SCR1_DMEM_AWIDTH-1:0]                       axi_dmem_addr;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       axi_dmem_wdata;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       axi_dmem_rdata;
-type_scr1_mem_resp_e                                axi_dmem_resp;
+logic [1:0]                                         axi_dmem_resp;
 
 `ifdef SCR1_TCM_EN
 // Instruction memory interface from router to TCM
 logic                                               tcm_imem_req_ack;
 logic                                               tcm_imem_req;
-type_scr1_mem_cmd_e                                 tcm_imem_cmd;
+logic                                               tcm_imem_cmd;
 logic [`SCR1_IMEM_AWIDTH-1:0]                       tcm_imem_addr;
 logic [`SCR1_IMEM_DWIDTH-1:0]                       tcm_imem_rdata;
-type_scr1_mem_resp_e                                tcm_imem_resp;
+logic [1:0]                                         tcm_imem_resp;
 
 // Data memory interface from router to TCM
 logic                                               tcm_dmem_req_ack;
 logic                                               tcm_dmem_req;
-type_scr1_mem_cmd_e                                 tcm_dmem_cmd;
-type_scr1_mem_width_e                               tcm_dmem_width;
+logic                                               tcm_dmem_cmd;
+logic [1:0]                                         tcm_dmem_width;
 logic [`SCR1_DMEM_AWIDTH-1:0]                       tcm_dmem_addr;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       tcm_dmem_wdata;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       tcm_dmem_rdata;
-type_scr1_mem_resp_e                                tcm_dmem_resp;
+logic [1:0]                                         tcm_dmem_resp;
 `endif // SCR1_TCM_EN
 
 // Data memory interface from router to memory-mapped timer
 logic                                               timer_dmem_req_ack;
 logic                                               timer_dmem_req;
-type_scr1_mem_cmd_e                                 timer_dmem_cmd;
-type_scr1_mem_width_e                               timer_dmem_width;
+logic                                               timer_dmem_cmd;
+logic [1:0]                                         timer_dmem_width;
 logic [`SCR1_DMEM_AWIDTH-1:0]                       timer_dmem_addr;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       timer_dmem_wdata;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       timer_dmem_rdata;
-type_scr1_mem_resp_e                                timer_dmem_resp;
+logic [1:0]                                         timer_dmem_resp;
 
 // Misc
 logic                                               timer_irq;
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
index 87e6607..97f565c 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
@@ -144,68 +144,68 @@
 // Instruction memory interface from core to router
 logic                                               core_imem_req_ack;
 logic                                               core_imem_req;
-type_scr1_mem_cmd_e                                 core_imem_cmd;
+logic                                               core_imem_cmd;
 logic [`SCR1_IMEM_AWIDTH-1:0]                       core_imem_addr;
 logic [`SCR1_IMEM_DWIDTH-1:0]                       core_imem_rdata;
-type_scr1_mem_resp_e                                core_imem_resp;
+logic [1:0]                                         core_imem_resp;
 
 // Data memory interface from core to router
 logic                                               core_dmem_req_ack;
 logic                                               core_dmem_req;
-type_scr1_mem_cmd_e                                 core_dmem_cmd;
-type_scr1_mem_width_e                               core_dmem_width;
+logic                                               core_dmem_cmd;
+logic [1:0]                                         core_dmem_width;
 logic [`SCR1_DMEM_AWIDTH-1:0]                       core_dmem_addr;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       core_dmem_wdata;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       core_dmem_rdata;
-type_scr1_mem_resp_e                                core_dmem_resp;
+logic [1:0]                                         core_dmem_resp;
 
 // Instruction memory interface from router to WB bridge
 logic                                               wb_imem_req_ack;
 logic                                               wb_imem_req;
-type_scr1_mem_cmd_e                                 wb_imem_cmd;
+logic                                               wb_imem_cmd;
 logic [`SCR1_IMEM_AWIDTH-1:0]                       wb_imem_addr;
 logic [`SCR1_IMEM_DWIDTH-1:0]                       wb_imem_rdata;
-type_scr1_mem_resp_e                                wb_imem_resp;
+logic [1:0]                                         wb_imem_resp;
 
 // Data memory interface from router to WB bridge
 logic                                               wb_dmem_req_ack;
 logic                                               wb_dmem_req;
-type_scr1_mem_cmd_e                                 wb_dmem_cmd;
-type_scr1_mem_width_e                               wb_dmem_width;
+logic                                               wb_dmem_cmd;
+logic [1:0]                                         wb_dmem_width;
 logic [`SCR1_DMEM_AWIDTH-1:0]                       wb_dmem_addr;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       wb_dmem_wdata;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       wb_dmem_rdata;
-type_scr1_mem_resp_e                                wb_dmem_resp;
+logic [1:0]                                         wb_dmem_resp;
 
 `ifdef SCR1_TCM_EN
 // Instruction memory interface from router to TCM
 logic                                               tcm_imem_req_ack;
 logic                                               tcm_imem_req;
-type_scr1_mem_cmd_e                                 tcm_imem_cmd;
+logic                                               tcm_imem_cmd;
 logic [`SCR1_IMEM_AWIDTH-1:0]                       tcm_imem_addr;
 logic [`SCR1_IMEM_DWIDTH-1:0]                       tcm_imem_rdata;
-type_scr1_mem_resp_e                                tcm_imem_resp;
+logic [1:0]                                         tcm_imem_resp;
 
 // Data memory interface from router to TCM
 logic                                               tcm_dmem_req_ack;
 logic                                               tcm_dmem_req;
-type_scr1_mem_cmd_e                                 tcm_dmem_cmd;
-type_scr1_mem_width_e                               tcm_dmem_width;
+logic                                               tcm_dmem_cmd;
+logic [1:0]                                         tcm_dmem_width;
 logic [`SCR1_DMEM_AWIDTH-1:0]                       tcm_dmem_addr;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       tcm_dmem_wdata;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       tcm_dmem_rdata;
-type_scr1_mem_resp_e                                tcm_dmem_resp;
+logic [1:0]                                         tcm_dmem_resp;
 `endif // SCR1_TCM_EN
 
 // Data memory interface from router to memory-mapped timer
 logic                                               timer_dmem_req_ack;
 logic                                               timer_dmem_req;
-type_scr1_mem_cmd_e                                 timer_dmem_cmd;
-type_scr1_mem_width_e                               timer_dmem_width;
+logic                                               timer_dmem_cmd;
+logic [1:0]                                         timer_dmem_width;
 logic [`SCR1_DMEM_AWIDTH-1:0]                       timer_dmem_addr;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       timer_dmem_wdata;
 logic [`SCR1_DMEM_DWIDTH-1:0]                       timer_dmem_rdata;
-type_scr1_mem_resp_e                                timer_dmem_resp;
+logic [1:0]                                         timer_dmem_resp;
 
 logic                                               timer_irq;
 logic [63:0]                                        timer_val;
@@ -474,7 +474,7 @@
     .port1_width    (                    ),
     .port1_addr     (                    ),
     .port1_wdata    (                    ),
-    .port1_rdata    ('0                  ),
+    .port1_rdata    (32'h0               ),
     .port1_resp     (SCR1_MEM_RESP_RDY_ER),
 `endif // SCR1_TCM_EN
     // Interface to memory-mapped timer
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..b97154e 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -24,5 +24,59 @@
     `include "gl/user_proj_example.v"
 `else
     `include "user_project_wrapper.v"
-    `include "user_proj_example.v"
-`endif
\ No newline at end of file
+    `include "spi_master/src/spim_top.sv"
+    `include "spi_master/src/spim_regs.sv"
+    `include "spi_master/src/spim_clkgen.sv"
+    `include "spi_master/src/spim_ctrl.sv"
+    `include "spi_master/src/spim_rx.sv"
+    `include "spi_master/src/spim_tx.sv"
+
+     `include "sdram_ctrl/src/top/sdrc_top.v" 
+     `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v" 
+     `include "lib/async_fifo.sv"  
+     `include "sdram_ctrl/src/core/sdrc_core.v"
+     `include "sdram_ctrl/src/core/sdrc_bank_ctl.v"
+     `include "sdram_ctrl/src/core/sdrc_bank_fsm.v"
+     `include "sdram_ctrl/src/core/sdrc_bs_convert.v"
+     `include "sdram_ctrl/src/core/sdrc_req_gen.v"
+     `include "sdram_ctrl/src/core/sdrc_xfr_ctl.v"
+
+     `include "lib/registers.v"
+     `include "lib/clk_ctl.v"
+     `include "digital_core/src/glbl_cfg.sv"
+     `include "digital_core/src/digital_core.sv"
+
+     `include "wb_interconnect/src/wb_arb.sv"
+     `include "wb_interconnect/src/wb_interconnect.sv"
+
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
+     `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
+     `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
+     `include "syntacore/scr1/src/core/scr1_clk_ctrl.sv"
+     `include "syntacore/scr1/src/core/scr1_tapc_shift_reg.sv"
+     `include "syntacore/scr1/src/core/scr1_tapc.sv"
+     `include "syntacore/scr1/src/core/scr1_tapc_synchronizer.sv"
+     `include "syntacore/scr1/src/core/scr1_core_top.sv"
+     `include "syntacore/scr1/src/core/scr1_dm.sv"
+     `include "syntacore/scr1/src/core/scr1_dmi.sv"
+     `include "syntacore/scr1/src/core/scr1_scu.sv"
+      
+     `include "syntacore/scr1/src/top/scr1_dmem_router.sv"
+     `include "syntacore/scr1/src/top/scr1_dp_memory.sv"
+     `include "syntacore/scr1/src/top/scr1_tcm.sv"
+     `include "syntacore/scr1/src/top/scr1_timer.sv"
+     `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
+     `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
+     `include "syntacore/scr1/src/top/scr1_top_wb.sv"
+     `include "lib/sync_fifo.sv"
+`endif
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 2a3462b..0ff3294 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -28,7 +28,7 @@
  *
  *-------------------------------------------------------------
  */
-
+`default_nettype wire
 module user_project_wrapper #(
     parameter BITS = 32
 ) (
@@ -78,11 +78,12 @@
     output [2:0] user_irq
 );
 
+
 /*--------------------------------------*/
 /* User project is instantiated  here   */
 /*--------------------------------------*/
 
-user_proj_example mprj (
+digital_core u_core (
     `ifdef USE_POWER_PINS
 	.vdda1(vdda1),	// User area 1 3.3V power
 	.vdda2(vdda2),	// User area 2 3.3V power
@@ -94,19 +95,21 @@
 	.vssd2(vssd2),	// User area 2 digital ground
     `endif
 
-    .wb_clk_i(wb_clk_i),
-    .wb_rst_i(wb_rst_i),
+    .clk(wb_clk_i),
+    .rst_n(!wb_rst_i),
+    .rtc_clk(user_clock2),
 
     // MGMT SoC Wishbone Slave
 
-    .wbs_cyc_i(wbs_cyc_i),
-    .wbs_stb_i(wbs_stb_i),
-    .wbs_we_i(wbs_we_i),
-    .wbs_sel_i(wbs_sel_i),
-    .wbs_adr_i(wbs_adr_i),
-    .wbs_dat_i(wbs_dat_i),
-    .wbs_ack_o(wbs_ack_o),
-    .wbs_dat_o(wbs_dat_o),
+    .wbd_ext_cyc_i(wbs_cyc_i),
+    .wbd_ext_stb_i(wbs_stb_i),
+    .wbd_ext_we_i(wbs_we_i),
+    .wbd_ext_sel_i(wbs_sel_i),
+    .wbd_ext_adr_i(wbs_adr_i),
+    .wbd_ext_dat_i(wbs_dat_i),
+    .wbd_ext_ack_o(wbs_ack_o),
+    .wbd_ext_dat_o(wbs_dat_o),
+    .wbd_ext_err_o(),
 
     // Logic Analyzer
 
diff --git a/verilog/rtl/wb_interconnect/src/wb_arb.sv b/verilog/rtl/wb_interconnect/src/wb_arb.sv
new file mode 100644
index 0000000..b127d5c
--- /dev/null
+++ b/verilog/rtl/wb_interconnect/src/wb_arb.sv
@@ -0,0 +1,117 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Wishbone Arbitor                                            ////
+////                                                              ////
+////  This file is part of the YIFive cores project               ////
+////  http://www.opencores.org/cores/yifive/                      ////
+////                                                              ////
+////  Description                                                 ////
+////      This block implement simple round robine request        ////
+//        arbitor for wishbone interface.                         ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 12th June 2021, Dinesh A                            ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+
+module wb_arb(clk, rstn, req, gnt);
+
+input		clk;
+input		rstn;
+input	[2:0]	req;	// Req input
+output	[1:0]	gnt; 	// Grant output
+
+///////////////////////////////////////////////////////////////////////
+//
+// Parameters
+//
+
+
+parameter	[1:0]
+                grant0 = 3'h0,
+                grant1 = 3'h1,
+                grant2 = 3'h2;
+
+///////////////////////////////////////////////////////////////////////
+// Local Registers and Wires
+//////////////////////////////////////////////////////////////////////
+
+reg [1:0]	state, next_state;
+
+///////////////////////////////////////////////////////////////////////
+//  Misc Logic 
+//////////////////////////////////////////////////////////////////////
+
+assign	gnt = state;
+
+always@(posedge clk or negedge rstn)
+	if(!rstn)       state <= grant0;
+	else		state <= next_state;
+
+///////////////////////////////////////////////////////////////////////
+//
+// Next State Logic 
+//   - implements round robin arbitration algorithm
+//   - switches grant if current req is dropped or next is asserted
+//   - parks at last grant
+//////////////////////////////////////////////////////////////////////
+
+always@(state or req )
+   begin
+      next_state = state;	// Default Keep State
+      case(state)		
+         grant0:
+      	// if this req is dropped or next is asserted, check for other req's
+      	if(!req[0] ) begin
+      		if(req[1])	next_state = grant1;
+      		else if(req[2])	next_state = grant2;
+      	end
+         grant1:
+      	// if this req is dropped or next is asserted, check for other req's
+      	if(!req[1] ) begin
+      		if(req[2])	next_state = grant2;
+      		else if(req[0])	next_state = grant0;
+      	end
+         grant2:
+      	// if this req is dropped or next is asserted, check for other req's
+      	if(!req[2] ) begin
+      	   if(req[0])	next_state = grant0;
+      	   else if(req[1])	next_state = grant1;
+      	end
+      endcase
+   end
+
+endmodule 
+
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
new file mode 100644
index 0000000..d626b95
--- /dev/null
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -0,0 +1,303 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Wishbone Interconnect                                       ////
+////                                                              ////
+////  This file is part of the YIFive cores project               ////
+////  http://www.opencores.org/cores/yifive/                      ////
+////                                                              ////
+////  Description                                                 ////
+////	1. 3 masters and 3 slaves share bus Wishbone connection   ////
+////	2. This block implement simple round robine request       ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 12th June 2021, Dinesh A                            ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+
+
+module wb_interconnect(
+         input logic		clk_i, 
+         input logic            rst_n,
+         
+         // Master 0 Interface
+         input   logic	[31:0]	m0_wbd_dat_i,
+         input   logic  [31:0]	m0_wbd_adr_i,
+         input   logic  [3:0]	m0_wbd_sel_i,
+         input   logic  	m0_wbd_we_i,
+         input   logic  	m0_wbd_cyc_i,
+         input   logic  	m0_wbd_stb_i,
+         input   logic [3:0] 	m0_wbd_tid_i, // target id
+         output  logic	[31:0]	m0_wbd_dat_o,
+         output  logic		m0_wbd_ack_o,
+         output  logic		m0_wbd_err_o,
+         
+         // Master 1 Interface
+         input	logic [31:0]	m1_wbd_dat_i,
+         input	logic [31:0]	m1_wbd_adr_i,
+         input	logic [3:0]	m1_wbd_sel_i,
+         input	logic 	        m1_wbd_we_i,
+         input	logic 	        m1_wbd_cyc_i,
+         input	logic 	        m1_wbd_stb_i,
+         input  logic [3:0] 	m1_wbd_tid_i, // target id
+         output	logic [31:0]	m1_wbd_dat_o,
+         output	logic 	        m1_wbd_ack_o,
+         output	logic 	        m1_wbd_err_o,
+         
+         // Master 2 Interface
+         input	logic [31:0]	m2_wbd_dat_i,
+         input	logic [31:0]	m2_wbd_adr_i,
+         input	logic [3:0]	m2_wbd_sel_i,
+         input	logic 	        m2_wbd_we_i,
+         input	logic 	        m2_wbd_cyc_i,
+         input	logic 	        m2_wbd_stb_i,
+         input  logic [3:0] 	m2_wbd_tid_i, // target id
+         output	logic [31:0]	m2_wbd_dat_o,
+         output	logic 	        m2_wbd_ack_o,
+         output	logic 	        m2_wbd_err_o,
+         
+         
+         // Slave 0 Interface
+         input	logic [31:0]	s0_wbd_dat_i,
+         input	logic 	        s0_wbd_ack_i,
+         input	logic 	        s0_wbd_err_i,
+         output	logic [31:0]	s0_wbd_dat_o,
+         output	logic [31:0]	s0_wbd_adr_o,
+         output	logic [3:0]	s0_wbd_sel_o,
+         output	logic 	        s0_wbd_we_o,
+         output	logic 	        s0_wbd_cyc_o,
+         output	logic 	        s0_wbd_stb_o,
+         
+         // Slave 1 Interface
+         input	logic [31:0]	s1_wbd_dat_i,
+         input	logic 	        s1_wbd_ack_i,
+         input	logic 	        s1_wbd_err_i,
+         output	logic [31:0]	s1_wbd_dat_o,
+         output	logic [31:0]	s1_wbd_adr_o,
+         output	logic [3:0]	s1_wbd_sel_o,
+         output	logic 	        s1_wbd_we_o,
+         output	logic 	        s1_wbd_cyc_o,
+         output	logic 	        s1_wbd_stb_o,
+         
+         // Slave 2 Interface
+         input	logic [31:0]	s2_wbd_dat_i,
+         input	logic 	        s2_wbd_ack_i,
+         input	logic 	        s2_wbd_err_i,
+         output	logic [31:0]	s2_wbd_dat_o,
+         output	logic [31:0]	s2_wbd_adr_o,
+         output	logic [3:0]	s2_wbd_sel_o,
+         output	logic 	        s2_wbd_we_o,
+         output	logic 	        s2_wbd_cyc_o,
+         output	logic 	        s2_wbd_stb_o
+	);
+
+////////////////////////////////////////////////////////////////////
+//
+// Type define
+//
+
+
+// WishBone Wr Interface
+typedef struct packed { 
+  logic	[31:0]	wbd_dat;
+  logic  [31:0]	wbd_adr;
+  logic  [3:0]	wbd_sel;
+  logic  	wbd_we;
+  logic  	wbd_cyc;
+  logic  	wbd_stb;
+  logic [3:0] 	wbd_tid; // target id
+} type_wb_wr_intf;
+
+// WishBone Rd Interface
+typedef struct packed { 
+  logic	[31:0]	wbd_dat;
+  logic  	wbd_ack;
+  logic  	wbd_err;
+} type_wb_rd_intf;
+
+
+// Master Write Interface
+type_wb_wr_intf  m0_wb_wr;
+type_wb_wr_intf  m1_wb_wr;
+type_wb_wr_intf  m2_wb_wr;
+
+// Master Read Interface
+type_wb_rd_intf  m0_wb_rd;
+type_wb_rd_intf  m1_wb_rd;
+type_wb_rd_intf  m2_wb_rd;
+
+// Slave Write Interface
+type_wb_wr_intf  s0_wb_wr;
+type_wb_wr_intf  s1_wb_wr;
+type_wb_wr_intf  s2_wb_wr;
+
+// Slave Read Interface
+type_wb_rd_intf  s0_wb_rd;
+type_wb_rd_intf  s1_wb_rd;
+type_wb_rd_intf  s2_wb_rd;
+
+
+type_wb_wr_intf  i_bus_m;  // Multiplexed Master I/F
+type_wb_rd_intf  i_bus_s;  // Multiplexed Slave I/F
+
+
+//----------------------------------------
+// Master Mapping
+// -------------------------------------
+assign m0_wb_wr.wbd_dat = m0_wbd_dat_i;
+assign m0_wb_wr.wbd_adr = m0_wbd_adr_i;
+assign m0_wb_wr.wbd_sel = m0_wbd_sel_i;
+assign m0_wb_wr.wbd_we  = m0_wbd_we_i;
+assign m0_wb_wr.wbd_cyc = m0_wbd_cyc_i;
+assign m0_wb_wr.wbd_stb = m0_wbd_stb_i;
+assign m0_wb_wr.wbd_tid = m0_wbd_tid_i;
+
+assign m1_wb_wr.wbd_dat = m1_wbd_dat_i;
+assign m1_wb_wr.wbd_adr = m1_wbd_adr_i;
+assign m1_wb_wr.wbd_sel = m1_wbd_sel_i;
+assign m1_wb_wr.wbd_we  = m1_wbd_we_i;
+assign m1_wb_wr.wbd_cyc = m1_wbd_cyc_i;
+assign m1_wb_wr.wbd_stb = m1_wbd_stb_i;
+assign m1_wb_wr.wbd_tid = m1_wbd_tid_i;
+
+assign m2_wb_wr.wbd_dat = m2_wbd_dat_i;
+assign m2_wb_wr.wbd_adr = m2_wbd_adr_i;
+assign m2_wb_wr.wbd_sel = m2_wbd_sel_i;
+assign m2_wb_wr.wbd_we  = m2_wbd_we_i;
+assign m2_wb_wr.wbd_cyc = m2_wbd_cyc_i;
+assign m2_wb_wr.wbd_stb = m2_wbd_stb_i;
+assign m2_wb_wr.wbd_tid = m2_wbd_tid_i;
+
+assign m0_wbd_dat_o  =  m0_wb_rd.wbd_dat;
+assign m0_wbd_ack_o  =  m0_wb_rd.wbd_ack;
+assign m0_wbd_err_o  =  m0_wb_rd.wbd_err;
+
+assign m1_wbd_dat_o  =  m1_wb_rd.wbd_dat;
+assign m1_wbd_ack_o  =  m1_wb_rd.wbd_ack;
+assign m1_wbd_err_o  =  m1_wb_rd.wbd_err;
+
+assign m2_wbd_dat_o  =  m2_wb_rd.wbd_dat;
+assign m2_wbd_ack_o  =  m2_wb_rd.wbd_ack;
+assign m2_wbd_err_o  =  m2_wb_rd.wbd_err;
+
+assign s0_wb_rd.wbd_dat  = s0_wbd_dat_i ;
+assign s0_wb_rd.wbd_ack  = s0_wbd_ack_i ;
+assign s0_wb_rd.wbd_err  = s0_wbd_err_i ;
+
+assign s1_wb_rd.wbd_dat  = s1_wbd_dat_i ;
+assign s1_wb_rd.wbd_ack  = s1_wbd_ack_i ;
+assign s1_wb_rd.wbd_err  = s1_wbd_err_i ;
+
+assign s2_wb_rd.wbd_dat  = s2_wbd_dat_i ;
+assign s2_wb_rd.wbd_ack  = s2_wbd_ack_i ;
+assign s2_wb_rd.wbd_err  = s2_wbd_err_i ;
+
+
+//----------------------------------------
+// Slave Mapping
+// -------------------------------------
+
+assign  s0_wbd_dat_o =  s0_wb_wr.wbd_dat ;
+assign  s0_wbd_adr_o =  s0_wb_wr.wbd_adr ;
+assign  s0_wbd_sel_o =  s0_wb_wr.wbd_sel ;
+assign  s0_wbd_we_o  =  s0_wb_wr.wbd_we  ;
+assign  s0_wbd_cyc_o =  s0_wb_wr.wbd_cyc ;
+assign  s0_wbd_stb_o =  s0_wb_wr.wbd_stb ;
+                     
+assign  s1_wbd_dat_o =  s1_wb_wr.wbd_dat ;
+assign  s1_wbd_adr_o =  s1_wb_wr.wbd_adr ;
+assign  s1_wbd_sel_o =  s1_wb_wr.wbd_sel ;
+assign  s1_wbd_we_o  =  s1_wb_wr.wbd_we  ;
+assign  s1_wbd_cyc_o =  s1_wb_wr.wbd_cyc ;
+assign  s1_wbd_stb_o =  s1_wb_wr.wbd_stb ;
+                     
+assign  s2_wbd_dat_o =  s2_wb_wr.wbd_dat ;
+assign  s2_wbd_adr_o =  s2_wb_wr.wbd_adr ;
+assign  s2_wbd_sel_o =  s2_wb_wr.wbd_sel ;
+assign  s2_wbd_we_o  =  s2_wb_wr.wbd_we  ;
+assign  s2_wbd_cyc_o =  s2_wb_wr.wbd_cyc ;
+assign  s2_wbd_stb_o =  s2_wb_wr.wbd_stb ;
+
+//
+// arbitor 
+//
+logic [1:0]  gnt;
+
+wb_arb	u_wb_arb(
+	.clk(clk_i), 
+	.rstn(rst_n),
+	.req({	m2_wbd_cyc_i,
+		m1_wbd_cyc_i,
+		m0_wbd_cyc_i}),
+	.gnt(gnt)
+);
+
+
+// Generate Multiplexed Master Interface based on grant
+always_comb begin
+     case(gnt)
+        3'h0:	   i_bus_m = m0_wb_wr;
+        3'h1:	   i_bus_m = m1_wb_wr;
+        3'h2:	   i_bus_m = m2_wb_wr;
+        default:   i_bus_m = m0_wb_wr;
+     endcase			
+end
+
+
+// Generate Multiplexed Slave Interface based on target Id
+wire [3:0] wbd_tid =  i_bus_m.wbd_tid; // to fix iverilog warning
+always_comb begin
+     case(wbd_tid)
+        3'h0:	   i_bus_s = s0_wb_rd;
+        3'h1:	   i_bus_s = s1_wb_rd;
+        3'h2:	   i_bus_s = s2_wb_rd;
+        default:   i_bus_s = s0_wb_rd;
+     endcase			
+end
+
+
+// Connect Master => Slave
+assign  s0_wb_wr = (i_bus_m.wbd_tid == 2'b00) ? i_bus_m : 'h0;
+assign  s1_wb_wr = (i_bus_m.wbd_tid == 2'b01) ? i_bus_m : 'h0;
+assign  s2_wb_wr = (i_bus_m.wbd_tid == 2'b10) ? i_bus_m : 'h0;
+
+// Connect Slave to Master
+assign  m0_wb_rd = (gnt == 2'b00) ? i_bus_s : 'h0;
+assign  m1_wb_rd = (gnt == 2'b01) ? i_bus_s : 'h0;
+assign  m2_wb_rd = (gnt == 2'b10) ? i_bus_s : 'h0;
+
+
+
+endmodule
+