diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index e987bbf..ed2fa74 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -22,13 +22,18 @@
 CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
 CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
 
+
 ## User Project Pointers
 UPRJ_VERILOG_PATH ?= ../../../verilog
 UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
 UPRJ_BEHAVIOURAL_MODELS = ../model
+UPRJ_BEHAVIOURAL_AGENTS = ../agents
 UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
 UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
-UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
+
+## SYNTACORE FIRMWARE
+SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+GCC64_PREFIX?=riscv64-unknown-elf
 
 ## RISCV GCC 
 GCC_PATH?=/ef/apps/bin
@@ -49,16 +54,24 @@
 vvp:  ${PATTERN:=.vvp}
 
 %.vvp: %_tb.v %.hex
+	${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(SYNTACORE_FIRMWARE_PATH)  user_uart.c -o user_uart.o
+	${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I$(SYNTACORE_FIRMWARE_PATH)  $(SYNTACORE_FIRMWARE_PATH)/crt_tcm.S -o crt_tcm.o
+	${GCC64_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -T $(SYNTACORE_FIRMWARE_PATH)/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -o user_uart.elf
+	${GCC64_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex
+	${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump
+	rm crt_tcm.o user_uart.o
 ifeq ($(SIM),RTL)
 	iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
 	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
 	$< -o $@ 
 else  
 	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
 	$< -o $@ 
 endif
 
@@ -79,6 +92,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
 
 .PHONY: clean hex all
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c
index f0d8010..1ceec26 100644
--- a/verilog/dv/risc_boot/risc_boot.c
+++ b/verilog/dv/risc_boot/risc_boot.c
@@ -39,6 +39,15 @@
 #define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038)
 #define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C)
 
+#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x30010000)
+#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x30010004)
+#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x30010008)
+#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x3001000C)
+#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x30010010)
+#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x30010014)
+#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x30010018)
+#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x3001001C)
+#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x30010020)
 
 #define GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP   0x1C00
 
@@ -168,45 +177,7 @@
     // Wake Up CPU Core
     reg_mprj_globl_reg0  = 0x07; 
 
-    // Add some delay for user core to boot
-    for(i = 0; i < 40; i ++);
+    // configure the user uart
+    reg_mprj_uart_reg0  = 0x7;
 
-    if(reg_mprj_globl_reg6  != 0x11223344) bFail = 1;
-    if(reg_mprj_globl_reg7  != 0x22334455) bFail = 1;
-    if(reg_mprj_globl_reg8  != 0x33445566) bFail = 1;
-    if(reg_mprj_globl_reg9  != 0x44556677) bFail = 1;
-    if(reg_mprj_globl_reg10 != 0x55667788) bFail = 1;
-    if(reg_mprj_globl_reg11 != 0x66778899) bFail = 1;
-
-
-    if(bFail == 0) {
-        reg_mprj_datal = 0xAB610000;
-    } else {
-        reg_mprj_datal = 0xAB600000;
-    }
-
-	// Connect the housekeeping SPI to the SPI master
-	// so that the CSB line is not left floating.  This allows
-	// all of the GPIO pins to be used for user functions.
-        reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-
-     /* Apply configuration */
-    reg_mprj_xfer = 1;
-    while (reg_mprj_xfer == 1);
 }
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index fe5a499..2777eaf 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -58,6 +58,7 @@
 `include "caravel_netlists.v"
 `include "spiflash.v"
 `include "mt48lc8m8a2.v"
+`include "uart_agent.v"
 
 module risc_boot_tb;
 	reg clock;
@@ -71,6 +72,28 @@
 	wire [7:0] mprj_io_0;
 	wire [15:0] checkbits;
 
+        //----------------------------------
+        // Uart Configuration
+        // ---------------------------------
+        reg [1:0]      uart_data_bit        ;
+        reg	       uart_stop_bits       ; // 0: 1 stop bit; 1: 2 stop bit;
+        reg	       uart_stick_parity    ; // 1: force even parity
+        reg	       uart_parity_en       ; // parity enable
+        reg	       uart_even_odd_parity ; // 0: odd parity; 1: even parity
+        
+        reg [7:0]      uart_data            ;
+        reg [15:0]     uart_divisor         ;	// divided by n * 16
+        reg [15:0]     uart_timeout         ;// wait time limit
+        
+        reg [15:0]     uart_rx_nu           ;
+        reg [15:0]     uart_tx_nu           ;
+        reg [7:0]      uart_write_data [0:39];
+        reg 	       uart_fifo_enable     ;	// fifo mode disable
+	reg            test_fail            ;
+        
+        integer i,j;
+	//---------------------------------
+	
 	assign checkbits = mprj_io[31:16];
 
 	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
@@ -97,36 +120,84 @@
         end
         `endif
 
-	initial begin
 
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (200) begin
-			repeat (1000) @(posedge clock);
-			// $display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		`ifdef GL
-			$display ("Monitor: Timeout, Test user Risc Boot (GL) Failed");
-		`else
-			$display ("Monitor: Timeout, Test user Risc Boot (RTL) Failed");
-		`endif
-		$display("%c[0m",27);
-		$finish;
-	end
-
-	initial begin
+        initial
+        begin
+           uart_data_bit           = 2'b11;
+           uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
+           uart_stick_parity       = 0; // 1: force even parity
+           uart_parity_en          = 0; // parity enable
+           uart_even_odd_parity    = 1; // 0: odd parity; 1: even parity
+           uart_divisor            = 15;// divided by n * 16
+           uart_timeout            = 500;// wait time limit
+           uart_fifo_enable        = 0;	// fifo mode disable
+        
+           #200; // Wait for reset removal
+          
+	   // Wait for Managment core to boot up 
 	   wait(checkbits == 16'h AB60);
-		$display("Monitor: Test User Risc Boot Started");
-		wait(checkbits == 16'h AB61);
-	    	$display("#############################################");
-		`ifdef GL
-	    	$display("Monitor: Test User Risc Boot (GL) Passed");
-		`else
-		    $display("Monitor: Test User Risc Boot (RTL) Passed");
-		`endif
-	    	$display("#############################################");
-	    $finish;
-	end
+	   $display("Monitor: Test User Risc Boot Started");
+       
+	   // Wait for user risc core to boot up 
+           repeat (35000) @(posedge clock);  
+           tb_uart.uart_init;
+           tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
+        	                          uart_stick_parity, uart_timeout, uart_divisor);
+           
+           for (i=0; i<40; i=i+1)
+           	uart_write_data[i] = $random;
+           
+           
+           
+           fork
+              begin
+                 for (i=0; i<40; i=i+1)
+                 begin
+                   $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]);
+                    tb_uart.write_char (uart_write_data[i]);
+                 end
+              end
+           
+              begin
+                 for (j=0; j<40; j=j+1)
+                 begin
+                   tb_uart.read_char_chk(uart_write_data[j]);
+                 end
+              end
+              join
+           
+              #100
+              tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+           
+              test_fail = 0;
+        
+              // Check 
+              // if all the 40 byte transmitted
+              // if all the 40 byte received
+              // if no error 
+              if(uart_tx_nu != 40) test_fail = 1;
+              if(uart_rx_nu != 40) test_fail = 1;
+              if(tb_uart.err_cnt != 0) test_fail = 1;
+        
+              $display("###################################################");
+              if(test_fail == 0) begin
+                 `ifdef GL
+                     $display("Monitor: Standalone User UART Test (GL) Passed");
+                 `else
+                     $display("Monitor: Standalone User UART Test (RTL) Passed");
+                 `endif
+              end else begin
+                  `ifdef GL
+                      $display("Monitor: Standalone User UART Test (GL) Failed");
+                  `else
+                      $display("Monitor: Standalone User UART Test (RTL) Failed");
+                  `endif
+               end
+              $display("###################################################");
+              #100
+              $finish;
+        end
+
 
 	initial begin
 		RSTB <= 1'b0;
@@ -216,7 +287,7 @@
 
    // Quard flash
 	spiflash #(
-		.FILENAME("user_risc_boot.hex")
+		.FILENAME("user_uart.hex")
 	) u_user_spiflash (
 		.csb(user_flash_csb),
 		.clk(user_flash_clk),
@@ -271,6 +342,22 @@
      );
 
 
+//---------------------------
+//  UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd   = mprj_io[37];
+assign mprj_io[36]  = uart_rxd ;
+ 
+uart_agent tb_uart(
+	.mclk                (clock              ),
+	.txd                 (uart_rxd           ),
+	.rxd                 (uart_txd           )
+	);
+
+
+
 
 /**
 //-----------------------------------------------------------------------------
diff --git a/verilog/dv/risc_boot/user_uart.c b/verilog/dv/risc_boot/user_uart.c
new file mode 100644
index 0000000..cb8c107
--- /dev/null
+++ b/verilog/dv/risc_boot/user_uart.c
@@ -0,0 +1,43 @@
+
+#define SC_SIM_OUTPORT (0xf0000000)
+#define uint32_t  long
+
+#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x30000000)
+#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x30000004)
+#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x30000008)
+#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x3000000C)
+#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x30000010)
+#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x30000014)
+#define reg_mprj_globl_reg6  (*(volatile uint32_t*)0x30000018)
+#define reg_mprj_globl_reg7  (*(volatile uint32_t*)0x3000001C)
+#define reg_mprj_globl_reg8  (*(volatile uint32_t*)0x30000020)
+#define reg_mprj_globl_reg9  (*(volatile uint32_t*)0x30000024)
+#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028)
+#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C)
+#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030)
+#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034)
+#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038)
+#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C)
+
+#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x30010000)
+#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x30010004)
+#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x30010008)
+#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x3001000C)
+#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x30010010)
+#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x30010014)
+#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x30010018)
+#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x3001001C)
+#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x30010020)
+
+int main()
+{
+
+    while(1) {
+       // Check UART RX fifo has data, if available loop back the data
+       if(reg_mprj_uart_reg8 != 0) { 
+	   reg_mprj_uart_reg5 = reg_mprj_uart_reg6;
+       }
+    }
+
+    return 0;
+}
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index f7499c6..d2bccea 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -22,16 +22,22 @@
 CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
 CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
 
+
 ## User Project Pointers
 UPRJ_VERILOG_PATH ?= ../../../verilog
 UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
 UPRJ_BEHAVIOURAL_MODELS = ../model
+UPRJ_BEHAVIOURAL_AGENTS = ../agents
 UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
 UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
 
+## SYNTACORE FIRMWARE
+SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+GCC64_PREFIX?=riscv64-unknown-elf
+
 ## RISCV GCC 
 GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv64-unknown-elf
+GCC_PREFIX?=riscv32-unknown-elf
 PDK_PATH?=/ef/tech/SW/sky130A
 
 ## Simulation mode: RTL/GL
@@ -47,17 +53,25 @@
 
 vvp:  ${PATTERN:=.vvp}
 
-%.vvp: %_tb.v %.hex
+%.vvp: %_tb.v
+	riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common  user_uart.c -o user_uart.o
+	riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/  ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
+	riscv64-unknown-elf-gcc -o user_uart.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32
+	riscv64-unknown-elf-objcopy -O verilog user_uart.elf user_uart.hex
+	riscv64-unknown-elf-objdump -D user_uart.elf > user_uart.dump
+	rm crt_tcm.o user_uart.o
 ifeq ($(SIM),RTL)
 	iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
 	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
 	$< -o $@ 
 else  
 	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
 	$< -o $@ 
 endif
 
@@ -67,10 +81,8 @@
 %.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
 	${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
 
-%.hex: %.elf
-	${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
+%.hex: 
+	echo @"This is user boot test, noting to compile the mangment core code"
 
 %.bin: %.elf
 	${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
@@ -78,6 +90,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
 
 .PHONY: clean hex all
diff --git a/verilog/dv/user_risc_boot/uprj_netlists.v b/verilog/dv/user_risc_boot/uprj_netlists.v
index fe938c1..598170e 100644
--- a/verilog/dv/user_risc_boot/uprj_netlists.v
+++ b/verilog/dv/user_risc_boot/uprj_netlists.v
@@ -16,12 +16,20 @@
 // Include caravel global defines for the number of the user project IO pads 
 `define USE_POWER_PINS
 
-    `include "spi_master/src/spim_top.sv"
-    `include "spi_master/src/spim_regs.sv"
-    `include "spi_master/src/spim_clkgen.sv"
-    `include "spi_master/src/spim_ctrl.sv"
-    `include "spi_master/src/spim_rx.sv"
-    `include "spi_master/src/spim_tx.sv"
+     `include "spi_master/src/spim_top.sv"
+     `include "spi_master/src/spim_regs.sv"
+     `include "spi_master/src/spim_clkgen.sv"
+     `include "spi_master/src/spim_ctrl.sv"
+     `include "spi_master/src/spim_rx.sv"
+     `include "spi_master/src/spim_tx.sv"
+
+     `include "uart/src/uart_core.sv"
+     `include "uart/src/uart_cfg.sv"
+     `include "uart/src/uart_rxfsm.sv"
+     `include "uart/src/uart_txfsm.sv"
+     `include "lib/async_fifo_th.sv"  
+     `include "lib/reset_sync.sv"  
+     `include "lib/double_sync_low.v"  
 
      `include "sdram_ctrl/src/top/sdrc_top.v" 
      `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v" 
diff --git a/verilog/dv/user_risc_boot/user_risc_boot.hex b/verilog/dv/user_risc_boot/user_risc_boot.hex
deleted file mode 100755
index 5ab43fa..0000000
--- a/verilog/dv/user_risc_boot/user_risc_boot.hex
+++ /dev/null
@@ -1,79 +0,0 @@
-@00000000
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 13 00 00 00 6F 00 00 00 FF FF FF FF
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-6F 00 E0 18 13 00 00 00 13 00 00 00 13 00 00 00
-13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
-13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
-13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
-93 00 00 00 13 01 00 00 93 01 00 00 13 02 00 00
-93 02 00 00 13 03 00 00 93 03 00 00 13 04 00 00
-93 04 00 00 13 05 00 00 93 05 00 00 13 06 00 00
-93 06 00 00 13 07 00 00 93 07 00 00 13 08 00 00
-93 08 00 00 13 09 00 00 93 09 00 00 13 0A 00 00
-93 0A 00 00 13 0B 00 00 93 0B 00 00 13 0C 00 00
-93 0C 00 00 13 0D 00 00 93 0D 00 00 13 0E 00 00
-93 0E 00 00 13 0F 00 00 93 0F 00 00 97 01 00 20
-93 81 41 62 13 05 00 40 97 05 00 20 93 85 85 D7
-17 06 00 20 13 06 06 E3 63 0D B5 00 29 A0 14 41
-94 C1 11 05 91 05 E3 9C C5 FE 17 06 00 20 13 06
-66 E1 97 05 00 20 93 85 E5 E0 21 A0 23 20 06 00
-11 06 E3 9D C5 FE 17 01 01 20 13 01 A1 D3 17 05
-00 20 13 05 25 DF 17 06 00 20 13 06 A6 DE B3 05
-A6 40 17 07 01 20 13 07 E7 91 33 02 B7 40 92 85
-17 06 00 20 13 06 06 DD 29 A0 14 41 94 C1 11 05
-91 05 E3 1C C5 FE 21 A0 23 A0 05 00 91 05 E3 9D
-E5 FE B7 02 49 00 05 43 23 A0 62 00 B7 02 49 00
-91 02 13 03 30 06 23 A0 62 00 B7 02 49 00 C1 02
-7D 53 23 A0 62 00 23 A2 62 00 01 45 81 45 97 02
-00 20 E7 80 22 CC 97 02 00 20 93 82 A2 D1 6D 71
-06 C2 0A C4 0E C6 12 C8 16 CA 1A CC 1E CE 22 D0
-26 D2 2A D4 2E D6 32 D8 36 DA 3A DC 3E DE C2 C0
-C6 C2 CA C4 CE C6 D2 C8 D6 CA DA CC DE CE E2 D0
-E6 D2 EA D4 EE D6 F2 D8 F6 DA FA DC FE DE 73 25
-20 34 F3 25 10 34 0A 86 EF 00 80 04 92 40 22 41
-B2 41 42 42 D2 42 62 43 F2 43 02 54 92 54 22 55
-B2 55 42 56 D2 56 62 57 F2 57 06 48 96 48 26 49
-B6 49 46 4A D6 4A 66 4B F6 4B 06 5C 96 5C 26 5D
-B6 5D 46 5E D6 5E 66 5F F6 5F 51 61 73 00 20 30
-6F F0 5F D1 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-@00000400
-37 37 22 11 B7 07 00 30 93 02 47 34 37 43 33 22
-23 AC 57 00 93 03 53 45 37 55 44 33 23 AE 77 00
-93 05 65 56 37 66 55 44 8C D3 93 06 76 67 37 78
-66 55 D4 D3 93 08 88 78 37 9E 77 66 23 A4 17 03
-93 0E 9E 89 23 A6 D7 03 01 A0 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-97 02 00 E0 93 82 42 09 82 82 13 00 00 00 13 00
-00 00 13 00 00 00 13 00 00 00 13 00 00 00 01 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-@000004A0
-13 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index 8009a57..ea56e6b 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -62,7 +62,7 @@
 
 module user_risc_boot_tb;
 	reg clock;
-	reg RSTB;
+	reg wb_rst_i;
 	reg power1, power2;
 	reg power3, power4;
 
@@ -190,9 +190,9 @@
 	end
 
 	initial begin
-		RSTB <= 1'b0;
+		wb_rst_i <= 1'b1;
 		#100;
-		RSTB <= 1'b1;	    	// Release reset
+		wb_rst_i <= 1'b0;	    	// Release reset
 	end
 
 
@@ -208,8 +208,8 @@
     .vssd2(),	// User area 2 digital ground
 `endif
     .wb_clk_i        (clock),  // System clock
-    .rtc_clk         (1'b1),  // Real-time clock
-    .wb_rst_i        (RSTB),  // Regular Reset signal
+    .user_clock2     (1'b1),  // Real-time clock
+    .wb_rst_i        (wb_rst_i),  // Regular Reset signal
 
     .wbd_ext_cyc_i   (wbd_ext_cyc_i),  // strobe/request
     .wbd_ext_stb_i   (wbd_ext_stb_i),  // strobe/request
diff --git a/verilog/dv/user_risc_boot/user_uart.c b/verilog/dv/user_risc_boot/user_uart.c
new file mode 100644
index 0000000..cb8c107
--- /dev/null
+++ b/verilog/dv/user_risc_boot/user_uart.c
@@ -0,0 +1,43 @@
+
+#define SC_SIM_OUTPORT (0xf0000000)
+#define uint32_t  long
+
+#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x30000000)
+#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x30000004)
+#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x30000008)
+#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x3000000C)
+#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x30000010)
+#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x30000014)
+#define reg_mprj_globl_reg6  (*(volatile uint32_t*)0x30000018)
+#define reg_mprj_globl_reg7  (*(volatile uint32_t*)0x3000001C)
+#define reg_mprj_globl_reg8  (*(volatile uint32_t*)0x30000020)
+#define reg_mprj_globl_reg9  (*(volatile uint32_t*)0x30000024)
+#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028)
+#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C)
+#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030)
+#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034)
+#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038)
+#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C)
+
+#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x30010000)
+#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x30010004)
+#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x30010008)
+#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x3001000C)
+#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x30010010)
+#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x30010014)
+#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x30010018)
+#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x3001001C)
+#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x30010020)
+
+int main()
+{
+
+    while(1) {
+       // Check UART RX fifo has data, if available loop back the data
+       if(reg_mprj_uart_reg8 != 0) { 
+	   reg_mprj_uart_reg5 = reg_mprj_uart_reg6;
+       }
+    }
+
+    return 0;
+}
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index 1ec201f..45b15cc 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -22,16 +22,22 @@
 CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
 CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
 
+
 ## User Project Pointers
 UPRJ_VERILOG_PATH ?= ../../../verilog
 UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
 UPRJ_BEHAVIOURAL_MODELS = ../model
+UPRJ_BEHAVIOURAL_AGENTS = ../agents
 UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
 UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
 
+## SYNTACORE FIRMWARE
+SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+GCC64_PREFIX?=riscv64-unknown-elf
+
 ## RISCV GCC 
 GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv64-unknown-elf
+GCC_PREFIX?=riscv32-unknown-elf
 PDK_PATH?=/ef/tech/SW/sky130A
 
 ## Simulation mode: RTL/GL
@@ -47,17 +53,25 @@
 
 vvp:  ${PATTERN:=.vvp}
 
-%.vvp: %_tb.v %.hex
+%.vvp: %_tb.v
+	riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common  user_uart.c -o user_uart.o
+	riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/  ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
+	riscv64-unknown-elf-gcc -o user_uart.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32
+	riscv64-unknown-elf-objcopy -O verilog user_uart.elf user_uart.hex
+	riscv64-unknown-elf-objdump -D user_uart.elf > user_uart.dump
+	rm crt_tcm.o user_uart.o
 ifeq ($(SIM),RTL)
 	iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
 	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
 	$< -o $@ 
 else  
 	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
 	$< -o $@ 
 endif
 
@@ -67,10 +81,8 @@
 %.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
 	${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
 
-%.hex: %.elf
-	${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
+%.hex: 
+	echo @"This is user boot test, noting to compile the mangment core code"
 
 %.bin: %.elf
 	${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
@@ -78,6 +90,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
 
 .PHONY: clean hex all
diff --git a/verilog/dv/user_uart/run_iverilog b/verilog/dv/user_uart/run_iverilog
old mode 100644
new mode 100755
index 6f95c23..16a9f45
--- a/verilog/dv/user_uart/run_iverilog
+++ b/verilog/dv/user_uart/run_iverilog
@@ -11,7 +11,8 @@
 rm crt_tcm.o user_uart.o
 
 #iverilog with waveform dump
-#iverilog -g2005-sv -DWFDUMP -I $PDK_PATH -I ../ -I ../../../verilog/rtl -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $$CARAVEL_ROOT/verilog/dv/caravel -I ../model ../agents user_uart_tb.v -o user_uart_tb.vvp
+#iverilog -g2005-sv -DWFDUMP -I $PDK_PATH -I ../ -I ../../../verilog/rtl -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
+
 
 iverilog -g2005-sv -I $PDK_PATH -I ../ -I ../../../verilog/rtl -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
 
diff --git a/verilog/dv/user_uart/uprj_netlists.v b/verilog/dv/user_uart/uprj_netlists.v
index 0aa46db..598170e 100644
--- a/verilog/dv/user_uart/uprj_netlists.v
+++ b/verilog/dv/user_uart/uprj_netlists.v
@@ -29,6 +29,7 @@
      `include "uart/src/uart_txfsm.sv"
      `include "lib/async_fifo_th.sv"  
      `include "lib/reset_sync.sv"  
+     `include "lib/double_sync_low.v"  
 
      `include "sdram_ctrl/src/top/sdrc_top.v" 
      `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v" 
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 84938f5..fbb254e 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -55,7 +55,7 @@
 
 `default_nettype none
 
-`timescale 1 ns / 1 ps
+`timescale 1 ns / 1 ns
 
 `include "uprj_netlists.v"
 `include "spiflash.v"
@@ -63,26 +63,26 @@
 `include "uart_agent.v"
 
 
-`define ADDR_SPACE_UART = 32'h3001_0000;
+`define ADDR_SPACE_UART  32'h3001_0000
 
 
-task user_uart_tb;
+module user_uart_tb;
 
 reg            clock         ;
-reg            RSTB          ;
+reg            wb_rst_i      ;
 reg            power1, power2;
 reg            power3, power4;
 
-reg            wbd_ext_cyc_i ;  // strobe/request
-reg            wbd_ext_stb_i ;  // strobe/request
-reg [31:0]     wbd_ext_adr_i ;  // address
-reg            wbd_ext_we_i  ;  // write
-reg [31:0]     wbd_ext_dat_i ;  // data output
-reg [3:0]      wbd_ext_sel_i ;  // byte enable
+reg            wbd_ext_cyc_i;  // strobe/request
+reg            wbd_ext_stb_i;  // strobe/request
+reg [31:0]     wbd_ext_adr_i;  // address
+reg            wbd_ext_we_i;  // write
+reg [31:0]     wbd_ext_dat_i;  // data output
+reg [3:0]      wbd_ext_sel_i;  // byte enable
 
-wire [31:0]    wbd_ext_dat_o ;  // data input
-wire           wbd_ext_ack_o ;  // acknowlegement
-wire           wbd_ext_err_o ;  // error
+wire [31:0]    wbd_ext_dat_o;  // data input
+wire           wbd_ext_ack_o;  // acknowlegement
+wire           wbd_ext_err_o;  // error
 
 // User I/O
 wire [37:0]    io_oeb        ;
@@ -113,8 +113,34 @@
 
 integer i,j;
 
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
 
+	always #12.5 clock <= (clock === 1'b0);
 
+	initial begin
+		clock = 0;
+                wbd_ext_cyc_i ='h0;  // strobe/request
+                wbd_ext_stb_i ='h0;  // strobe/request
+                wbd_ext_adr_i ='h0;  // address
+                wbd_ext_we_i  ='h0;  // write
+                wbd_ext_dat_i ='h0;  // data output
+                wbd_ext_sel_i ='h0;  // byte enable
+	end
+
+	`ifdef WFDUMP
+	   initial begin
+	   	$dumpfile("risc_boot.vcd");
+	   	$dumpvars(4, user_uart_tb);
+	   end
+       `endif
+
+	initial begin
+		wb_rst_i <= 1'b1;
+		#100;
+		wb_rst_i <= 1'b0;	    	// Release reset
+	end
 initial
 begin
    uart_data_bit           = 2'b11;
@@ -128,7 +154,7 @@
 
    #200; // Wait for reset removal
    repeat (10) @(posedge clock);
-   $display("Monitor: Standalone User Risc Boot Test Started");
+   $display("Monitor: Standalone User Uart Test Started");
    
    #1;
    //------------ SDRAM Config - 2
@@ -144,48 +170,47 @@
    // Remove all the reset
    wb_user_core_write('h3000_0000,'h7);
 
-   repeat (2000) @(posedge app_clk);  // wait for Processor Get Ready
+   repeat (20000) @(posedge clock);  // wait for Processor Get Ready
    tb_uart.uart_init;
    wb_user_core_write(`ADDR_SPACE_UART+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1});  
    
+   tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
+	                          uart_stick_parity, uart_timeout, uart_divisor);
    
    for (i=0; i<40; i=i+1)
    	uart_write_data[i] = $random;
    
    
-     tb_top.tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
-	                          uart_stick_parity, uart_timeout, uart_divisor, uart_fifo_enable);
    
-      fork
+   fork
       begin
          for (i=0; i<40; i=i+1)
          begin
-           $display ("\n... UART Agent Writing char %x ...", write_data[i]);
-            tb_top.tb_uart.write_char (uart_write_data[i]);
+           $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]);
+            user_uart_tb.tb_uart.write_char (uart_write_data[i]);
          end
       end
    
       begin
          for (j=0; j<40; j=j+1)
          begin
-           tb_top.tb_uart.read_char_chk(uart_write_data[j]);
+           user_uart_tb.tb_uart.read_char_chk(uart_write_data[j]);
          end
       end
       join
    
       #100
-      tb_top.tb_uart.report_status(rx_nu, tx_nu);
+      tb_uart.report_status(uart_rx_nu, uart_tx_nu);
    
       test_fail = 0;
-      wb_user_core_read(32'h30000018,read_data);
 
       // Check 
       // if all the 40 byte transmitted
       // if all the 40 byte received
       // if no error 
-      if(tx_nu != 40) test_fail = 1;
-      if(rx_nu != 40) test_fail = 1;
-      if(tb_top.tb_uart.err_cnt != 0) test_fail = 1;
+      if(uart_tx_nu != 40) test_fail = 1;
+      if(uart_rx_nu != 40) test_fail = 1;
+      if(tb_uart.err_cnt != 0) test_fail = 1;
 
       $display("###################################################");
       if(test_fail == 0) begin
@@ -219,8 +244,8 @@
     .vssd2(),	// User area 2 digital ground
 `endif
     .wb_clk_i        (clock),  // System clock
-    .rtc_clk         (1'b1),  // Real-time clock
-    .wb_rst_i        (RSTB),  // Regular Reset signal
+    .user_clock2     (1'b1),  // Real-time clock
+    .wb_rst_i        (wb_rst_i),  // Regular Reset signal
 
     .wbd_ext_cyc_i   (wbd_ext_cyc_i),  // strobe/request
     .wbd_ext_stb_i   (wbd_ext_stb_i),  // strobe/request
diff --git a/verilog/rtl/digital_core/src/digital_core.sv b/verilog/rtl/digital_core/src/digital_core.sv
index 405df05..5d37e27 100644
--- a/verilog/rtl/digital_core/src/digital_core.sv
+++ b/verilog/rtl/digital_core/src/digital_core.sv
@@ -200,7 +200,7 @@
 logic   [7:0]                   wbd_uart_dat_o; // data output
 logic                           wbd_uart_sel_o; // byte enable
 logic                           wbd_uart_cyc_o ;
-logic   7:0]                    wbd_uart_dat_i; // data input
+logic   [7:0]                   wbd_uart_dat_i; // data input
 logic                           wbd_uart_ack_i; // acknowlegement
 logic                           wbd_uart_err_i;  // error
 
@@ -210,13 +210,13 @@
 logic                              cpu_rst_n     ;
 logic                              spi_rst_n     ;
 logic                              sdram_rst_n   ;
+logic                              cpu_clk       ;
+logic                              rtc_clk       ;
 
 logic [31:0]                       fuse_mhartid  ;
 logic [15:0]                       irq_lines     ;
 logic                              soft_irq      ;
 
-        .si                    ( uart_rx                 ),
-        .so                    ( uart_tx                 )
 //------------------------------------------------
 // Configuration Parameter
 //------------------------------------------------
@@ -578,18 +578,18 @@
          .s2_wbd_sel_o  (wbd_glbl_sel_o ),
          .s2_wbd_we_o   (wbd_glbl_we_o  ),  
          .s2_wbd_cyc_o  (wbd_glbl_cyc_o ),
-         .s2_wbd_stb_o  (wbd_glbl_stb_o )
+         .s2_wbd_stb_o  (wbd_glbl_stb_o ),
 
          // Slave 3 Interface
-         .s2_wbd_err_i  (1'b0           ),
-         .s2_wbd_dat_i  (wbd_uart_dat_i ),
-         .s2_wbd_ack_i  (wbd_uart_ack_i ),
-         .s2_wbd_dat_o  (wbd_uart_dat_o ),
-         .s2_wbd_adr_o  (wbd_uart_adr_o ),
-         .s2_wbd_sel_o  (wbd_uart_sel_o ),
-         .s2_wbd_we_o   (wbd_uart_we_o  ),  
-         .s2_wbd_cyc_o  (wbd_uart_cyc_o ),
-         .s2_wbd_stb_o  (wbd_uart_stb_o )
+         .s3_wbd_err_i  (1'b0           ),
+         .s3_wbd_dat_i  (wbd_uart_dat_i ),
+         .s3_wbd_ack_i  (wbd_uart_ack_i ),
+         .s3_wbd_dat_o  (wbd_uart_dat_o ),
+         .s3_wbd_adr_o  (wbd_uart_adr_o ),
+         .s3_wbd_sel_o  (wbd_uart_sel_o ),
+         .s3_wbd_we_o   (wbd_uart_we_o  ),  
+         .s3_wbd_cyc_o  (wbd_uart_cyc_o ),
+         .s3_wbd_stb_o  (wbd_uart_stb_o )
 	);
 
 glbl_cfg   u_glbl_cfg (
@@ -649,8 +649,8 @@
         );
 
 uart_core   u_uart_core (
-        arst_n                 (wb_rst_n                  ), // async reset
-        app_clk                (wb_clk_i                  ),
+        .arst_n                 (wb_rst_n                  ), // async reset
+        .app_clk                (wb_clk_i                  ),
 
         // Reg Bus Interface Signal
        .reg_cs                 (wbd_uart_stb_o            ),
diff --git a/verilog/rtl/lib/reset_sync.sv b/verilog/rtl/lib/reset_sync.sv
index ea99a4a..f2c552f 100644
--- a/verilog/rtl/lib/reset_sync.sv
+++ b/verilog/rtl/lib/reset_sync.sv
@@ -57,7 +57,7 @@
 input    scan_mode  ; // test mode
 input    dclk       ; // Destination clock
 input    arst_n     ; // Async Reset
-input    srst_n     ; // Sync Reset w.r.t dclk
+output   srst_n     ; // Sync Reset w.r.t dclk
 
 
 reg      in_data_s  ; // One   Cycle sync 
diff --git a/verilog/rtl/uart/src/uart_cfg.sv b/verilog/rtl/uart/src/uart_cfg.sv
index a979c77..1cd7ee1 100644
--- a/verilog/rtl/uart/src/uart_cfg.sv
+++ b/verilog/rtl/uart/src/uart_cfg.sv
@@ -105,7 +105,7 @@
 // Uart Rx fifo interface
 //--------------------------------
 input            rx_fifo_empty;
-wire [4:0]       rx_fifo_dval          ; // Total Rx fifo Data Available
+input [4:0]      rx_fifo_dval          ; // Total Rx fifo Data Available
 output           rx_fifo_rd_en;
 input [7:0]      rx_fifo_data;
 
diff --git a/verilog/rtl/uart/src/uart_core.sv b/verilog/rtl/uart/src/uart_core.sv
index d318e3f..258c134 100644
--- a/verilog/rtl/uart/src/uart_core.sv
+++ b/verilog/rtl/uart/src/uart_core.sv
@@ -127,10 +127,16 @@
 
 wire   [11:0]   cfg_baud_16x         ; // 16x Baud clock generation
 wire            rx_fifo_wr_full      ;
+wire            tx_fifo_rd_empty     ;
+wire            tx_fifo_rd           ;
 wire           app_rxfifo_empty      ;
-
+wire           app_rxfifo_rd_en      ;
+wire           app_tx_fifo_full      ;
+wire           rx_fifo_wr            ;
+wire           tx_fifo_wr_en         ;
 wire [AW:0]    tx_fifo_fspace        ; // Total Tx fifo Free Space
 wire [AW:0]    rx_fifo_dval          ; // Total Rx fifo Data Available
+wire           si_ss                 ;
 
 uart_cfg u_cfg (
 
@@ -163,7 +169,7 @@
             . tx_fifo_data        (app_txfifo_data),
 
             . rx_fifo_empty       (app_rxfifo_empty),
-             .rd_fifo_dval        (rx_fifo_dval   ),
+             .rx_fifo_dval        (rx_fifo_dval   ),
             . rx_fifo_rd_en       (app_rxfifo_rd_en),
             . rx_fifo_data        (app_rxfifo_data) ,
 
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 33f2c1f..ba06633 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -37,6 +37,7 @@
     `include "uart/src/uart_txfsm.sv"
     `include "lib/async_fifo_th.sv"  
     `include "lib/reset_sync.sv"  
+    `include "lib/double_sync_low.v"  
 
      `include "sdram_ctrl/src/top/sdrc_top.v" 
      `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v" 
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index 61f7f64..410dc9b 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -121,7 +121,7 @@
          output	logic [3:0]	s2_wbd_sel_o,
          output	logic 	        s2_wbd_we_o,
          output	logic 	        s2_wbd_cyc_o,
-         output	logic 	        s2_wbd_stb_o
+         output	logic 	        s2_wbd_stb_o,
 
          // Slave 3 Interface
 	 // Uart is 8bit interface