)]}'
{
  "commit": "54e49ce02474a5a5fa999aeae538f91a967a8a1c",
  "tree": "4094c4c80685ea2ae4b84c4c0dfa131edb80df7b",
  "parents": [
    "6330d336c861be868540c509ec797fb4e5ad8b24"
  ],
  "author": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Thu Jun 17 08:40:42 2021 +0530"
  },
  "committer": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Thu Jun 17 08:40:42 2021 +0530"
  },
  "message": "spi rtl issue fix in clkgen\n",
  "tree_diff": [
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      "old_path": "verilog/rtl/spi_master/src/spim_clkgen.sv",
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      "new_mode": 33188,
      "new_path": "verilog/rtl/spi_master/src/spim_clkgen.sv"
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      "new_path": "verilog/rtl/spi_master/synth/Makefile"
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}