)]}'
{
  "commit": "3db503544fb07642eca32e063509144f25b6bdbd",
  "tree": "305292b1576e4a7e08ceaa602d76b57e39163104",
  "parents": [
    "25e2d746de87b228a1851832682cfcbf9239e33d"
  ],
  "author": {
    "name": "dinesha",
    "email": "dineshannayya@users.noreply.github.com",
    "time": "Tue Jun 08 11:20:32 2021 +0000"
  },
  "committer": {
    "name": "dinesha",
    "email": "dineshannayya@users.noreply.github.com",
    "time": "Tue Jun 08 11:20:32 2021 +0000"
  },
  "message": "sdram control added",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "0d6dc291b83e6b91136ff2ba436207e2cfb8024b",
      "new_mode": 33261,
      "new_path": "verilog/rtl/lib/async_fifo.sv"
    },
    {
      "type": "modify",
      "old_id": "fb934a29a3737cefd0c5d057b215ca1a174448bb",
      "old_mode": 33188,
      "old_path": "verilog/rtl/lib/sync_fifo.sv",
      "new_id": "2b96bfc760dffda28c8def336ba3f890a31f456d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/lib/sync_fifo.sv"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "2206db67369c10cfdf8c2f495a7d12523d13a7c4",
      "new_mode": 33261,
      "new_path": "verilog/rtl/sdram_ctrl/src/core/sdrc_bank_ctl.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "5eeb1e99dd12480d6be8b63100b51000cec6eda3",
      "new_mode": 33261,
      "new_path": "verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "025e74cee829be09a3bc76a95f105c107cee8068",
      "new_mode": 33261,
      "new_path": "verilog/rtl/sdram_ctrl/src/core/sdrc_bs_convert.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "b9eacde1b6c34fe8f80118190f4c2ece0dc205e3",
      "new_mode": 33261,
      "new_path": "verilog/rtl/sdram_ctrl/src/core/sdrc_core.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "af7b506035344914a2cacef7d4fe64e81332c489",
      "new_mode": 33261,
      "new_path": "verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "cd87d2601e8facc4810e0010bf025768582610a9",
      "new_mode": 33261,
      "new_path": "verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "10c10dab3b8e35c8431b8304280ab01679aa1e0e",
      "new_mode": 33261,
      "new_path": "verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "645eb9b6bb3d57d124ae364fd4c2d9ce8328274c",
      "new_mode": 33261,
      "new_path": "verilog/rtl/sdram_ctrl/src/filelist_rtl.f"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "353a20b0b2ac2500383aa83b440dadf8cdb07142",
      "new_mode": 33261,
      "new_path": "verilog/rtl/sdram_ctrl/src/run_modelsim"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "077f6886e7aee9a0c0f5bca6e96fe52238cc0c20",
      "new_mode": 33261,
      "new_path": "verilog/rtl/sdram_ctrl/src/top/sdrc_top.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "c5857659c2d7317b8b86a73bd4a3a706519378a3",
      "new_mode": 33261,
      "new_path": "verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v"
    },
    {
      "type": "modify",
      "old_id": "9aa0b4ddf007f4c18e3cc254b5719162f42af00f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv",
      "new_id": "abc712796b8ca08b3c09e16d9b1e0558a8d41853",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv"
    },
    {
      "type": "modify",
      "old_id": "1346b59588365f99aded1b3e555f5e19bfd8c908",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv",
      "new_id": "c2a5349a74e730cb50bcb5650e01598b150156ca",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv"
    },
    {
      "type": "modify",
      "old_id": "87dd341b9af85d3e6c0ea96a86603135beb1b970",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/src/wb_top.files",
      "new_id": "1a3ba74f01f1c19ae72eb105acdbf84e4eacfc01",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/src/wb_top.files"
    }
  ]
}