Step 1:  Create new cells for new GPIO default vectors.
Creating new layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag
Creating new gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Step 2:  Modify top-level layouts to use the specified defaults.
Done.