)]}'
{
  "id": "5dd9f75502a612bd3aa73390075304fc698c3f09",
  "entries": [
    {
      "mode": 33188,
      "type": "blob",
      "id": "984760704a1530993cd968ac6d652807861bfadd",
      "name": "eFPGA_top.gds"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "b32ae18957258f16b4e7113c148acacb6ef2a4ce",
      "name": "user_proj_example.gds"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "4fb27179c3315e440162cfcef0766824c768d879",
      "name": "user_project_wrapper.gds"
    }
  ]
}