diff --git a/gds/caravel.gds.gz b/gds/caravel.gds.gz
new file mode 100644
index 0000000..e83ca01
--- /dev/null
+++ b/gds/caravel.gds.gz
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diff --git a/gds/caravel_00020005.gds.gz.00.split b/gds/caravel_00020005.gds.gz.00.split
new file mode 100644
index 0000000..3da24df
--- /dev/null
+++ b/gds/caravel_00020005.gds.gz.00.split
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diff --git a/gds/caravel_00020005.gds.gz.01.split b/gds/caravel_00020005.gds.gz.01.split
new file mode 100644
index 0000000..fa3d1ec
--- /dev/null
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diff --git a/gds/caravel_00020005.gds.gz.02.split b/gds/caravel_00020005.gds.gz.02.split
new file mode 100644
index 0000000..da8ac0d
--- /dev/null
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diff --git a/gds/caravel_00020005.gds.gz.03.split b/gds/caravel_00020005.gds.gz.03.split
new file mode 100644
index 0000000..d93bf23
--- /dev/null
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diff --git a/gds/caravel_00020005.gds.gz.04.split b/gds/caravel_00020005.gds.gz.04.split
new file mode 100644
index 0000000..205ef46
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diff --git a/gds/caravel_00020005_fill_pattern.gds.gz.00.split b/gds/caravel_00020005_fill_pattern.gds.gz.00.split
new file mode 100644
index 0000000..b02b922
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diff --git a/gds/caravel_00020005_fill_pattern.gds.gz.01.split b/gds/caravel_00020005_fill_pattern.gds.gz.01.split
new file mode 100644
index 0000000..7497168
--- /dev/null
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diff --git a/gds/caravel_00020005_fill_pattern.gds.gz.02.split b/gds/caravel_00020005_fill_pattern.gds.gz.02.split
new file mode 100644
index 0000000..5ccab04
--- /dev/null
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diff --git a/gds/caravel_00020005_fill_pattern.gds.gz.03.split b/gds/caravel_00020005_fill_pattern.gds.gz.03.split
new file mode 100644
index 0000000..0eb74e4
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diff --git a/gds/eFPGA_top.gds b/gds/eFPGA_top.gds
deleted file mode 100644
index 9847607..0000000
--- a/gds/eFPGA_top.gds
+++ /dev/null
Binary files differ
diff --git a/gds/eFPGA_top.gds.gz b/gds/eFPGA_top.gds.gz
new file mode 100644
index 0000000..b593c31
--- /dev/null
+++ b/gds/eFPGA_top.gds.gz
Binary files differ
diff --git a/gds/user_id_prog_zero.gds.gz b/gds/user_id_prog_zero.gds.gz
new file mode 100644
index 0000000..0cf4f9e
--- /dev/null
+++ b/gds/user_id_prog_zero.gds.gz
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diff --git a/gds/user_id_programming.gds.gz b/gds/user_id_programming.gds.gz
new file mode 100644
index 0000000..bb90221
--- /dev/null
+++ b/gds/user_id_programming.gds.gz
Binary files differ
diff --git a/gds/user_proj_example.gds b/gds/user_proj_example.gds
deleted file mode 100644
index b32ae18..0000000
--- a/gds/user_proj_example.gds
+++ /dev/null
Binary files differ
diff --git a/gds/user_proj_example.gds.gz b/gds/user_proj_example.gds.gz
new file mode 100644
index 0000000..267a7b6
--- /dev/null
+++ b/gds/user_proj_example.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
deleted file mode 100644
index 4fb2717..0000000
--- a/gds/user_project_wrapper.gds
+++ /dev/null
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
new file mode 100644
index 0000000..79422b2
--- /dev/null
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/info.yaml b/info.yaml
index aa434d0..dee9c3b 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,19 +1,19 @@
----
 project:
-  description: "FABulous SKY - a heterogeneous FPGA fabric in Skywater130"
-  foundry: "SkyWater"
-  git_url: "https://github.com/nguyendao-uom/eFPGA_v3_caravel"
-  organization: ""
-  organization_url: ""
-  owner: "Nguyen Dao"
-  process: "SKY130"
-  project_name: "FABulous_Sky"
-  project_id: "00000000"
+  category: Test Harness
+  cover_image: docs/source/eFPGA_ver3.png
+  description: FABulous SKY - a heterogeneous FPGA fabric in Skywater130
+  foundry: SkyWater
+  git_url: https://github.com/nguyendao-uom/eFPGA_v3_caravel
+  organization: ''
+  organization_url: ''
+  owner: Nguyen Dao
+  process: SKY130
+  project_id: '00020005'
+  project_name: FABulous_Sky
+  shuttle_url: https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-two/slot-005.git
   tags:
-    - "Open MPW"
-    - "Test Harness"
-  category: "Test Harness"
-  top_level_netlist: "caravel/verilog/gl/caravel.v"
-  user_level_netlist: "verilog/gl/user_project_wrapper.v"
-  version: "1.00"
-  cover_image: "docs/source/eFPGA_ver3.png"
+  - Open MPW
+  - Test Harness
+  top_level_netlist: caravel/verilog/gl/caravel.v
+  user_level_netlist: verilog/gl/user_project_wrapper.v
+  version: '1.00'
diff --git a/mag/.magicrc b/mag/.magicrc
new file mode 100755
index 0000000..12328c6
--- /dev/null
+++ b/mag/.magicrc
@@ -0,0 +1,97 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch.  This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+    scalegrid 1 2
+}
+
+drc off
+drc euclidean on
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+    set PDKPATH "$::env(PDK_ROOT)/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid 
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+   set MAGTYPE maglef
+}
+
+	path search [concat "../$MAGTYPE" [path search]]
+
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+    addpath ${PDKPATH}/libs.ref/mag/sky130_ml_xx_hd
+} else {
+    addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/mag
+}
+
+addpath hexdigits
+addpath ../subcells/simple_por/mag
+
+# add path to GDS cells
+
+# add path to IP from catalog.  This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space.  Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/mag/caravan.mag b/mag/caravan.mag
new file mode 100644
index 0000000..34c7af2
--- /dev/null
+++ b/mag/caravan.mag
@@ -0,0 +1,55762 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1638836243
+<< checkpaint >>
+rect -1260 -1260 718860 1038860
+<< isosubstrate >>
+rect 707553 886338 709093 889314
+rect 8741 806938 10281 809914
+rect 8741 763738 10281 766714
+rect 8741 720538 10281 723514
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+rect 707553 122538 709093 125514
+rect 142084 47031 145468 49885
+rect 650094 46832 661434 55344
+<< metal1 >>
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+rect 483624 1004640 483630 1004652
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+rect 460640 6598 473160 19088
+rect 515440 6598 527960 19088
+rect 570422 6811 582590 18975
+rect 624222 6811 636390 18975
+use xres_buf  rstb_level
+timestamp 1638030917
+transform -1 0 145710 0 -1 50488
+box 414 -400 3522 3800
+use open_source  open_source_0 hexdigits
+timestamp 1638586442
+transform 1 0 206074 0 1 2336
+box 752 5164 29030 16242
+use caravan_motto  caravan_motto_0
+timestamp 1637698689
+transform 1 0 -54560 0 1 -52
+box 367960 10204 399802 14768
+use caravan_logo  caravan_logo_0
+timestamp 1636751500
+transform 1 0 255300 0 1 6032
+box 2240 2560 37000 11520
+use copyright_block_a  copyright_block_a_0
+timestamp 1636248774
+transform 1 0 149582 0 1 16298
+box -262 -9464 35048 2764
+use user_id_textblock  user_id_textblock_0
+timestamp 1608324878
+transform 1 0 96272 0 1 6890
+box -656 1508 33720 10344
+use caravel_clocking  clocking
+timestamp 1638662845
+transform 1 0 621684 0 1 63608
+box -38 -48 20000 12000
+use housekeeping  housekeeping
+timestamp 1638464048
+transform 1 0 606434 0 1 100002
+box 0 0 60046 110190
+use digital_pll  pll
+timestamp 1638470892
+transform 1 0 628146 0 1 80944
+box 0 0 15000 15000
+use user_id_programming  user_id_value
+timestamp 1638030917
+transform 1 0 656624 0 1 88126
+box 0 0 7109 7077
+use gpio_defaults_block_1803 gpio_defaults_block_0
+timestamp 1636219436
+transform -1 0 709467 0 1 134000
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_bidir_1\[0\]
+timestamp 1638030917
+transform -1 0 710203 0 1 121000
+box 882 167 34000 13000
+use simple_por  por ../maglef
+timestamp 1638030790
+transform 1 0 650146 0 -1 55282
+box -14 11 11344 8684
+use mgmt_core_wrapper  soc
+timestamp 1638280046
+transform 1 0 52034 0 1 53002
+box 382 -400 524400 164400
+use gpio_control_block  gpio_control_bidir_2\[2\]
+timestamp 1638030917
+transform 1 0 7631 0 1 202600
+box 882 167 34000 13000
+use gpio_defaults_block_1803 gpio_defaults_block_1
+timestamp 1636219436
+transform -1 0 709467 0 1 179200
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_bidir_1\[1\]
+timestamp 1638030917
+transform -1 0 710203 0 1 166200
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_bidir_2\[1\]
+timestamp 1638030917
+transform 1 0 7631 0 1 245800
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_37
+timestamp 1638587925
+transform 1 0 8367 0 1 215600
+box -38 0 6018 2224
+use mgmt_protect  mgmt_buffers
+timestamp 1638030917
+transform 1 0 192180 0 1 232036
+box -400 -400 220400 32400
+use spare_logic_block  spare_logic_block_3
+timestamp 1638030917
+transform 1 0 88632 0 1 232528
+box 0 0 9000 9000
+use spare_logic_block  spare_logic_block_1
+timestamp 1638030917
+transform 1 0 168632 0 1 232528
+box 0 0 9000 9000
+use spare_logic_block  spare_logic_block_2
+timestamp 1638030917
+transform 1 0 428632 0 1 232528
+box 0 0 9000 9000
+use spare_logic_block  spare_logic_block_0
+timestamp 1638030917
+transform 1 0 640874 0 1 220592
+box 0 0 9000 9000
+use gpio_control_block  gpio_control_in_1a\[0\]
+timestamp 1638030917
+transform -1 0 710203 0 1 211200
+box 882 167 34000 13000
+use gpio_defaults_block_0403 gpio_defaults_block_2
+timestamp 1638299091
+transform -1 0 709467 0 1 224200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_36
+timestamp 1638587925
+transform 1 0 8367 0 1 258800
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1a\[1\]
+timestamp 1638030917
+transform -1 0 710203 0 1 256400
+box 882 167 34000 13000
+use gpio_defaults_block_0403 gpio_defaults_block_3
+timestamp 1638299091
+transform -1 0 709467 0 1 269400
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_bidir_2\[0\]
+timestamp 1638030917
+transform 1 0 7631 0 1 289000
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_35
+timestamp 1638587925
+transform 1 0 8367 0 1 302000
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1a\[2\]
+timestamp 1638030917
+transform -1 0 710203 0 1 301400
+box 882 167 34000 13000
+use gpio_defaults_block_0403 gpio_defaults_block_4
+timestamp 1638299091
+transform -1 0 709467 0 1 314400
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_2\[7\]
+timestamp 1638030917
+transform 1 0 7631 0 1 418600
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_2\[8\]
+timestamp 1638030917
+transform 1 0 7631 0 1 375400
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_2\[9\]
+timestamp 1638030917
+transform 1 0 7631 0 1 332200
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_32
+timestamp 1638587925
+transform 1 0 8367 0 1 431600
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_33
+timestamp 1638587925
+transform 1 0 8367 0 1 388400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_34
+timestamp 1638587925
+transform 1 0 8367 0 1 345200
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1a\[3\]
+timestamp 1638030917
+transform -1 0 710203 0 1 346400
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_1a\[4\]
+timestamp 1638030917
+transform -1 0 710203 0 1 391600
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_1a\[5\]
+timestamp 1638030917
+transform -1 0 710203 0 1 479800
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_5
+timestamp 1638587925
+transform -1 0 709467 0 1 359400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_6
+timestamp 1638587925
+transform -1 0 709467 0 1 404600
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_7
+timestamp 1638587925
+transform -1 0 709467 0 1 492800
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_2\[4\]
+timestamp 1638030917
+transform 1 0 7631 0 1 632600
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_2\[5\]
+timestamp 1638030917
+transform 1 0 7631 0 1 589400
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_2\[6\]
+timestamp 1638030917
+transform 1 0 7631 0 1 546200
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_30
+timestamp 1638587925
+transform 1 0 8367 0 1 602400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_31
+timestamp 1638587925
+transform 1 0 8367 0 1 559200
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1\[0\]
+timestamp 1638030917
+transform -1 0 710203 0 1 523800
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_1\[1\]
+timestamp 1638030917
+transform -1 0 710203 0 1 568800
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_1\[2\]
+timestamp 1638030917
+transform -1 0 710203 0 1 614000
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_10
+timestamp 1638587925
+transform -1 0 709467 0 1 627000
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_8
+timestamp 1638587925
+transform -1 0 709467 0 1 536800
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_9
+timestamp 1638587925
+transform -1 0 709467 0 1 581800
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_2\[2\]
+timestamp 1638030917
+transform 1 0 7631 0 1 719000
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_2\[3\]
+timestamp 1638030917
+transform 1 0 7631 0 1 675800
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_27
+timestamp 1638587925
+transform 1 0 8367 0 1 732000
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_28
+timestamp 1638587925
+transform 1 0 8367 0 1 688800
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_29
+timestamp 1638587925
+transform 1 0 8367 0 1 645600
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1\[3\]
+timestamp 1638030917
+transform -1 0 710203 0 1 659000
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_1\[4\]
+timestamp 1638030917
+transform -1 0 710203 0 1 704200
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_11
+timestamp 1638587925
+transform -1 0 709467 0 1 672000
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_12
+timestamp 1638587925
+transform -1 0 709467 0 1 717200
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_2\[0\]
+timestamp 1638030917
+transform 1 0 7631 0 1 805400
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_2\[1\]
+timestamp 1638030917
+transform 1 0 7631 0 1 762200
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_14
+timestamp 1638587925
+transform 1 0 8367 0 1 818400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_26
+timestamp 1638587925
+transform 1 0 8367 0 1 775200
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1\[5\]
+timestamp 1638030917
+transform -1 0 710203 0 1 884800
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_13
+timestamp 1638587925
+transform -1 0 709467 0 1 897800
+box -38 0 6018 2224
+use chip_io_alt  padframe
+timestamp 1638031010
+transform 1 0 0 0 1 0
+box 0 0 717600 1037600
+use caravan_power_routing  caravan_power_routing_0
+timestamp 1638483672
+transform 1 0 0 0 1 0
+box 0 0 717600 1037600
+use user_analog_project_wrapper  mprj
+timestamp 1632839657
+transform 1 0 65308 0 1 278718
+box -800 -800 584800 704800
+<< labels >>
+flabel metal5 s 187640 6598 200160 19088 0 FreeSans 24000 0 0 0 clock
+port 0 nsew signal input
+flabel metal5 s 351040 6598 363560 19088 0 FreeSans 24000 0 0 0 flash_clk
+port 1 nsew signal tristate
+flabel metal5 s 296240 6598 308760 19088 0 FreeSans 24000 0 0 0 flash_csb
+port 2 nsew signal tristate
+flabel metal5 s 405840 6598 418360 19088 0 FreeSans 24000 0 0 0 flash_io0
+port 3 nsew signal tristate
+flabel metal5 s 460640 6598 473160 19088 0 FreeSans 24000 0 0 0 flash_io1
+port 4 nsew signal tristate
+flabel metal5 s 515440 6598 527960 19088 0 FreeSans 24000 0 0 0 gpio
+port 5 nsew signal bidirectional
+flabel metal5 s 698512 101240 711002 113760 0 FreeSans 24000 0 0 0 mprj_io[0]
+port 6 nsew signal bidirectional
+flabel metal5 s 698512 684440 711002 696960 0 FreeSans 24000 0 0 0 mprj_io[10]
+port 7 nsew signal bidirectional
+flabel metal5 s 698512 729440 711002 741960 0 FreeSans 24000 0 0 0 mprj_io[11]
+port 8 nsew signal bidirectional
+flabel metal5 s 698512 774440 711002 786960 0 FreeSans 24000 0 0 0 mprj_io[12]
+port 9 nsew signal bidirectional
+flabel metal5 s 698512 863640 711002 876160 0 FreeSans 24000 0 0 0 mprj_io[13]
+port 10 nsew signal bidirectional
+flabel metal5 s 628240 1018512 640760 1031002 0 FreeSans 24000 0 0 0 mprj_io[15]
+port 12 nsew signal bidirectional
+flabel metal5 s 526440 1018512 538960 1031002 0 FreeSans 24000 0 0 0 mprj_io[16]
+port 13 nsew signal bidirectional
+flabel metal5 s 475040 1018512 487560 1031002 0 FreeSans 24000 0 0 0 mprj_io[17]
+port 14 nsew signal bidirectional
+flabel metal5 s 386040 1018512 398560 1031002 0 FreeSans 24000 0 0 0 mprj_io[18]
+port 15 nsew signal bidirectional
+flabel metal5 s 284240 1018512 296760 1031002 0 FreeSans 24000 0 0 0 mprj_io[19]
+port 16 nsew signal bidirectional
+flabel metal5 s 698512 146440 711002 158960 0 FreeSans 24000 0 0 0 mprj_io[1]
+port 17 nsew signal bidirectional
+flabel metal5 s 232640 1018512 245160 1031002 0 FreeSans 24000 0 0 0 mprj_io[20]
+port 18 nsew signal bidirectional
+flabel metal5 s 181240 1018512 193760 1031002 0 FreeSans 24000 0 0 0 mprj_io[21]
+port 19 nsew signal bidirectional
+flabel metal5 s 129840 1018512 142360 1031002 0 FreeSans 24000 0 0 0 mprj_io[22]
+port 20 nsew signal bidirectional
+flabel metal5 s 78440 1018512 90960 1031002 0 FreeSans 24000 0 0 0 mprj_io[23]
+port 21 nsew signal bidirectional
+flabel metal5 s 6598 956440 19088 968960 0 FreeSans 24000 0 0 0 mprj_io[24]
+port 22 nsew signal bidirectional
+flabel metal5 s 6598 786640 19088 799160 0 FreeSans 24000 0 0 0 mprj_io[25]
+port 23 nsew signal bidirectional
+flabel metal5 s 6598 743440 19088 755960 0 FreeSans 24000 0 0 0 mprj_io[26]
+port 24 nsew signal bidirectional
+flabel metal5 s 6598 700240 19088 712760 0 FreeSans 24000 0 0 0 mprj_io[27]
+port 25 nsew signal bidirectional
+flabel metal5 s 6598 657040 19088 669560 0 FreeSans 24000 0 0 0 mprj_io[28]
+port 26 nsew signal bidirectional
+flabel metal5 s 6598 613840 19088 626360 0 FreeSans 24000 0 0 0 mprj_io[29]
+port 27 nsew signal bidirectional
+flabel metal5 s 698512 191440 711002 203960 0 FreeSans 24000 0 0 0 mprj_io[2]
+port 28 nsew signal bidirectional
+flabel metal5 s 6598 570640 19088 583160 0 FreeSans 24000 0 0 0 mprj_io[30]
+port 29 nsew signal bidirectional
+flabel metal5 s 6598 527440 19088 539960 0 FreeSans 24000 0 0 0 mprj_io[31]
+port 30 nsew signal bidirectional
+flabel metal5 s 6598 399840 19088 412360 0 FreeSans 24000 0 0 0 mprj_io[32]
+port 31 nsew signal bidirectional
+flabel metal5 s 6598 356640 19088 369160 0 FreeSans 24000 0 0 0 mprj_io[33]
+port 32 nsew signal bidirectional
+flabel metal5 s 6598 313440 19088 325960 0 FreeSans 24000 0 0 0 mprj_io[34]
+port 33 nsew signal bidirectional
+flabel metal5 s 6598 270240 19088 282760 0 FreeSans 24000 0 0 0 mprj_io[35]
+port 34 nsew signal bidirectional
+flabel metal5 s 6598 227040 19088 239560 0 FreeSans 24000 0 0 0 mprj_io[36]
+port 35 nsew signal bidirectional
+flabel metal5 s 6598 183840 19088 196360 0 FreeSans 24000 0 0 0 mprj_io[37]
+port 36 nsew signal bidirectional
+flabel metal5 s 698512 236640 711002 249160 0 FreeSans 24000 0 0 0 mprj_io[3]
+port 37 nsew signal bidirectional
+flabel metal5 s 698512 281640 711002 294160 0 FreeSans 24000 0 0 0 mprj_io[4]
+port 38 nsew signal bidirectional
+flabel metal5 s 698512 326640 711002 339160 0 FreeSans 24000 0 0 0 mprj_io[5]
+port 39 nsew signal bidirectional
+flabel metal5 s 698512 371840 711002 384360 0 FreeSans 24000 0 0 0 mprj_io[6]
+port 40 nsew signal bidirectional
+flabel metal5 s 698512 549040 711002 561560 0 FreeSans 24000 0 0 0 mprj_io[7]
+port 41 nsew signal bidirectional
+flabel metal5 s 698512 594240 711002 606760 0 FreeSans 24000 0 0 0 mprj_io[8]
+port 42 nsew signal bidirectional
+flabel metal5 s 698512 639240 711002 651760 0 FreeSans 24000 0 0 0 mprj_io[9]
+port 43 nsew signal bidirectional
+flabel metal5 s 136713 7143 144150 18309 0 FreeSans 24000 0 0 0 resetb
+port 44 nsew signal input
+flabel metal5 s 6167 70054 19619 80934 0 FreeSans 24000 0 0 0 vccd
+port 45 nsew signal bidirectional
+flabel metal5 s 697980 909666 711432 920546 0 FreeSans 24000 0 0 0 vccd1
+port 46 nsew signal bidirectional
+flabel metal5 s 6167 914054 19619 924934 0 FreeSans 24000 0 0 0 vccd2
+port 47 nsew signal bidirectional
+flabel metal5 s 624222 6811 636390 18975 0 FreeSans 24000 0 0 0 vdda
+port 48 nsew signal bidirectional
+flabel metal5 s 698624 819822 710788 831990 0 FreeSans 24000 0 0 0 vdda1
+port 49 nsew signal bidirectional
+flabel metal5 s 698624 505222 710788 517390 0 FreeSans 24000 0 0 0 vdda1_2
+port 50 nsew signal bidirectional
+flabel metal5 s 6811 484410 18975 496578 0 FreeSans 24000 0 0 0 vdda2
+port 51 nsew signal bidirectional
+flabel metal5 s 6811 111610 18975 123778 0 FreeSans 24000 0 0 0 vddio
+port 52 nsew signal bidirectional
+flabel metal5 s 6811 871210 18975 883378 0 FreeSans 24000 0 0 0 vddio_2
+port 53 nsew signal bidirectional
+flabel metal5 s 80222 6811 92390 18975 0 FreeSans 24000 0 0 0 vssa
+port 54 nsew signal bidirectional
+flabel metal5 s 577010 1018624 589178 1030788 0 FreeSans 24000 0 0 0 vssa1
+port 55 nsew signal bidirectional
+flabel metal5 s 698624 417022 710788 429190 0 FreeSans 24000 0 0 0 vssa1_2
+port 56 nsew signal bidirectional
+flabel metal5 s 6811 829010 18975 841178 0 FreeSans 24000 0 0 0 vssa2
+port 57 nsew signal bidirectional
+flabel metal5 s 243266 6167 254146 19619 0 FreeSans 24000 0 0 0 vssd
+port 58 nsew signal bidirectional
+flabel metal5 s 697980 461866 711432 472746 0 FreeSans 24000 0 0 0 vssd1
+port 59 nsew signal bidirectional
+flabel metal5 s 6167 442854 19619 453734 0 FreeSans 24000 0 0 0 vssd2
+port 60 nsew signal bidirectional
+flabel metal5 s 570422 6811 582590 18975 0 FreeSans 24000 0 0 0 vssio
+port 61 nsew signal bidirectional
+flabel metal5 s 334810 1018624 346978 1030788 0 FreeSans 24000 0 0 0 vssio_2
+port 62 nsew signal bidirectional
+flabel metal5 621960 246802 629984 249230 0 FreeSans 16000 0 0 0 vccd1_core
+flabel metal5 621948 250708 629990 253036 0 FreeSans 16000 0 0 0 vssd1_core
+flabel metal5 621550 262640 629508 265144 0 FreeSans 16000 0 0 0 vdda1_core
+flabel metal5 621514 266692 629472 269196 0 FreeSans 16000 0 0 0 vssa1_core
+flabel metal5 590480 230750 595228 233134 0 FreeSans 16000 0 0 0 vccd_core
+flabel metal5 590522 234770 595540 236910 0 FreeSans 16000 0 0 0 vssd_core
+flabel metal5 621512 258708 630212 261250 0 FreeSans 16000 0 0 0 vssa2_core
+flabel metal5 621598 254668 630298 257210 0 FreeSans 16000 0 0 0 vdda2_core
+flabel metal5 621936 242776 630636 245318 0 FreeSans 16000 0 0 0 vssd2_core
+flabel metal5 621794 238736 630494 241278 0 FreeSans 16000 0 0 0 vccd2_core
+flabel metal5 s 698512 952840 711002 965360 0 FreeSans 24000 0 0 0 mprj_io[14]
+port 11 nsew signal bidirectional
+<< properties >>
+string FIXED_BBOX 0 0 717600 1037600
+<< end >>
diff --git a/mag/caravel.mag b/mag/caravel.mag
new file mode 100644
index 0000000..c9b0cbf
--- /dev/null
+++ b/mag/caravel.mag
@@ -0,0 +1,65318 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1638835791
+<< checkpaint >>
+rect -1260 -1260 718860 1038860
+<< isosubstrate >>
+rect 98738 1027427 101714 1028967
+rect 150138 1027427 153114 1028967
+rect 201538 1027427 204514 1028967
+rect 252938 1027427 255914 1028967
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+rect 707553 302938 709093 305914
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+rect 707553 167738 709093 170714
+rect 707553 122538 709093 125514
+rect 142074 46934 145452 49898
+rect 650094 46832 661434 55344
+<< metal1 >>
+rect 145190 1007428 145196 1007480
+rect 145248 1007468 145254 1007480
+rect 154574 1007468 154580 1007480
+rect 145248 1007440 154580 1007468
+rect 145248 1007428 145254 1007440
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+rect 466454 1006000 466460 1006012
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+rect 580947 73220 581013 73221
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+rect 520411 42124 520477 42125
+rect 520411 42060 520412 42124
+rect 520476 42060 520477 42124
+rect 520411 42059 520477 42060
+<< metal5 >>
+rect 78440 1018512 90960 1031002
+rect 129840 1018512 142360 1031002
+rect 181240 1018512 193760 1031002
+rect 232640 1018512 245160 1031002
+rect 284240 1018512 296760 1031002
+rect 334810 1018624 346978 1030788
+rect 386040 1018512 398560 1031002
+rect 475040 1018512 487560 1031002
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+rect 628240 1018512 640760 1031002
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+rect 187640 6598 200160 19088
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+rect 296240 6598 308760 19088
+rect 351040 6598 363560 19088
+rect 405840 6598 418360 19088
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+rect 624222 6811 636390 18975
+<< comment >>
+rect 0 1037400 717600 1037600
+rect 0 37510 200 1037400
+rect 717400 200 717600 1037400
+rect 39330 0 717600 200
+use caravel_motto  caravel_motto_0
+timestamp 1637698310
+transform 1 0 -54372 0 1 -4446
+box 373080 14838 395618 19242
+use caravel_logo  caravel_logo_0
+timestamp 1636495793
+transform 1 0 269370 0 1 5100
+box -2520 0 15000 15560
+use open_source  open_source_0 hexdigits
+timestamp 1635801696
+transform 1 0 206098 0 1 2054
+box 752 5164 29030 16242
+use xres_buf  rstb_level
+timestamp 1638492834
+transform -1 0 145710 0 -1 50488
+box 414 -400 3522 3800
+use user_id_textblock  user_id_textblock_0
+timestamp 1608324878
+transform 1 0 96272 0 1 6890
+box -656 1508 33720 10344
+use copyright_block  copyright_block_0
+timestamp 1636248654
+transform 1 0 149582 0 1 16298
+box -262 -9464 35048 2764
+use caravel_clocking  clocking
+timestamp 1638662845
+transform 1 0 626764 0 1 63284
+box -38 -48 20000 12000
+use housekeeping  housekeeping
+timestamp 1638835791
+transform 1 0 606434 0 1 100002
+box 0 0 60046 110190
+use digital_pll  pll
+timestamp 1638492834
+transform 1 0 628146 0 1 80944
+box 0 0 15000 15000
+use user_id_programming  user_id_value
+timestamp 1638492834
+transform 1 0 656624 0 1 88126
+box 0 0 7109 7077
+use gpio_control_block  gpio_control_bidir_1\[0\]
+timestamp 1638492834
+transform -1 0 710203 0 1 121000
+box 882 167 34000 13000
+use gpio_defaults_block_1803 gpio_defaults_block_0
+timestamp 1638492834
+transform -1 0 709467 0 1 134000
+box -38 0 6018 2224
+use simple_por  por ../maglef
+timestamp 1638030790
+transform 1 0 650146 0 -1 55282
+box -14 11 11344 8684
+use mgmt_core_wrapper  soc
+timestamp 1638280046
+transform 1 0 52034 0 1 53002
+box 382 -400 524400 164400
+use gpio_control_block  gpio_control_bidir_2\[2\]
+timestamp 1638492834
+transform 1 0 7631 0 1 202600
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_bidir_1\[1\]
+timestamp 1638492834
+transform -1 0 710203 0 1 166200
+box 882 167 34000 13000
+use gpio_defaults_block_1803 gpio_defaults_block_1
+timestamp 1638492834
+transform -1 0 709467 0 1 179200
+box -38 0 6018 2224
+use mgmt_protect  mgmt_buffers
+timestamp 1638030917
+transform 1 0 192180 0 1 232036
+box -400 -400 220400 32400
+use gpio_control_block  gpio_control_bidir_2\[1\]
+timestamp 1638492834
+transform 1 0 7631 0 1 245800
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_37
+timestamp 1638492834
+transform 1 0 8367 0 1 215600
+box -38 0 6018 2224
+use spare_logic_block  spare_logic_block_3
+timestamp 1638492834
+transform 1 0 88632 0 1 232528
+box 0 0 9000 9000
+use spare_logic_block  spare_logic_block_1
+timestamp 1638492834
+transform 1 0 168632 0 1 232528
+box 0 0 9000 9000
+use spare_logic_block  spare_logic_block_2
+timestamp 1638492834
+transform 1 0 428632 0 1 232528
+box 0 0 9000 9000
+use spare_logic_block  spare_logic_block_0
+timestamp 1638492834
+transform 1 0 640874 0 1 220592
+box 0 0 9000 9000
+use gpio_control_block  gpio_control_in_1a\[0\]
+timestamp 1638492834
+transform -1 0 710203 0 1 211200
+box 882 167 34000 13000
+use gpio_defaults_block_0403 gpio_defaults_block_2
+timestamp 1638492834
+transform -1 0 709467 0 1 224200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_36
+timestamp 1638492834
+transform 1 0 8367 0 1 258800
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1a\[1\]
+timestamp 1638492834
+transform -1 0 710203 0 1 256400
+box 882 167 34000 13000
+use gpio_defaults_block_0403 gpio_defaults_block_3
+timestamp 1638492834
+transform -1 0 709467 0 1 269400
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_bidir_2\[0\]
+timestamp 1638492834
+transform 1 0 7631 0 1 289000
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_35
+timestamp 1638492834
+transform 1 0 8367 0 1 302000
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1a\[2\]
+timestamp 1638492834
+transform -1 0 710203 0 1 301400
+box 882 167 34000 13000
+use gpio_defaults_block_0403 gpio_defaults_block_4
+timestamp 1638492834
+transform -1 0 709467 0 1 314400
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_2\[13\]
+timestamp 1638492834
+transform 1 0 7631 0 1 418600
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_2\[14\]
+timestamp 1638492834
+transform 1 0 7631 0 1 375400
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_2\[15\]
+timestamp 1638492834
+transform 1 0 7631 0 1 332200
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_32
+timestamp 1638492834
+transform 1 0 8367 0 1 431600
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_33
+timestamp 1638492834
+transform 1 0 8367 0 1 388400
+box -38 0 6018 2224
+use gpio_defaults_block  gpio_defaults_defaults_block_34
+timestamp 1638492834
+transform 1 0 8367 0 1 345200
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1a\[3\]
+timestamp 1638492834
+transform -1 0 710203 0 1 346400
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_1a\[4\]
+timestamp 1638492834
+transform -1 0 710203 0 1 391600
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_1a\[5\]
+timestamp 1638492834
+transform -1 0 710203 0 1 479800
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_6
+timestamp 1638492834
+transform -1 0 709467 0 1 404600
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_5
+timestamp 1638492834
+transform -1 0 709467 0 1 359400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_7
+timestamp 1638492834
+transform -1 0 709467 0 1 492800
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_30
+timestamp 1638492834
+transform 1 0 8367 0 1 602400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_31
+timestamp 1638492834
+transform 1 0 8367 0 1 559200
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_2\[12\]
+timestamp 1638492834
+transform 1 0 7631 0 1 546200
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_2\[11\]
+timestamp 1638492834
+transform 1 0 7631 0 1 589400
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_9
+timestamp 1638492834
+transform -1 0 709467 0 1 581800
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_8
+timestamp 1638492834
+transform -1 0 709467 0 1 536800
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1\[1\]
+timestamp 1638492834
+transform -1 0 710203 0 1 568800
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_1\[0\]
+timestamp 1638492834
+transform -1 0 710203 0 1 523800
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_28
+timestamp 1638492834
+transform 1 0 8367 0 1 688800
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_29
+timestamp 1638492834
+transform 1 0 8367 0 1 645600
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_2\[9\]
+timestamp 1638492834
+transform 1 0 7631 0 1 675800
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_2\[10\]
+timestamp 1638492834
+transform 1 0 7631 0 1 632600
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_11
+timestamp 1638492834
+transform -1 0 709467 0 1 672000
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_10
+timestamp 1638492834
+transform -1 0 709467 0 1 627000
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1\[3\]
+timestamp 1638492834
+transform -1 0 710203 0 1 659000
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_1\[2\]
+timestamp 1638492834
+transform -1 0 710203 0 1 614000
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_26
+timestamp 1638492834
+transform 1 0 8367 0 1 775200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_27
+timestamp 1638492834
+transform 1 0 8367 0 1 732000
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_2\[8\]
+timestamp 1638492834
+transform 1 0 7631 0 1 719000
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_2\[7\]
+timestamp 1638492834
+transform 1 0 7631 0 1 762200
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_13
+timestamp 1638492834
+transform -1 0 709467 0 1 762200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_12
+timestamp 1638492834
+transform -1 0 709467 0 1 717200
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1\[5\]
+timestamp 1638492834
+transform -1 0 710203 0 1 749200
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_1\[4\]
+timestamp 1638492834
+transform -1 0 710203 0 1 704200
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_25
+timestamp 1638492834
+transform 1 0 8367 0 1 818400
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_2\[6\]
+timestamp 1638492834
+transform 1 0 7631 0 1 805400
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_24
+timestamp 1638492834
+transform 1 0 8367 0 1 944200
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_2\[5\]
+timestamp 1638492834
+transform 1 0 7631 0 1 931200
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_14
+timestamp 1638492834
+transform -1 0 709467 0 1 940600
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1\[6\]
+timestamp 1638492834
+transform -1 0 710203 0 1 927600
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_22
+timestamp 1638492834
+transform 0 1 161594 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_23
+timestamp 1638492834
+transform 0 1 110194 -1 0 1029341
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_2\[4\]
+timestamp 1638492834
+transform 0 1 97200 -1 0 1030077
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_2\[3\]
+timestamp 1638492834
+transform 0 1 148600 -1 0 1030077
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_21
+timestamp 1638492834
+transform 0 1 212994 -1 0 1029341
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_2\[2\]
+timestamp 1638492834
+transform 0 1 200000 -1 0 1030077
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_2\[1\]
+timestamp 1638492834
+transform 0 1 251400 -1 0 1030077
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_19
+timestamp 1638492834
+transform 0 1 315994 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_20
+timestamp 1638492834
+transform 0 1 264394 -1 0 1029341
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_2\[0\]
+timestamp 1638492834
+transform 0 1 303000 -1 0 1030077
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_17
+timestamp 1638492834
+transform 0 1 433794 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_18
+timestamp 1638492834
+transform 0 1 366394 -1 0 1029341
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1\[9\]
+timestamp 1638492834
+transform 0 1 420800 -1 0 1030077
+box 882 167 34000 13000
+use gpio_control_block  gpio_control_in_1\[10\]
+timestamp 1638492834
+transform 0 1 353400 -1 0 1030077
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_16
+timestamp 1638492834
+transform 0 1 510794 -1 0 1029341
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1\[8\]
+timestamp 1638492834
+transform 0 1 497800 -1 0 1030077
+box 882 167 34000 13000
+use gpio_defaults_block_1800 gpio_defaults_block_15
+timestamp 1638492834
+transform 0 1 562194 -1 0 1029341
+box -38 0 6018 2224
+use gpio_control_block  gpio_control_in_1\[7\]
+timestamp 1638492834
+transform 0 1 549200 -1 0 1030077
+box 882 167 34000 13000
+use chip_io  padframe
+timestamp 1638030917
+transform 1 0 0 0 1 0
+box 0 0 717600 1037600
+use caravel_power_routing  caravel_power_routing_0
+timestamp 1638492834
+transform 1 0 0 0 1 0
+box 0 0 717600 1037600
+use user_project_wrapper  mprj
+timestamp 1637147503
+transform 1 0 65308 0 1 278718
+box -8726 -7654 592650 711590
+<< labels >>
+flabel metal5 s 187640 6598 200160 19088 0 FreeSans 24000 0 0 0 clock
+port 0 nsew signal input
+flabel metal5 s 351040 6598 363560 19088 0 FreeSans 24000 0 0 0 flash_clk
+port 1 nsew signal tristate
+flabel metal5 s 296240 6598 308760 19088 0 FreeSans 24000 0 0 0 flash_csb
+port 2 nsew signal tristate
+flabel metal5 s 405840 6598 418360 19088 0 FreeSans 24000 0 0 0 flash_io0
+port 3 nsew signal tristate
+flabel metal5 s 460640 6598 473160 19088 0 FreeSans 24000 0 0 0 flash_io1
+port 4 nsew signal tristate
+flabel metal5 s 515440 6598 527960 19088 0 FreeSans 24000 0 0 0 gpio
+port 5 nsew signal bidirectional
+flabel metal5 s 698512 101240 711002 113760 0 FreeSans 24000 0 0 0 mprj_io[0]
+port 6 nsew signal bidirectional
+flabel metal5 s 698512 684440 711002 696960 0 FreeSans 24000 0 0 0 mprj_io[10]
+port 7 nsew signal bidirectional
+flabel metal5 s 698512 729440 711002 741960 0 FreeSans 24000 0 0 0 mprj_io[11]
+port 8 nsew signal bidirectional
+flabel metal5 s 698512 774440 711002 786960 0 FreeSans 24000 0 0 0 mprj_io[12]
+port 9 nsew signal bidirectional
+flabel metal5 s 698512 863640 711002 876160 0 FreeSans 24000 0 0 0 mprj_io[13]
+port 10 nsew signal bidirectional
+flabel metal5 s 698512 952840 711002 965360 0 FreeSans 24000 0 0 0 mprj_io[14]
+port 11 nsew signal bidirectional
+flabel metal5 s 628240 1018512 640760 1031002 0 FreeSans 24000 0 0 0 mprj_io[15]
+port 12 nsew signal bidirectional
+flabel metal5 s 526440 1018512 538960 1031002 0 FreeSans 24000 0 0 0 mprj_io[16]
+port 13 nsew signal bidirectional
+flabel metal5 s 475040 1018512 487560 1031002 0 FreeSans 24000 0 0 0 mprj_io[17]
+port 14 nsew signal bidirectional
+flabel metal5 s 386040 1018512 398560 1031002 0 FreeSans 24000 0 0 0 mprj_io[18]
+port 15 nsew signal bidirectional
+flabel metal5 s 284240 1018512 296760 1031002 0 FreeSans 24000 0 0 0 mprj_io[19]
+port 16 nsew signal bidirectional
+flabel metal5 s 698512 146440 711002 158960 0 FreeSans 24000 0 0 0 mprj_io[1]
+port 17 nsew signal bidirectional
+flabel metal5 s 232640 1018512 245160 1031002 0 FreeSans 24000 0 0 0 mprj_io[20]
+port 18 nsew signal bidirectional
+flabel metal5 s 181240 1018512 193760 1031002 0 FreeSans 24000 0 0 0 mprj_io[21]
+port 19 nsew signal bidirectional
+flabel metal5 s 129840 1018512 142360 1031002 0 FreeSans 24000 0 0 0 mprj_io[22]
+port 20 nsew signal bidirectional
+flabel metal5 s 78440 1018512 90960 1031002 0 FreeSans 24000 0 0 0 mprj_io[23]
+port 21 nsew signal bidirectional
+flabel metal5 s 6598 956440 19088 968960 0 FreeSans 24000 0 0 0 mprj_io[24]
+port 22 nsew signal bidirectional
+flabel metal5 s 6598 786640 19088 799160 0 FreeSans 24000 0 0 0 mprj_io[25]
+port 23 nsew signal bidirectional
+flabel metal5 s 6598 743440 19088 755960 0 FreeSans 24000 0 0 0 mprj_io[26]
+port 24 nsew signal bidirectional
+flabel metal5 s 6598 700240 19088 712760 0 FreeSans 24000 0 0 0 mprj_io[27]
+port 25 nsew signal bidirectional
+flabel metal5 s 6598 657040 19088 669560 0 FreeSans 24000 0 0 0 mprj_io[28]
+port 26 nsew signal bidirectional
+flabel metal5 s 6598 613840 19088 626360 0 FreeSans 24000 0 0 0 mprj_io[29]
+port 27 nsew signal bidirectional
+flabel metal5 s 698512 191440 711002 203960 0 FreeSans 24000 0 0 0 mprj_io[2]
+port 28 nsew signal bidirectional
+flabel metal5 s 6598 570640 19088 583160 0 FreeSans 24000 0 0 0 mprj_io[30]
+port 29 nsew signal bidirectional
+flabel metal5 s 6598 527440 19088 539960 0 FreeSans 24000 0 0 0 mprj_io[31]
+port 30 nsew signal bidirectional
+flabel metal5 s 6598 399840 19088 412360 0 FreeSans 24000 0 0 0 mprj_io[32]
+port 31 nsew signal bidirectional
+flabel metal5 s 6598 356640 19088 369160 0 FreeSans 24000 0 0 0 mprj_io[33]
+port 32 nsew signal bidirectional
+flabel metal5 s 6598 313440 19088 325960 0 FreeSans 24000 0 0 0 mprj_io[34]
+port 33 nsew signal bidirectional
+flabel metal5 s 6598 270240 19088 282760 0 FreeSans 24000 0 0 0 mprj_io[35]
+port 34 nsew signal bidirectional
+flabel metal5 s 6598 227040 19088 239560 0 FreeSans 24000 0 0 0 mprj_io[36]
+port 35 nsew signal bidirectional
+flabel metal5 s 6598 183840 19088 196360 0 FreeSans 24000 0 0 0 mprj_io[37]
+port 36 nsew signal bidirectional
+flabel metal5 s 698512 236640 711002 249160 0 FreeSans 24000 0 0 0 mprj_io[3]
+port 37 nsew signal bidirectional
+flabel metal5 s 698512 281640 711002 294160 0 FreeSans 24000 0 0 0 mprj_io[4]
+port 38 nsew signal bidirectional
+flabel metal5 s 698512 326640 711002 339160 0 FreeSans 24000 0 0 0 mprj_io[5]
+port 39 nsew signal bidirectional
+flabel metal5 s 698512 371840 711002 384360 0 FreeSans 24000 0 0 0 mprj_io[6]
+port 40 nsew signal bidirectional
+flabel metal5 s 698512 549040 711002 561560 0 FreeSans 24000 0 0 0 mprj_io[7]
+port 41 nsew signal bidirectional
+flabel metal5 s 698512 594240 711002 606760 0 FreeSans 24000 0 0 0 mprj_io[8]
+port 42 nsew signal bidirectional
+flabel metal5 s 698512 639240 711002 651760 0 FreeSans 24000 0 0 0 mprj_io[9]
+port 43 nsew signal bidirectional
+flabel metal5 s 136713 7143 144150 18309 0 FreeSans 24000 0 0 0 resetb
+port 44 nsew signal input
+flabel metal5 s 6167 70054 19619 80934 0 FreeSans 24000 0 0 0 vccd
+port 45 nsew signal bidirectional
+flabel metal5 s 697980 909666 711432 920546 0 FreeSans 24000 0 0 0 vccd1
+port 46 nsew signal bidirectional
+flabel metal5 s 6167 914054 19619 924934 0 FreeSans 24000 0 0 0 vccd2
+port 47 nsew signal bidirectional
+flabel metal5 s 624222 6811 636390 18975 0 FreeSans 24000 0 0 0 vdda
+port 48 nsew signal bidirectional
+flabel metal5 s 698624 819822 710788 831990 0 FreeSans 24000 0 0 0 vdda1
+port 49 nsew signal bidirectional
+flabel metal5 s 698624 505222 710788 517390 0 FreeSans 24000 0 0 0 vdda1_2
+port 50 nsew signal bidirectional
+flabel metal5 s 6811 484410 18975 496578 0 FreeSans 24000 0 0 0 vdda2
+port 51 nsew signal bidirectional
+flabel metal5 s 6811 111610 18975 123778 0 FreeSans 24000 0 0 0 vddio
+port 52 nsew signal bidirectional
+flabel metal5 s 6811 871210 18975 883378 0 FreeSans 24000 0 0 0 vddio_2
+port 53 nsew signal bidirectional
+flabel metal5 s 80222 6811 92390 18975 0 FreeSans 24000 0 0 0 vssa
+port 54 nsew signal bidirectional
+flabel metal5 s 577010 1018624 589178 1030788 0 FreeSans 24000 0 0 0 vssa1
+port 55 nsew signal bidirectional
+flabel metal5 s 698624 417022 710788 429190 0 FreeSans 24000 0 0 0 vssa1_2
+port 56 nsew signal bidirectional
+flabel metal5 s 6811 829010 18975 841178 0 FreeSans 24000 0 0 0 vssa2
+port 57 nsew signal bidirectional
+flabel metal5 s 243266 6167 254146 19619 0 FreeSans 24000 0 0 0 vssd
+port 58 nsew signal bidirectional
+flabel metal5 s 697980 461866 711432 472746 0 FreeSans 24000 0 0 0 vssd1
+port 59 nsew signal bidirectional
+flabel metal5 s 6167 442854 19619 453734 0 FreeSans 24000 0 0 0 vssd2
+port 60 nsew signal bidirectional
+flabel metal5 s 570422 6811 582590 18975 0 FreeSans 24000 0 0 0 vssio
+port 61 nsew signal bidirectional
+flabel metal5 s 334810 1018624 346978 1030788 0 FreeSans 24000 0 0 0 vssio_2
+port 62 nsew signal bidirectional
+flabel metal5 621960 246802 629984 249230 0 FreeSans 16000 0 0 0 vccd1_core
+flabel metal5 621948 250708 629990 253036 0 FreeSans 16000 0 0 0 vssd1_core
+flabel metal5 621550 262640 629508 265144 0 FreeSans 16000 0 0 0 vdda1_core
+flabel metal5 621514 266692 629472 269196 0 FreeSans 16000 0 0 0 vssa1_core
+flabel metal5 590480 230750 595228 233134 0 FreeSans 16000 0 0 0 vccd_core
+flabel metal5 590522 234770 595540 236910 0 FreeSans 16000 0 0 0 vssd_core
+flabel metal5 621512 258708 630212 261250 0 FreeSans 16000 0 0 0 vssa2_core
+flabel metal5 621598 254668 630298 257210 0 FreeSans 16000 0 0 0 vdda2_core
+flabel metal5 621936 242776 630636 245318 0 FreeSans 16000 0 0 0 vssd2_core
+flabel metal5 621794 238736 630494 241278 0 FreeSans 16000 0 0 0 vccd2_core
+<< properties >>
+string FIXED_BBOX 0 0 717600 1037600
+<< end >>
diff --git a/mag/compose_final.tcl b/mag/compose_final.tcl
new file mode 100644
index 0000000..1b0a775
--- /dev/null
+++ b/mag/compose_final.tcl
@@ -0,0 +1,28 @@
+#!/bin/env wish
+drc off
+random seed 131077
+load caravel -dereference
+property GDS_FILE /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/gds/caravel.gds
+property GDS_START 0
+select top cell
+set bbox [box values]
+load caravel_00020005_fill_pattern -quiet
+snap internal
+box values {*}$bbox
+paint comment
+property GDS_FILE /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/gds/caravel_00020005_fill_pattern.gds
+property GDS_START 0
+property FIXED_BBOX "$bbox"
+load caravel_00020005 -quiet
+box values 0 0 0 0
+box position 6um 6um
+getcell caravel child 0 0
+getcell caravel_00020005_fill_pattern child 0 0
+box position 0 0
+getcell advSeal_6um_gen
+puts stdout "Writing final GDS. . . "
+flush stdout
+gds undefined allow
+cif *hier write disable
+gds write /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/gds/caravel_00020005.gds
+quit -noprompt
diff --git a/mag/gpio_defaults_block_1800.mag b/mag/gpio_defaults_block_1800.mag
new file mode 100644
index 0000000..5e064c7
--- /dev/null
+++ b/mag/gpio_defaults_block_1800.mag
@@ -0,0 +1,1461 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1638587925
+<< viali >>
+rect 1087 833 1121 867
+rect 1639 833 1673 867
+rect 4583 833 4617 867
+rect 1225 765 1259 799
+rect 1915 765 1949 799
+rect 2191 765 2225 799
+rect 2513 765 2547 799
+rect 2973 765 3007 799
+rect 3433 765 3467 799
+rect 3893 765 3927 799
+rect 4353 765 4387 799
+rect 4813 765 4847 799
+rect 5273 765 5307 799
+<< metal1 >>
+rect 0 2202 5980 2224
+rect 0 2150 78 2202
+rect 130 2150 142 2202
+rect 194 2150 206 2202
+rect 258 2150 270 2202
+rect 322 2150 1478 2202
+rect 1530 2150 1542 2202
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+rect 2994 2150 3006 2202
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+rect 3122 2150 4278 2202
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+rect 4522 2150 5980 2202
+rect 0 2128 5980 2150
+rect 0 1658 5980 1680
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+rect 5222 1606 5980 1658
+rect 0 1584 5980 1606
+rect 0 1114 5980 1136
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+rect 194 1062 206 1114
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+rect 322 1062 1478 1114
+rect 1530 1062 1542 1114
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+rect 0 1040 5980 1062
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+rect 4161 768 4344 796
+rect 4200 756 4264 768
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+rect 4759 768 4804 796
+rect 4798 756 4804 768
+rect 4856 796 4862 808
+rect 4936 796 5000 808
+rect 5258 796 5264 808
+rect 4856 768 5000 796
+rect 5219 768 5264 796
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+rect 5316 796 5322 808
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+rect 5316 768 5460 796
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+rect 1636 728 1722 756
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+rect 716 688 722 700
+rect 0 570 5980 592
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+rect 1022 518 2178 570
+rect 2230 518 2242 570
+rect 2294 518 2306 570
+rect 2358 518 2370 570
+rect 2422 518 3578 570
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+rect 3694 518 3706 570
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+rect 3822 518 4978 570
+rect 5030 518 5042 570
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+rect 5158 518 5170 570
+rect 5222 518 5980 570
+rect 0 496 5980 518
+<< via1 >>
+rect 78 2150 130 2202
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+<< via2 >>
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+<< via3 >>
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+rect 4448 1060 4452 1116
+rect 4452 1060 4508 1116
+rect 4508 1060 4512 1116
+rect 4448 1056 4512 1060
+rect 788 572 852 576
+rect 788 516 792 572
+rect 792 516 848 572
+rect 848 516 852 572
+rect 788 512 852 516
+rect 868 572 932 576
+rect 868 516 872 572
+rect 872 516 928 572
+rect 928 516 932 572
+rect 868 512 932 516
+rect 948 572 1012 576
+rect 948 516 952 572
+rect 952 516 1008 572
+rect 1008 516 1012 572
+rect 948 512 1012 516
+rect 2188 572 2252 576
+rect 2188 516 2192 572
+rect 2192 516 2248 572
+rect 2248 516 2252 572
+rect 2188 512 2252 516
+rect 2268 572 2332 576
+rect 2268 516 2272 572
+rect 2272 516 2328 572
+rect 2328 516 2332 572
+rect 2268 512 2332 516
+rect 2348 572 2412 576
+rect 2348 516 2352 572
+rect 2352 516 2408 572
+rect 2408 516 2412 572
+rect 2348 512 2412 516
+rect 3588 572 3652 576
+rect 3588 516 3592 572
+rect 3592 516 3648 572
+rect 3648 516 3652 572
+rect 3588 512 3652 516
+rect 3668 572 3732 576
+rect 3668 516 3672 572
+rect 3672 516 3728 572
+rect 3728 516 3732 572
+rect 3668 512 3732 516
+rect 3748 572 3812 576
+rect 3748 516 3752 572
+rect 3752 516 3808 572
+rect 3808 516 3812 572
+rect 3748 512 3812 516
+rect 4988 572 5052 576
+rect 4988 516 4992 572
+rect 4992 516 5048 572
+rect 5048 516 5052 572
+rect 4988 512 5052 516
+rect 5068 572 5132 576
+rect 5068 516 5072 572
+rect 5072 516 5128 572
+rect 5128 516 5132 572
+rect 5068 512 5132 516
+rect 5148 572 5212 576
+rect 5148 516 5152 572
+rect 5152 516 5208 572
+rect 5208 516 5212 572
+rect 5148 512 5212 516
+<< metal4 >>
+rect 60 2208 340 2224
+rect 60 2144 88 2208
+rect 152 2144 168 2208
+rect 232 2144 248 2208
+rect 312 2144 340 2208
+rect 60 1120 340 2144
+rect 60 1056 88 1120
+rect 152 1056 168 1120
+rect 232 1056 248 1120
+rect 312 1056 340 1120
+rect 60 1014 340 1056
+rect 60 778 82 1014
+rect 318 778 340 1014
+rect 60 496 340 778
+rect 760 1714 1040 2224
+rect 760 1478 782 1714
+rect 1018 1478 1040 1714
+rect 760 576 1040 1478
+rect 760 512 788 576
+rect 852 512 868 576
+rect 932 512 948 576
+rect 1012 512 1040 576
+rect 760 496 1040 512
+rect 1460 2208 1740 2224
+rect 1460 2144 1488 2208
+rect 1552 2144 1568 2208
+rect 1632 2144 1648 2208
+rect 1712 2144 1740 2208
+rect 1460 1120 1740 2144
+rect 1460 1056 1488 1120
+rect 1552 1056 1568 1120
+rect 1632 1056 1648 1120
+rect 1712 1056 1740 1120
+rect 1460 1014 1740 1056
+rect 1460 778 1482 1014
+rect 1718 778 1740 1014
+rect 1460 496 1740 778
+rect 2160 1714 2440 2224
+rect 2160 1478 2182 1714
+rect 2418 1478 2440 1714
+rect 2160 576 2440 1478
+rect 2160 512 2188 576
+rect 2252 512 2268 576
+rect 2332 512 2348 576
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+rect 2160 496 2440 512
+rect 2860 2208 3140 2224
+rect 2860 2144 2888 2208
+rect 2952 2144 2968 2208
+rect 3032 2144 3048 2208
+rect 3112 2144 3140 2208
+rect 2860 1120 3140 2144
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+rect 2952 1056 2968 1120
+rect 3032 1056 3048 1120
+rect 3112 1056 3140 1120
+rect 2860 1014 3140 1056
+rect 2860 778 2882 1014
+rect 3118 778 3140 1014
+rect 2860 496 3140 778
+rect 3560 1714 3840 2224
+rect 3560 1478 3582 1714
+rect 3818 1478 3840 1714
+rect 3560 576 3840 1478
+rect 3560 512 3588 576
+rect 3652 512 3668 576
+rect 3732 512 3748 576
+rect 3812 512 3840 576
+rect 3560 496 3840 512
+rect 4260 2208 4540 2224
+rect 4260 2144 4288 2208
+rect 4352 2144 4368 2208
+rect 4432 2144 4448 2208
+rect 4512 2144 4540 2208
+rect 4260 1120 4540 2144
+rect 4260 1056 4288 1120
+rect 4352 1056 4368 1120
+rect 4432 1056 4448 1120
+rect 4512 1056 4540 1120
+rect 4260 1014 4540 1056
+rect 4260 778 4282 1014
+rect 4518 778 4540 1014
+rect 4260 496 4540 778
+rect 4960 1714 5240 2224
+rect 4960 1478 4982 1714
+rect 5218 1478 5240 1714
+rect 4960 576 5240 1478
+rect 4960 512 4988 576
+rect 5052 512 5068 576
+rect 5132 512 5148 576
+rect 5212 512 5240 576
+rect 4960 496 5240 512
+<< via4 >>
+rect 82 778 318 1014
+rect 782 1664 1018 1714
+rect 782 1600 788 1664
+rect 788 1600 852 1664
+rect 852 1600 868 1664
+rect 868 1600 932 1664
+rect 932 1600 948 1664
+rect 948 1600 1012 1664
+rect 1012 1600 1018 1664
+rect 782 1478 1018 1600
+rect 1482 778 1718 1014
+rect 2182 1664 2418 1714
+rect 2182 1600 2188 1664
+rect 2188 1600 2252 1664
+rect 2252 1600 2268 1664
+rect 2268 1600 2332 1664
+rect 2332 1600 2348 1664
+rect 2348 1600 2412 1664
+rect 2412 1600 2418 1664
+rect 2182 1478 2418 1600
+rect 2882 778 3118 1014
+rect 3582 1664 3818 1714
+rect 3582 1600 3588 1664
+rect 3588 1600 3652 1664
+rect 3652 1600 3668 1664
+rect 3668 1600 3732 1664
+rect 3732 1600 3748 1664
+rect 3748 1600 3812 1664
+rect 3812 1600 3818 1664
+rect 3582 1478 3818 1600
+rect 4282 778 4518 1014
+rect 4982 1664 5218 1714
+rect 4982 1600 4988 1664
+rect 4988 1600 5052 1664
+rect 5052 1600 5068 1664
+rect 5068 1600 5132 1664
+rect 5132 1600 5148 1664
+rect 5148 1600 5212 1664
+rect 5212 1600 5218 1664
+rect 4982 1478 5218 1600
+<< metal5 >>
+rect 0 1714 5980 1756
+rect 0 1478 782 1714
+rect 1018 1478 2182 1714
+rect 2418 1478 3582 1714
+rect 3818 1478 4982 1714
+rect 5218 1478 5980 1714
+rect 0 1436 5980 1478
+rect 0 1014 5980 1056
+rect 0 778 82 1014
+rect 318 778 1482 1014
+rect 1718 778 2882 1014
+rect 3118 778 4282 1014
+rect 4518 778 5980 1014
+rect 0 736 5980 778
+use sky130_fd_sc_hd__fill_1  FILLER_0_9 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 828 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_2 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 0 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_0
+timestamp 1638322937
+transform 1 0 0 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 1 544
+box -38 -48 590 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 920 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_15
+timestamp 1638322937
+transform 1 0 1380 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[5\]
+timestamp 1638322937
+transform 1 0 2300 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[1\]
+timestamp 1638322937
+transform 1 0 1196 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[4\]
+timestamp 1638322937
+transform 1 0 2024 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[3\]
+timestamp 1638322937
+transform 1 0 1748 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[2\]
+timestamp 1638322937
+transform 1 0 1472 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_6 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 2576 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_38 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 3496 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_33
+timestamp 1638322937
+transform 1 0 3036 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_29
+timestamp 1638322937
+transform 1 0 2668 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_27
+timestamp 1638322937
+transform 1 0 2484 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[7\]
+timestamp 1638322937
+transform 1 0 3220 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[6\]
+timestamp 1638322937
+transform 1 0 2760 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_43
+timestamp 1638322937
+transform 1 0 3956 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_51 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 4692 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_48
+timestamp 1638322937
+transform 1 0 4416 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_39
+timestamp 1638322937
+transform 1 0 3588 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[9\]
+timestamp 1638322937
+transform 1 0 4140 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[8\]
+timestamp 1638322937
+transform 1 0 3680 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[12\]
+timestamp 1638322937
+transform 1 0 4508 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_8
+timestamp 1638322937
+transform 1 0 5152 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_7
+timestamp 1638322937
+transform 1 0 5152 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_55
+timestamp 1638322937
+transform 1 0 5060 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_55
+timestamp 1638322937
+transform 1 0 5060 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[10\]
+timestamp 1638322937
+transform 1 0 4784 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_60
+timestamp 1638322937
+transform 1 0 5520 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_57
+timestamp 1638322937
+transform 1 0 5244 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_61
+timestamp 1638322937
+transform 1 0 5612 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[11\]
+timestamp 1638322937
+transform 1 0 5244 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_3
+timestamp 1638322937
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_1
+timestamp 1638322937
+transform -1 0 5980 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_4
+timestamp 1638322937
+transform 1 0 0 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_3
+timestamp 1638322937
+transform 1 0 276 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_15
+timestamp 1638322937
+transform 1 0 1380 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_9
+timestamp 1638322937
+transform 1 0 2576 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_27
+timestamp 1638322937
+transform 1 0 2484 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_29
+timestamp 1638322937
+transform 1 0 2668 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_41
+timestamp 1638322937
+transform 1 0 3772 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_10
+timestamp 1638322937
+transform 1 0 5152 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_2_57
+timestamp 1638322937
+transform 1 0 5244 0 1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_61
+timestamp 1638322937
+transform 1 0 5612 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_5
+timestamp 1638322937
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  FILLER_2_53
+timestamp 1638322937
+transform 1 0 4876 0 1 1632
+box -38 -48 314 592
+<< labels >>
+rlabel metal5 s 0 1436 5980 1756 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 760 496 1040 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 2160 496 2440 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 3560 496 3840 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 4960 496 5240 2224 6 VGND
+port 0 nsew ground input
+rlabel metal5 s 0 736 5980 1056 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 60 496 340 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 1460 496 1740 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 2860 496 3140 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 4260 496 4540 2224 6 VPWR
+port 1 nsew power input
+rlabel metal2 s 202 0 258 400 6 gpio_defaults[0]
+port 2 nsew signal tristate
+rlabel metal2 s 4802 0 4858 400 6 gpio_defaults[10]
+port 3 nsew signal tristate
+rlabel metal2 s 5262 0 5318 400 6 gpio_defaults[11]
+port 4 nsew signal tristate
+rlabel metal2 s 5722 0 5778 400 6 gpio_defaults[12]
+port 5 nsew signal tristate
+rlabel metal2 s 662 0 718 400 6 gpio_defaults[1]
+port 6 nsew signal tristate
+rlabel metal2 s 1122 0 1178 400 6 gpio_defaults[2]
+port 7 nsew signal tristate
+rlabel metal2 s 1582 0 1638 400 6 gpio_defaults[3]
+port 8 nsew signal tristate
+rlabel metal2 s 2042 0 2098 400 6 gpio_defaults[4]
+port 9 nsew signal tristate
+rlabel metal2 s 2502 0 2558 400 6 gpio_defaults[5]
+port 10 nsew signal tristate
+rlabel metal2 s 2962 0 3018 400 6 gpio_defaults[6]
+port 11 nsew signal tristate
+rlabel metal2 s 3422 0 3478 400 6 gpio_defaults[7]
+port 12 nsew signal tristate
+rlabel metal2 s 3882 0 3938 400 6 gpio_defaults[8]
+port 13 nsew signal tristate
+rlabel metal2 s 4342 0 4398 400 6 gpio_defaults[9]
+port 14 nsew signal tristate
+<< properties >>
+string FIXED_BBOX 0 0 6000 2200
+<< end >>
diff --git a/mag/mag2gds_caravel.tcl b/mag/mag2gds_caravel.tcl
new file mode 100644
index 0000000..12c9d1e
--- /dev/null
+++ b/mag/mag2gds_caravel.tcl
@@ -0,0 +1 @@
+	random seed 131077; 	drc off; 	crashbackups stop; 	addpath hexdigits; 	addpath /mnt/shuttles/shuttle/mpw-two/caravel/mag; 	addpath /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag; 	load user_project_wrapper; 	property LEFview true; 	property GDS_FILE /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/gds/user_project_wrapper.gds; 	property GDS_START 0; 	load mgmt_core_wrapper; 	property LEFview true; 	property GDS_FILE ../mgmt_core_wrapper/gds/mgmt_core_wrapper.gds; 	property GDS_START 0; 	load /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/user_id_programming; 	load /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/user_id_textblock; 	load ../maglef/simple_por; 	load /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/caravel -dereference; 	select top cell; 	expand; 	cif *hier write disable; 	cif *array write disable; 	gds write /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/gds/caravel.gds; 	quit -noprompt;
diff --git a/mag/user_id_programming.mag b/mag/user_id_programming.mag
new file mode 100644
index 0000000..85bc0f4
--- /dev/null
+++ b/mag/user_id_programming.mag
@@ -0,0 +1,3159 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1638030917
+<< nwell >>
+rect 2304 2369 2397 2389
+<< viali >>
+rect 4353 5117 4387 5151
+rect 5273 5117 5307 5151
+rect 2145 4641 2179 4675
+rect 3249 4641 3283 4675
+rect 3617 4641 3651 4675
+rect 4721 4641 4755 4675
+rect 1593 4029 1627 4063
+rect 2053 4029 2087 4063
+rect 4445 4029 4479 4063
+rect 4721 4029 4755 4063
+rect 5549 4029 5583 4063
+rect 1685 3553 1719 3587
+rect 1961 3553 1995 3587
+rect 2697 3553 2731 3587
+rect 3157 3553 3191 3587
+rect 3433 3553 3467 3587
+rect 4261 3553 4295 3587
+rect 4813 3553 4847 3587
+rect 5273 3553 5307 3587
+rect 1593 2941 1627 2975
+rect 4813 2397 4847 2431
+rect 5089 2397 5123 2431
+rect 1593 1853 1627 1887
+rect 2145 1853 2179 1887
+rect 2605 1853 2639 1887
+rect 2881 1853 2915 1887
+rect 3249 1853 3283 1887
+rect 4077 1853 4111 1887
+rect 5641 1853 5675 1887
+rect 1685 1377 1719 1411
+rect 2973 1377 3007 1411
+rect 4629 1377 4663 1411
+<< metal1 >>
+rect 1104 6010 5980 6032
+rect 1104 5958 2607 6010
+rect 2659 5958 2671 6010
+rect 2723 5958 2735 6010
+rect 2787 5958 2799 6010
+rect 2851 5958 4232 6010
+rect 4284 5958 4296 6010
+rect 4348 5958 4360 6010
+rect 4412 5958 4424 6010
+rect 4476 5958 5980 6010
+rect 1104 5936 5980 5958
+rect 1104 5466 5980 5488
+rect 1104 5414 1794 5466
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+rect 5175 1060 5179 1116
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+rect 5255 1116 5319 1120
+rect 5255 1060 5259 1116
+rect 5259 1060 5315 1116
+rect 5315 1060 5319 1116
+rect 5255 1056 5319 1060
+<< metal4 >>
+rect 1756 5472 2076 6032
+rect 1756 5408 1764 5472
+rect 1828 5408 1844 5472
+rect 1908 5408 1924 5472
+rect 1988 5408 2004 5472
+rect 2068 5408 2076 5472
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+rect 1756 4384 2076 5002
+rect 1756 4320 1764 4384
+rect 1828 4320 1844 4384
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+rect 1756 3606 2076 4320
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+rect 1756 3296 2076 3370
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+rect 1756 2208 2076 3232
+rect 1756 2144 1764 2208
+rect 1828 2144 1844 2208
+rect 1908 2144 1924 2208
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+rect 1756 1738 1798 1974
+rect 2034 1738 2076 1974
+rect 1756 1120 2076 1738
+rect 1756 1056 1764 1120
+rect 1828 1056 1844 1120
+rect 1908 1056 1924 1120
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+rect 1756 1040 2076 1056
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+rect 5239 1056 5255 1120
+rect 5319 1056 5327 1120
+rect 5007 1040 5327 1056
+<< via4 >>
+rect 1798 5002 2034 5238
+rect 1798 3370 2034 3606
+rect 1798 1738 2034 1974
+rect 2611 4186 2847 4422
+rect 2611 2752 2847 2790
+rect 2611 2688 2641 2752
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+rect 2657 2688 2721 2752
+rect 2721 2688 2737 2752
+rect 2737 2688 2801 2752
+rect 2801 2688 2817 2752
+rect 2817 2688 2847 2752
+rect 2611 2554 2847 2688
+rect 3424 5002 3660 5238
+rect 3424 3370 3660 3606
+rect 3424 1738 3660 1974
+rect 4236 4186 4472 4422
+rect 4236 2752 4472 2790
+rect 4236 2688 4266 2752
+rect 4266 2688 4282 2752
+rect 4282 2688 4346 2752
+rect 4346 2688 4362 2752
+rect 4362 2688 4426 2752
+rect 4426 2688 4442 2752
+rect 4442 2688 4472 2752
+rect 4236 2554 4472 2688
+rect 5049 5002 5285 5238
+rect 5049 3370 5285 3606
+rect 5049 1738 5285 1974
+<< metal5 >>
+rect 1104 5238 5980 5280
+rect 1104 5002 1798 5238
+rect 2034 5002 3424 5238
+rect 3660 5002 5049 5238
+rect 5285 5002 5980 5238
+rect 1104 4960 5980 5002
+rect 1104 4422 5980 4464
+rect 1104 4186 2611 4422
+rect 2847 4186 4236 4422
+rect 4472 4186 5980 4422
+rect 1104 4144 5980 4186
+rect 1104 3606 5980 3648
+rect 1104 3370 1798 3606
+rect 2034 3370 3424 3606
+rect 3660 3370 5049 3606
+rect 5285 3370 5980 3606
+rect 1104 3328 5980 3370
+rect 1104 2790 5980 2832
+rect 1104 2554 2611 2790
+rect 2847 2554 4236 2790
+rect 4472 2554 5980 2790
+rect 1104 2512 5980 2554
+rect 1104 1974 5980 2016
+rect 1104 1738 1798 1974
+rect 2034 1738 3424 1974
+rect 3660 1738 5049 1974
+rect 5285 1738 5980 1974
+rect 1104 1696 5980 1738
+use sky130_fd_sc_hd__fill_1  FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 1380 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  FILLER_1_6 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 1656 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_2
+timestamp 1638025753
+transform 1 0 1104 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_0
+timestamp 1638025753
+transform 1 0 1104 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[3\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 1380 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[28\]
+timestamp 1638025753
+transform 1 0 1932 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[27\]
+timestamp 1638025753
+transform 1 0 1472 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_1_12 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 2208 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_8  FILLER_0_7 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 1748 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_20
+timestamp 1638025753
+transform 1 0 2944 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  FILLER_0_15
+timestamp 1638025753
+transform 1 0 2484 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[20\]
+timestamp 1638025753
+transform 1 0 2760 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[1\]
+timestamp 1638025753
+transform 1 0 3036 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[11\]
+timestamp 1638025753
+transform 1 0 2668 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[0\]
+timestamp 1638025753
+transform 1 0 2392 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6  FILLER_1_24 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3312 0 1 1632
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_8  FILLER_0_21
+timestamp 1638025753
+transform 1 0 3036 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_4  FILLER_0_32 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 4048 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_33 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 4140 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_18 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3956 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[7\]
+timestamp 1638025753
+transform 1 0 3864 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[15\]
+timestamp 1638025753
+transform 1 0 4416 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_29
+timestamp 1638025753
+transform 1 0 3772 0 -1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_3  FILLER_0_47
+timestamp 1638025753
+transform 1 0 5428 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_3
+timestamp 1638025753
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_1
+timestamp 1638025753
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[4\]
+timestamp 1638025753
+transform 1 0 5428 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_1_45
+timestamp 1638025753
+transform 1 0 5244 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_8  FILLER_0_39
+timestamp 1638025753
+transform 1 0 4692 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3  PHY_4
+timestamp 1638025753
+transform 1 0 1104 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_15
+timestamp 1638025753
+transform 1 0 2484 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_4  FILLER_2_27
+timestamp 1638025753
+transform 1 0 3588 0 -1 2720
+box -38 -48 406 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_19
+timestamp 1638025753
+transform 1 0 3956 0 -1 2720
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[13\]
+timestamp 1638025753
+transform 1 0 4600 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6  FILLER_2_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3  PHY_5
+timestamp 1638025753
+transform -1 0 5980 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[9\]
+timestamp 1638025753
+transform 1 0 4876 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6  FILLER_2_44
+timestamp 1638025753
+transform 1 0 5152 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3  PHY_6
+timestamp 1638025753
+transform 1 0 1104 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_3_6
+timestamp 1638025753
+transform 1 0 1656 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[31\]
+timestamp 1638025753
+transform 1 0 1380 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_3_18
+timestamp 1638025753
+transform 1 0 2760 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_3_30
+timestamp 1638025753
+transform 1 0 3864 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_3  PHY_7
+timestamp 1638025753
+transform -1 0 5980 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_8  FILLER_3_42
+timestamp 1638025753
+transform 1 0 4968 0 1 2720
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_1  FILLER_4_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_4_10
+timestamp 1638025753
+transform 1 0 2024 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_3  PHY_8
+timestamp 1638025753
+transform 1 0 1104 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[24\]
+timestamp 1638025753
+transform 1 0 1748 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[17\]
+timestamp 1638025753
+transform 1 0 1472 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1  FILLER_4_14
+timestamp 1638025753
+transform 1 0 2392 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[8\]
+timestamp 1638025753
+transform 1 0 3220 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[25\]
+timestamp 1638025753
+transform 1 0 2944 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[14\]
+timestamp 1638025753
+transform 1 0 2484 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_4_18
+timestamp 1638025753
+transform 1 0 2760 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1  FILLER_4_30
+timestamp 1638025753
+transform 1 0 3864 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_4_26
+timestamp 1638025753
+transform 1 0 3496 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_3  FILLER_4_35
+timestamp 1638025753
+transform 1 0 4324 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_20
+timestamp 1638025753
+transform 1 0 3956 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[22\]
+timestamp 1638025753
+transform 1 0 4048 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[16\]
+timestamp 1638025753
+transform 1 0 4600 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_4  FILLER_4_46
+timestamp 1638025753
+transform 1 0 5336 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_3  PHY_9
+timestamp 1638025753
+transform -1 0 5980 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[26\]
+timestamp 1638025753
+transform 1 0 5060 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_4_41
+timestamp 1638025753
+transform 1 0 4876 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_3  PHY_10
+timestamp 1638025753
+transform 1 0 1104 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_5_11
+timestamp 1638025753
+transform 1 0 2116 0 1 3808
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[6\]
+timestamp 1638025753
+transform 1 0 1380 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[2\]
+timestamp 1638025753
+transform 1 0 1840 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_5_6
+timestamp 1638025753
+transform 1 0 1656 0 1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_8  FILLER_5_23
+timestamp 1638025753
+transform 1 0 3220 0 1 3808
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3  FILLER_5_31
+timestamp 1638025753
+transform 1 0 3956 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[18\]
+timestamp 1638025753
+transform 1 0 4508 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[10\]
+timestamp 1638025753
+transform 1 0 4232 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1  FILLER_5_49
+timestamp 1638025753
+transform 1 0 5612 0 1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_11
+timestamp 1638025753
+transform -1 0 5980 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[29\]
+timestamp 1638025753
+transform 1 0 5336 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6  FILLER_5_40
+timestamp 1638025753
+transform 1 0 4784 0 1 3808
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3  PHY_14
+timestamp 1638025753
+transform 1 0 1104 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_12
+timestamp 1638025753
+transform 1 0 1104 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_7_3
+timestamp 1638025753
+transform 1 0 1380 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[19\]
+timestamp 1638025753
+transform 1 0 1932 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6  FILLER_6_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_8  FILLER_6_12
+timestamp 1638025753
+transform 1 0 2208 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_1  FILLER_6_24
+timestamp 1638025753
+transform 1 0 3312 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_6_20
+timestamp 1638025753
+transform 1 0 2944 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_7_15
+timestamp 1638025753
+transform 1 0 2484 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[30\]
+timestamp 1638025753
+transform 1 0 3036 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[21\]
+timestamp 1638025753
+transform 1 0 3404 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1  FILLER_6_36
+timestamp 1638025753
+transform 1 0 4416 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_6_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_3  FILLER_6_28
+timestamp 1638025753
+transform 1 0 3680 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_21
+timestamp 1638025753
+transform 1 0 3956 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[5\]
+timestamp 1638025753
+transform 1 0 4140 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[12\]
+timestamp 1638025753
+transform 1 0 4508 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6  FILLER_7_36
+timestamp 1638025753
+transform 1 0 4416 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_6  FILLER_7_27
+timestamp 1638025753
+transform 1 0 3588 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__fill_1  FILLER_7_42
+timestamp 1638025753
+transform 1 0 4968 0 1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_7_46
+timestamp 1638025753
+transform 1 0 5336 0 1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_3  PHY_15
+timestamp 1638025753
+transform -1 0 5980 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_13
+timestamp 1638025753
+transform -1 0 5980 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[23\]
+timestamp 1638025753
+transform 1 0 5060 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_6_48
+timestamp 1638025753
+transform 1 0 5520 0 -1 4896
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_8  FILLER_6_40
+timestamp 1638025753
+transform 1 0 4784 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3  PHY_16
+timestamp 1638025753
+transform 1 0 1104 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_8_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_8_15
+timestamp 1638025753
+transform 1 0 2484 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_4  FILLER_8_27
+timestamp 1638025753
+transform 1 0 3588 0 -1 5984
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12  FILLER_8_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_22
+timestamp 1638025753
+transform 1 0 3956 0 -1 5984
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_17
+timestamp 1638025753
+transform -1 0 5980 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6  FILLER_8_44
+timestamp 1638025753
+transform 1 0 5152 0 -1 5984
+box -38 -48 590 592
+<< labels >>
+rlabel metal2 s 4066 6277 4122 7077 4 mask_rev[0]
+port 1 nsew
+rlabel metal2 s 4066 0 4122 800 4 mask_rev[10]
+port 2 nsew
+rlabel metal2 s 1122 0 1178 800 4 mask_rev[11]
+port 3 nsew
+rlabel metal2 s 570 0 626 800 4 mask_rev[12]
+port 4 nsew
+rlabel metal2 s 5354 6277 5410 7077 4 mask_rev[13]
+port 5 nsew
+rlabel metal2 s 5906 0 5962 800 4 mask_rev[14]
+port 6 nsew
+rlabel metal3 s 6309 1640 7109 1760 4 mask_rev[15]
+port 7 nsew
+rlabel metal2 s 2226 0 2282 800 4 mask_rev[16]
+port 8 nsew
+rlabel metal2 s 1674 6277 1730 7077 4 mask_rev[17]
+port 9 nsew
+rlabel metal3 s 0 5176 800 5296 4 mask_rev[18]
+port 10 nsew
+rlabel metal2 s 2962 6277 3018 7077 4 mask_rev[19]
+port 11 nsew
+rlabel metal3 s 0 3272 800 3392 4 mask_rev[1]
+port 12 nsew
+rlabel metal3 s 6309 2456 7109 2576 4 mask_rev[20]
+port 13 nsew
+rlabel metal3 s 6309 824 7109 944 4 mask_rev[21]
+port 14 nsew
+rlabel metal3 s 0 5992 800 6112 4 mask_rev[22]
+port 15 nsew
+rlabel metal2 s 1674 0 1730 800 4 mask_rev[23]
+port 16 nsew
+rlabel metal2 s 5906 6277 5962 7077 4 mask_rev[24]
+port 17 nsew
+rlabel metal3 s 0 1640 800 1760 4 mask_rev[25]
+port 18 nsew
+rlabel metal2 s 4802 6277 4858 7077 4 mask_rev[26]
+port 19 nsew
+rlabel metal2 s 1122 6277 1178 7077 4 mask_rev[27]
+port 20 nsew
+rlabel metal2 s 6458 6277 6514 7077 4 mask_rev[28]
+port 21 nsew
+rlabel metal2 s 5354 0 5410 800 4 mask_rev[29]
+port 22 nsew
+rlabel metal3 s 0 2456 800 2576 4 mask_rev[2]
+port 23 nsew
+rlabel metal3 s 6309 5176 7109 5296 4 mask_rev[30]
+port 24 nsew
+rlabel metal2 s 2962 0 3018 800 4 mask_rev[31]
+port 25 nsew
+rlabel metal2 s 3514 0 3570 800 4 mask_rev[3]
+port 26 nsew
+rlabel metal3 s 6309 3544 7109 3664 4 mask_rev[4]
+port 27 nsew
+rlabel metal3 s 6309 4360 7109 4480 4 mask_rev[5]
+port 28 nsew
+rlabel metal3 s 0 4360 800 4480 4 mask_rev[6]
+port 29 nsew
+rlabel metal2 s 3514 6277 3570 7077 4 mask_rev[7]
+port 30 nsew
+rlabel metal2 s 4802 0 4858 800 4 mask_rev[8]
+port 31 nsew
+rlabel metal2 s 2226 6277 2282 7077 4 mask_rev[9]
+port 32 nsew
+rlabel metal5 s 1104 1696 5980 2016 4 VPWR
+port 33 nsew
+rlabel metal5 s 1104 2512 5980 2832 4 VGND
+port 34 nsew
+<< properties >>
+string FIXED_BBOX 0 0 7109 7077
+string GDS_FILE ../gds/user_id_programming.gds
+string GDS_START 0
+<< end >>
diff --git a/mag/user_id_textblock.mag b/mag/user_id_textblock.mag
new file mode 100644
index 0000000..5e50c6c
--- /dev/null
+++ b/mag/user_id_textblock.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+timestamp 1608324878
+<< checkpaint >>
+rect 1495 5490 6500 6570
+rect -630 428 19262 5490
+rect -630 -630 6210 428
+rect 16092 356 18972 428
+<< fillblock >>
+rect -328 754 16860 5172
+use alpha_5  alphaX_0 hexdigits
+timestamp 1598786981
+transform 1 0 14887 0 1 1080
+box 0 0 1620 3780
+use alpha_0  alphaX_1 hexdigits
+timestamp 1598786981
+transform 1 0 12750 0 1 1080
+box 0 0 1620 3780
+use alpha_0  alphaX_2
+timestamp 1598786981
+transform 1 0 10625 0 1 1080
+box 0 0 1620 3780
+use alpha_0  alphaX_3
+timestamp 1598786981
+transform 1 0 8500 0 1 1080
+box 0 0 1620 3780
+use alpha_2  alphaX_4 hexdigits
+timestamp 1598786981
+transform 1 0 6375 0 1 1080
+box 0 0 1620 3780
+use alpha_0  alphaX_5
+timestamp 1598786981
+transform 1 0 4250 0 1 1080
+box 0 0 1620 3780
+use alpha_0  alphaX_6
+timestamp 1598786981
+transform 1 0 2125 0 1 1080
+box 0 0 1620 3780
+use alpha_0  alphaX_7
+timestamp 1598786981
+transform 1 0 0 0 1 1080
+box 0 0 1620 3780
+<< end >>
diff --git a/signoff/.gitignore b/signoff/.gitignore
new file mode 100644
index 0000000..6407046
--- /dev/null
+++ b/signoff/.gitignore
@@ -0,0 +1 @@
+cdrcpost/*
diff --git a/signoff/build/__gpio_defaults.out b/signoff/build/__gpio_defaults.out
new file mode 100644
index 0000000..772520d
--- /dev/null
+++ b/signoff/build/__gpio_defaults.out
@@ -0,0 +1 @@
+GPIO defaults completed.
diff --git a/signoff/build/final_build.out b/signoff/build/final_build.out
new file mode 100644
index 0000000..814678a
--- /dev/null
+++ b/signoff/build/final_build.out
@@ -0,0 +1 @@
+Final build completed.
diff --git a/signoff/build/generate_fill.out b/signoff/build/generate_fill.out
new file mode 100644
index 0000000..5c30c7a
--- /dev/null
+++ b/signoff/build/generate_fill.out
@@ -0,0 +1,30569 @@
+This script will generate files caravel_00020005_fill_pattern_x_y.gds
+Now generating fill patterns.  This may take. . . quite. . . a while.
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill.tcl" from command line.
+Started: 12/09/2021 16:06:02
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: caravel
+Reading "caravel_logo".
+Reading "open_source".
+Reading "sky130_fd_sc_hvl__decap_8".
+Reading "sky130_fd_sc_hvl__diode_2".
+Reading "sky130_fd_sc_hvl__decap_4".
+Reading "sky130_fd_sc_hvl__fill_2".
+Reading "sky130_fd_sc_hvl__fill_1".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "xres_buf".
+Reading "font_22".
+Reading "font_73".
+Reading "font_43".
+Reading "font_49".
+Reading "font_65".
+Reading "font_68".
+Reading "font_54".
+Reading "font_67".
+Reading "font_6E".
+Reading "font_69".
+Reading "font_6C".
+Reading "font_61".
+Reading "font_53".
+Reading "caravel_motto".
+Reading "alpha_2".
+Reading "alpha_5".
+Reading "alpha_0".
+Reading "user_id_textblock".
+Reading "font_62".
+Reading "font_66".
+Reading "font_29".
+Reading "font_20".
+Reading "font_28".
+Reading "font_33".
+Reading "font_56".
+Reading "font_76".
+Reading "font_72".
+Reading "font_2D".
+Reading "font_4B".
+Reading "font_44".
+Reading "font_50".
+Reading "font_70".
+Reading "font_6F".
+Reading "font_74".
+Reading "font_57".
+Reading "font_6B".
+Reading "font_79".
+Reading "font_47".
+Reading "font_31".
+Reading "font_32".
+Reading "font_30".
+Reading "font_6D".
+Reading "font_4E".
+Reading "copyright_block".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__dfrtn_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "caravel_clocking".
+Reading "sky130_fd_sc_hd__ebufn_8".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__nand4bb_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__clkinvlp_2".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__ebufn_2".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "housekeeping".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__einvn_4".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "digital_pll".
+Reading "sky130_fd_sc_hd__dfbbn_1".
+Reading "sky130_fd_sc_hd__ebufn_1".
+Reading "gpio_logic_high".
+Reading "gpio_control_block".
+Reading "gpio_defaults_block_1803".
+Reading "OE_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "OE_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "OE_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "OE_sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "OE_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "OE_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "OE_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "OE_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "OE_sky130_fd_sc_hvl__schmittbuf_1".
+Reading "OE_sky130_fd_sc_hvl__buf_8".
+Reading "OE_sky130_fd_sc_hvl__fill_4".
+Reading "OE_sky130_fd_sc_hvl__inv_8".
+Reading "OE_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "OE_sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "OE_sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "simple_por".
+Reading "CD_sky130_fd_sc_hd__decap_3".
+Reading "CD_sky130_fd_sc_hd__conb_1".
+Reading "CD_sky130_fd_sc_hd__fill_1".
+Reading "CD_sky130_fd_sc_hd__decap_8".
+Reading "CD_sky130_fd_sc_hd__fill_2".
+Reading "CD_sky130_fd_sc_hd__decap_6".
+Reading "CD_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "CD_sky130_fd_sc_hd__decap_4".
+Reading "CD_sky130_fd_sc_hd__decap_12".
+Reading "user_id_programming".
+Reading "LO_sky130_fd_sc_hd__decap_3".
+Reading "LO_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "LO_sky130_fd_sc_hd__decap_12".
+Reading "LO_sky130_fd_sc_hd__decap_6".
+Reading "LO_sky130_fd_sc_hd__ebufn_2".
+Reading "LO_sky130_fd_sc_hd__decap_4".
+Reading "LO_sky130_fd_sc_hd__diode_2".
+Reading "LO_sky130_fd_sc_hd__fill_1".
+Reading "LO_sky130_fd_sc_hd__fill_2".
+Reading "LO_sky130_fd_sc_hd__dfxtp_1".
+Reading "LO_sky130_fd_sc_hd__decap_8".
+Reading "LO_sky130_fd_sc_hd__mux2_1".
+Reading "LO_sky130_fd_sc_hd__mux4_1".
+Reading "LO_sky130_fd_sc_hd__inv_1".
+Reading "LO_sky130_fd_sc_hd__and2_1".
+Reading "LO_sky130_fd_sc_hd__dlclkp_1".
+Reading "LO_sky130_fd_sc_hd__conb_1".
+Reading "LO_sky130_fd_sc_hd__clkbuf_2".
+Reading "LO_sky130_fd_sc_hd__clkbuf_16".
+Reading "LO_sky130_fd_sc_hd__and3b_4".
+Reading "LO_sky130_fd_sc_hd__and2_2".
+Reading "LO_sky130_fd_sc_hd__nor3b_4".
+Reading "LO_sky130_fd_sc_hd__clkbuf_1".
+Reading "LO_sky130_fd_sc_hd__and4bb_2".
+Reading "LO_sky130_fd_sc_hd__nor4b_2".
+Reading "LO_sky130_fd_sc_hd__and3_4".
+Reading "LO_sky130_fd_sc_hd__and4b_2".
+Reading "LO_sky130_fd_sc_hd__and4_2".
+Reading "LO_sky130_fd_sc_hd__and2b_2".
+Reading "LO_sky130_fd_sc_hd__clkbuf_4".
+Reading "LO_DFFRAM".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+Reading "LO_sky130_fd_sc_hd__buf_2".
+Reading "LO_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "LO_sky130_fd_sc_hd__buf_8".
+Reading "LO_sky130_fd_sc_hd__buf_6".
+Reading "LO_sky130_fd_sc_hd__clkbuf_8".
+Reading "LO_sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "LO_sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "LO_sky130_fd_sc_hd__dfxtp_2".
+Reading "LO_sky130_fd_sc_hd__buf_4".
+Reading "LO_sky130_fd_sc_hd__a221o_1".
+Reading "LO_sky130_fd_sc_hd__a22o_1".
+Reading "LO_sky130_fd_sc_hd__dfxtp_4".
+Reading "LO_sky130_fd_sc_hd__nand3_4".
+Reading "LO_sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "LO_sky130_fd_sc_hd__a2111o_1".
+Reading "LO_sky130_fd_sc_hd__and4_1".
+Reading "LO_sky130_fd_sc_hd__a2111o_2".
+Reading "LO_sky130_fd_sc_hd__o211a_1".
+Reading "LO_sky130_fd_sc_hd__and3_1".
+Reading "LO_sky130_fd_sc_hd__inv_2".
+Reading "LO_sky130_fd_sc_hd__clkinv_2".
+Reading "LO_sky130_fd_sc_hd__a2111oi_1".
+Reading "LO_sky130_fd_sc_hd__buf_12".
+Reading "LO_sky130_fd_sc_hd__and2b_1".
+Reading "LO_sky130_fd_sc_hd__nand3b_1".
+Reading "LO_sky130_fd_sc_hd__a221o_2".
+Reading "LO_sky130_fd_sc_hd__nor3b_1".
+Reading "LO_sky130_fd_sc_hd__nor3_4".
+Reading "LO_sky130_fd_sc_hd__inv_6".
+Reading "LO_sky130_fd_sc_hd__and3b_1".
+Reading "LO_sky130_fd_sc_hd__nor3b_2".
+Reading "LO_sky130_fd_sc_hd__or2_1".
+Reading "LO_sky130_fd_sc_hd__a211oi_1".
+Reading "LO_sky130_fd_sc_hd__nand2_1".
+Reading "LO_sky130_fd_sc_hd__nand3b_4".
+Reading "LO_sky130_fd_sc_hd__inv_8".
+Reading "LO_sky130_fd_sc_hd__nand3_1".
+Reading "LO_sky130_fd_sc_hd__inv_12".
+Reading "LO_sky130_fd_sc_hd__o2111a_1".
+Reading "LO_sky130_fd_sc_hd__a21oi_1".
+Reading "LO_sky130_fd_sc_hd__o21ai_4".
+Reading "LO_sky130_fd_sc_hd__mux2_2".
+Reading "LO_sky130_fd_sc_hd__inv_4".
+Reading "LO_sky130_fd_sc_hd__a21bo_1".
+Reading "LO_sky130_fd_sc_hd__o21a_1".
+Reading "LO_sky130_fd_sc_hd__a211o_2".
+Reading "LO_sky130_fd_sc_hd__or2b_1".
+Reading "LO_sky130_fd_sc_hd__a21oi_4".
+Reading "LO_sky130_fd_sc_hd__o21ai_1".
+Reading "LO_sky130_fd_sc_hd__a21boi_1".
+Reading "LO_sky130_fd_sc_hd__nor3_1".
+Reading "LO_sky130_fd_sc_hd__nor2_2".
+Reading "LO_sky130_fd_sc_hd__a31oi_1".
+Reading "LO_sky130_fd_sc_hd__a21o_1".
+Reading "LO_sky130_fd_sc_hd__o21bai_1".
+Reading "LO_sky130_fd_sc_hd__o211ai_1".
+Reading "LO_sky130_fd_sc_hd__o31ai_1".
+Reading "LO_sky130_fd_sc_hd__nor2_1".
+Reading "LO_sky130_fd_sc_hd__xor2_4".
+Reading "LO_sky130_fd_sc_hd__nand3_2".
+Reading "LO_sky130_fd_sc_hd__o21ba_1".
+Reading "LO_sky130_fd_sc_hd__a41oi_1".
+Reading "LO_sky130_fd_sc_hd__nor3_2".
+Reading "LO_sky130_fd_sc_hd__o41ai_1".
+Reading "LO_sky130_fd_sc_hd__o21bai_2".
+Reading "LO_sky130_fd_sc_hd__xnor2_4".
+Reading "LO_sky130_fd_sc_hd__a41oi_4".
+Reading "LO_sky130_fd_sc_hd__xnor2_2".
+Reading "LO_sky130_fd_sc_hd__or3b_1".
+Reading "LO_sky130_fd_sc_hd__nand2_4".
+Reading "LO_sky130_fd_sc_hd__xnor2_1".
+Reading "LO_sky130_fd_sc_hd__nand2_8".
+Reading "LO_sky130_fd_sc_hd__xor2_1".
+Reading "LO_sky130_fd_sc_hd__nor2b_1".
+Reading "LO_sky130_fd_sc_hd__o21a_2".
+Reading "LO_sky130_fd_sc_hd__o211a_2".
+Reading "LO_sky130_fd_sc_hd__o31a_1".
+Reading "LO_sky130_fd_sc_hd__mux2_4".
+Reading "LO_sky130_fd_sc_hd__mux2_8".
+Reading "LO_sky130_fd_sc_hd__a211o_1".
+Reading "LO_sky130_fd_sc_hd__a311o_1".
+Reading "LO_sky130_fd_sc_hd__a22oi_4".
+Reading "LO_sky130_fd_sc_hd__o2111a_4".
+Reading "LO_sky130_fd_sc_hd__o22a_1".
+Reading "LO_sky130_fd_sc_hd__a31o_1".
+Reading "LO_sky130_fd_sc_hd__nor2b_2".
+Reading "LO_sky130_fd_sc_hd__a22oi_2".
+Reading "LO_sky130_fd_sc_hd__o21bai_4".
+Reading "LO_sky130_fd_sc_hd__o41a_2".
+Reading "LO_sky130_fd_sc_hd__nand2_2".
+Reading "LO_sky130_fd_sc_hd__nor2_8".
+Reading "LO_sky130_fd_sc_hd__a32oi_2".
+Reading "LO_sky130_fd_sc_hd__a221oi_4".
+Reading "LO_sky130_fd_sc_hd__nor2b_4".
+Reading "LO_sky130_fd_sc_hd__or4_1".
+Reading "LO_sky130_fd_sc_hd__a211oi_2".
+Reading "LO_sky130_fd_sc_hd__clkinv_4".
+Reading "LO_sky130_fd_sc_hd__a2bb2oi_1".
+Reading "LO_sky130_fd_sc_hd__a31oi_4".
+Reading "LO_sky130_fd_sc_hd__a21oi_2".
+Reading "LO_sky130_fd_sc_hd__o311ai_1".
+Reading "LO_sky130_fd_sc_hd__a41oi_2".
+Reading "LO_sky130_fd_sc_hd__or3b_4".
+Reading "LO_sky130_fd_sc_hd__clkinv_16".
+Reading "LO_sky130_fd_sc_hd__o211ai_4".
+Reading "LO_sky130_fd_sc_hd__nor2_4".
+Reading "LO_sky130_fd_sc_hd__o21ba_2".
+Reading "LO_sky130_fd_sc_hd__o2111ai_2".
+Reading "LO_sky130_fd_sc_hd__o2111ai_1".
+Reading "LO_sky130_fd_sc_hd__a32o_1".
+Reading "LO_sky130_fd_sc_hd__a311oi_1".
+Reading "LO_sky130_fd_sc_hd__xor2_2".
+Reading "LO_sky130_fd_sc_hd__a2111o_4".
+Reading "LO_sky130_fd_sc_hd__or4_4".
+Reading "LO_sky130_fd_sc_hd__o21ai_2".
+Reading "LO_sky130_fd_sc_hd__a211oi_4".
+Reading "LO_sky130_fd_sc_hd__o311ai_4".
+Reading "LO_sky130_fd_sc_hd__nand3b_2".
+Reading "LO_sky130_fd_sc_hd__a2111oi_4".
+Reading "LO_sky130_fd_sc_hd__or2b_4".
+Reading "LO_sky130_fd_sc_hd__o21a_4".
+Reading "LO_sky130_fd_sc_hd__and4b_4".
+Reading "LO_sky130_fd_sc_hd__o2111ai_4".
+Reading "LO_sky130_fd_sc_hd__or2_2".
+Reading "LO_sky130_fd_sc_hd__a21boi_2".
+Reading "LO_sky130_fd_sc_hd__mux4_2".
+Reading "LO_sky130_fd_sc_hd__a221oi_2".
+Reading "LO_sky130_fd_sc_hd__o22ai_1".
+Reading "LO_sky130_fd_sc_hd__o2bb2ai_1".
+Reading "LO_sky130_fd_sc_hd__and4_4".
+Reading "LO_sky130_fd_sc_hd__a32oi_1".
+Reading "LO_sky130_fd_sc_hd__clkinv_8".
+Reading "LO_sky130_fd_sc_hd__o32ai_1".
+Reading "LO_sky130_fd_sc_hd__a41o_1".
+Reading "LO_sky130_fd_sc_hd__or4_2".
+Reading "LO_sky130_fd_sc_hd__o221ai_1".
+Reading "LO_sky130_fd_sc_hd__o32a_1".
+Reading "LO_sky130_fd_sc_hd__a22o_2".
+Reading "LO_sky130_fd_sc_hd__o41a_1".
+Reading "LO_sky130_fd_sc_hd__a22oi_1".
+Reading "LO_sky130_fd_sc_hd__and3_2".
+Reading "LO_sky130_fd_sc_hd__o221a_2".
+Reading "LO_sky130_fd_sc_hd__o221a_1".
+Reading "LO_sky130_fd_sc_hd__and2_4".
+Reading "LO_sky130_fd_sc_hd__or3_1".
+Reading "LO_sky130_fd_sc_hd__o22ai_2".
+Reading "LO_sky130_fd_sc_hd__a221oi_1".
+Reading "LO_sky130_fd_sc_hd__a221o_4".
+Reading "LO_sky130_fd_sc_hd__o311ai_2".
+Reading "LO_sky130_fd_sc_hd__o31ai_2".
+Reading "LO_sky130_fd_sc_hd__a311oi_2".
+Reading "LO_sky130_fd_sc_hd__a31oi_2".
+Reading "LO_sky130_fd_sc_hd__o311a_2".
+Reading "LO_sky130_fd_sc_hd__o211ai_2".
+Reading "LO_sky130_fd_sc_hd__o41ai_4".
+Reading "LO_sky130_fd_sc_hd__o31a_4".
+Reading "LO_sky130_fd_sc_hd__a311oi_4".
+Reading "LO_sky130_fd_sc_hd__and2b_4".
+Reading "LO_sky130_fd_sc_hd__o2bb2ai_2".
+Reading "LO_sky130_fd_sc_hd__o2bb2ai_4".
+Reading "LO_sky130_fd_sc_hd__o22a_2".
+Reading "LO_sky130_fd_sc_hd__and4b_1".
+Reading "LO_sky130_fd_sc_hd__nand2b_1".
+Reading "LO_sky130_fd_sc_hd__a21boi_4".
+Reading "LO_sky130_fd_sc_hd__o2111a_2".
+Reading "LO_sky130_fd_sc_hd__o31ai_4".
+Reading "LO_sky130_fd_sc_hd__a2bb2oi_2".
+Reading "LO_sky130_fd_sc_hd__a2bb2oi_4".
+Reading "LO_sky130_fd_sc_hd__or3_4".
+Reading "LO_sky130_fd_sc_hd__a22o_4".
+Reading "LO_sky130_fd_sc_hd__a32oi_4".
+Reading "LO_sky130_fd_sc_hd__o311a_1".
+Reading "LO_sky130_fd_sc_hd__a21o_2".
+Reading "LO_sky130_fd_sc_hd__or4b_1".
+Reading "LO_sky130_fd_sc_hd__a2111oi_2".
+Reading "LO_sky130_fd_sc_hd__a21o_4".
+Reading "LO_sky130_fd_sc_hd__a32o_4".
+Reading "LO_sky130_fd_sc_hd__and3b_2".
+Reading "LO_sky130_fd_sc_hd__o32ai_4".
+Reading "LO_sky130_fd_sc_hd__o221ai_2".
+Reading "LO_sky130_fd_sc_hd__a31o_2".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "LO_sky130_fd_bd_sram__openram_dff".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "LO_sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "LO_sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "LO_sky130_fd_bd_sram__openram_sense_amp".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "LO_sky130_fd_bd_sram__openram_write_driver".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "LO_sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "LO_sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "LO_sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "LO_sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "LO_sky130_fd_bd_sram__openram_dp_cell".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8".
+    5000 uses
+Reading "LO_sky130_fd_sc_hd__inv_16".
+Reading "LO_sky130_fd_sc_hd__o41ai_2".
+Reading "LO_sky130_fd_sc_hd__o211a_4".
+Reading "LO_mgmt_core".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+    105000 uses
+    110000 uses
+    115000 uses
+    120000 uses
+    125000 uses
+    130000 uses
+    135000 uses
+    140000 uses
+    145000 uses
+Reading "mgmt_core_wrapper".
+Reading "gpio_defaults_block_1800".
+Reading "sky130_fd_sc_hd__dfbbp_1".
+Reading "spare_logic_block".
+Reading "sky130_fd_sc_hd__einvp_4".
+Reading "sky130_fd_sc_hd__einvp_8".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hvl__conb_1".
+Reading "mgmt_protect_hv".
+Reading "mprj_logic_high".
+Reading "mprj2_logic_high".
+Reading "mgmt_protect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+Reading "gpio_defaults_block_0403".
+Reading "gpio_defaults_block".
+Reading "gpio_control_power_routing_right".
+Reading "gpio_control_power_routing_top".
+Reading "gpio_control_power_routing".
+Reading "caravel_power_routing".
+Reading "sky130_fd_io__corner_bus_overlay".
+Reading "sky130_ef_io__corner_pad".
+Reading "sky130_ef_io__com_bus_slice_20um".
+Reading "sky130_ef_io__com_bus_slice_10um".
+Reading "sky130_ef_io__com_bus_slice_5um".
+Reading "sky130_ef_io__com_bus_slice_1um".
+Reading "sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um".
+Reading "sky130_ef_io__hvc_vdda_overlay".
+Reading "sky130_fd_io__com_bus_slice".
+Reading "sky130_fd_io__com_bus_hookup".
+Reading "sky130_fd_io__overlay_vssa_hvc".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180851".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808664".
+Reading "sky130_fd_io__sio_clamp_pcap_4x5".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808680".
+Reading "sky130_fd_io__esd_rcclamp_nfetcap".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808336".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808666".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808665".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808678".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808679".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808677".
+Reading "sky130_fd_pr__via_pol1__example_5595914180839".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808667".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808660".
+Reading "sky130_fd_pr__dfl1__example_55959141808663".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808671".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808672".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808673".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808668".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808670".
+Reading "sky130_fd_pr__dfl1__example_55959141808662".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808661".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808675".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808676".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808674".
+Reading "sky130_fd_pr__via_l1m1__example_559591418084".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808669".
+Reading "sky130_fd_pr__gendlring__example_559591418081".
+Reading "sky130_fd_pr__genrivetdlring__example_559591418082".
+Reading "sky130_fd_pr__padplhp__example_559591418080".
+Reading "sky130_fd_io__pad_esd".
+Reading "sky130_fd_io__com_busses_esd".
+Reading "sky130_fd_io__top_ground_hvc_wpad".
+Reading "sky130_ef_io__vssa_hvc_clamped_pad".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808717".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808716".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808719".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808718".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808720".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180890".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808721".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808243".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808722".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808723".
+Reading "sky130_fd_io__xres_inv_hysv2".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180838".
+Reading "sky130_fd_io__tk_tie_r_out_esd".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808765".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808764".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808767".
+Reading "sky130_fd_io__res250_sub_small".
+Reading "sky130_fd_io__res250only_small".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808289".
+Reading "sky130_fd_pr__via_pol1__example_5595914180833".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808715".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180862".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180863".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808288".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180859".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180864".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808264".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180858".
+Reading "sky130_fd_io__com_res_weak_v2".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180819".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808555".
+Reading "sky130_fd_pr__via_pol1__example_55959141808147".
+Reading "sky130_fd_pr__tpl1__example_55959141808148".
+Reading "sky130_fd_pr__tpl1__example_55959141808149".
+Reading "sky130_fd_pr__tpl1__example_55959141808150".
+Reading "sky130_fd_pr__tpl1__example_55959141808151".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808152".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808153".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808154".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808155".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808156".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808157".
+Reading "sky130_fd_pr__dfl1__example_55959141808158".
+Reading "sky130_fd_io__signal_5_sym_hv_local_5term".
+Reading "sky130_fd_pr__via_pol1__example_55959141808274".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808400".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808128".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808372".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808326".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808290".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808127".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180897".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808551".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808552".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808350".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808260".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808402".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808724".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808259".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808261".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808553".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808725".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808554".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808726".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808727".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808728".
+Reading "sky130_fd_io__gpio_buf_localesdv2".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180848".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180849".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808766".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808370".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808369".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808137".
+Reading "sky130_fd_pr__dfl1sd__example_559591418086".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808371".
+Reading "sky130_fd_pr__via_pol1__example_559591418083".
+Reading "sky130_fd_io__hvsbt_inv_x1".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808385".
+Reading "sky130_fd_pr__dfl1sd__example_559591418088".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808615".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808316".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808616".
+Reading "sky130_fd_pr__via_pol1__example_55959141808612".
+Reading "sky130_fd_io__hvsbt_inv_x4".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808422".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808421".
+Reading "sky130_fd_io__hvsbt_inv_x2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808657".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808659".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808658".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808202".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180811".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180812".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418084".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418086".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808653".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808652".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418081".
+Reading "sky130_fd_io__gpio_pudrvr_strong_axres4v2".
+Reading "sky130_fd_pr__via_m2m3__example_55959141808714".
+Reading "sky130_fd_io__xres_p_em1c_cdns_55959141808753".
+Reading "sky130_fd_pr__dfl1__example_55959141808187".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808754".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808755".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808700".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808559".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808762".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808338".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808337".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808763".
+Reading "sky130_fd_pr__dfl1__example_55959141808729".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808730".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808731".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808732".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808733".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808734".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808735".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808736".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808737".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808738".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808739".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808740".
+Reading "sky130_fd_pr__via_pol1__example_55959141808273".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808741".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808742".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808743".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808744".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808324".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808745".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808746".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808747".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808748".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808749".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808270".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808750".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808751".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808752".
+Reading "sky130_fd_io__xres2v2_rcfilter_lpfv2".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180860".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180861".
+Reading "sky130_fd_io__com_res_weak_bentbigres".
+Reading "sky130_fd_io__com_res_weak".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180857".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808646".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808645".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808647".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808649".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808648".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808650".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808651".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808378".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_xres4v2".
+Reading "sky130_fd_io__top_gpio_pad".
+Reading "sky130_fd_io__com_busses".
+Reading "sky130_fd_io__tap_1".
+Reading "sky130_fd_io__inv_1".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808768".
+Reading "sky130_fd_pr__res_bent_nd__example_55959141808769".
+Reading "sky130_fd_pr__pfet_01v8__example_559591418085".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418087".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418089".
+Reading "sky130_fd_io__hvsbt_nand2".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180827".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808770".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808233".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808771".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808237".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180829".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808772".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808773".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808242".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808774".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808775".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808776".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180835".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808777".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808778".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808779".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808780".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808782".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808781".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808452".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808783".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808449".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808784".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808785".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808786".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808787".
+Reading "sky130_fd_io__xres4v2_in_buf".
+Reading "sky130_fd_io__top_xres4v2".
+Reading "sky130_fd_io__com_bus_slice_m4".
+Reading "sky130_fd_io__overlay_gpiov2_m4".
+Reading "sky130_fd_io__overlay_gpiov2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808558".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808251".
+Reading "sky130_fd_pr__dfm1sd2__example_55959141808561".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808560".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808563".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808562".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808564".
+Reading "sky130_fd_io__amux_switch_1v2b".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180868".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180869".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808565".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180875".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808566".
+Reading "sky130_fd_io__gpiov2_amx_pucsd_inv".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808567".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808122".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808123".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808477".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808568".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180884".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808569".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808100".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180815".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808570".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808571".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808441".
+Reading "sky130_fd_io__gpiov2_amx_inv4".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180823".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808572".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808573".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808106".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808574".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808510".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808575".
+Reading "sky130_fd_io__amx_inv1".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808576".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808504".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808577".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808578".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808579".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808581".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808418".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808580".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808140".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808496".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808497".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808278".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808462".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808582".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808583".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808498".
+Reading "sky130_fd_io__gpiov2_amux_drvr_ls".
+Reading "sky130_fd_io__gpiov2_amux_drvr".
+Reading "sky130_fd_io__xor2_1".
+Reading "sky130_fd_io__nand2_1".
+Reading "sky130_fd_io__nor2_1".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808419".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808420".
+Reading "sky130_fd_io__hvsbt_nor".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180894".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808584".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808455".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808445".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808447".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808248".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808200".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808457".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808450".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808451".
+Reading "sky130_fd_io__gpiov2_amux_nand5".
+Reading "sky130_fd_pr__dfm1sd__example_55959141808258".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808585".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808446".
+Reading "sky130_fd_io__gpiov2_amux_nand4".
+Reading "sky130_fd_io__gpiov2_amux_decoder".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808586".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808587".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808476".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808588".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808475".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808115".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808589".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv2".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808460".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808590".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180816".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808463".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808464".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808465".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808466".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808467".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808468".
+Reading "sky130_fd_io__gpiov2_amux_ctl_ls".
+Reading "sky130_fd_io__gpiov2_amux_ctl_inv_1".
+Reading "sky130_fd_io__gpiov2_amux_ls".
+Reading "sky130_fd_io__gpiov2_amux_ctl_logic".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808178".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808591".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808488".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808592".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808306".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808593".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808594".
+Reading "sky130_fd_io__res75only_small".
+Reading "sky130_fd_io__gpiov2_amux".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808608".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808517".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808533".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808230".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808529".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808518".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808609".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808604".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808610".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180811".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808549".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808190".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808548".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808611".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808191".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808189".
+Reading "sky130_fd_io__gpiov2_in_buf".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808481".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808537".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808600".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808528".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808550".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808607".
+Reading "sky130_fd_io__gpiov2_ipath_hvls".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808601".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180825".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808602".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808603".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808527".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808535".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808540".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808598".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808605".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808596".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808606".
+Reading "sky130_fd_io__gpiov2_vcchib_in_buf".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180812".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808597".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808599".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808546".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808547".
+Reading "sky130_fd_io__gpiov2_ipath_lvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808595".
+Reading "sky130_fd_io__gpiov2_inbuf_lvinv_x1".
+Reading "sky130_fd_io__gpiov2_ibuf_se".
+Reading "sky130_fd_io__gpiov2_buf_localesd".
+Reading "sky130_fd_io__hvsbt_nand2v2".
+Reading "sky130_fd_io__gpiov2_ictl_logic".
+Reading "sky130_fd_io__gpiov2_ipath".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808613".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808614".
+Reading "sky130_fd_io__hvsbt_inv_x8v2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808423".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808280".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808425".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808424".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808426".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808379".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808380".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808382".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808383".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808427".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808428".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808429".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808430".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808102".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808431".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808432".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808434".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808433".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808435".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808440".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180878".
+Reading "sky130_fd_pr__via_pol1__example_55959141808394".
+Reading "sky130_fd_pr__via_pol1__example_55959141808298".
+Reading "sky130_fd_io__com_ctl_ls".
+Reading "sky130_fd_io__hvsbt_inv_x8".
+Reading "sky130_fd_io__com_ctl_hldv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808617".
+Reading "sky130_fd_io__com_ctl_ls_en_1_v2".
+Reading "sky130_fd_io__com_ctl_ls_v2".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808439".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808438".
+Reading "sky130_fd_io__com_ctl_ls_1v2".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180813".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180822".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808618".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808619".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808620".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808621".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808622".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808623".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808116".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808624".
+Reading "sky130_fd_io__com_ctl_lsv2".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180880".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180879".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180882".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180881".
+Reading "sky130_fd_io__gpiov2_ctl_lsbank".
+Reading "sky130_fd_io__gpiov2_ctl".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808375".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808376".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808377".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808381".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808384".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808386".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808387".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808388".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808389".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808390".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808391".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808392".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808393".
+Reading "sky130_fd_pr__via_pol1__example_55959141808373".
+Reading "sky130_fd_pr__via_pol1__example_55959141808272".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808271".
+Reading "sky130_fd_pr__tpl1__example_55959141808374".
+Reading "sky130_fd_io__gpio_dat_ls_1v2".
+Reading "sky130_fd_io__gpio_dat_lsv2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808360".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808403".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808362".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808404".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808405".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808406".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808194".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808346".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808407".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808408".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808409".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808410".
+Reading "sky130_fd_pr__via_pol1__example_55959141808294".
+Reading "sky130_fd_pr__via_pol1__example_55959141808322".
+Reading "sky130_fd_pr__via_pol1__example_55959141808395".
+Reading "sky130_fd_pr__via_pol1__example_55959141808396".
+Reading "sky130_fd_pr__via_pol1__example_55959141808397".
+Reading "sky130_fd_pr__via_pol1__example_55959141808295".
+Reading "sky130_fd_pr__via_pol1__example_55959141808398".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808399".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808325".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808292".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808269".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808401".
+Reading "sky130_fd_io__com_cclat".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808368".
+Reading "sky130_fd_pr__tpl1__example_55959141808625".
+Reading "sky130_fd_io__com_opath_datoev2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808416".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808417".
+Reading "sky130_fd_io__hvsbt_xor".
+Reading "sky130_fd_io__hvsbt_xorv2".
+Reading "sky130_fd_io__com_ctl_ls_octl".
+Reading "sky130_fd_io__gpiov2_octl".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808354".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808626".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808627".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808628".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808629".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808630".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808631".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr2".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808633".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808632".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808634".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808635".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808636".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808637".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808638".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr3".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808327".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808328".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808329".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808330".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808304".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808331".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808134".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808332".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808333".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808334".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808343".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808344".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808345".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808347".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808348".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808639".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808640".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808641".
+Reading "sky130_fd_pr__via_pol1__example_55959141808320".
+Reading "sky130_fd_pr__via_pol1__example_55959141808321".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808323".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808291".
+Reading "sky130_fd_io__com_pdpredrvr_pbiasv2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180888".
+Reading "sky130_fd_io__gpiov2_octl_mux".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808642".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808141".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808184".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808643".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808183".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808139".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808143".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808364".
+Reading "sky130_fd_io__com_pdpredrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808363".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808314".
+Reading "sky130_fd_pr__via_pol1__example_5595914180854".
+Reading "sky130_fd_io__com_pupredrvr_strong_slowv2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808644".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808281".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808282".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808287".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808283".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808284".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808285".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808286".
+Reading "sky130_fd_pr__via_pol1__example_55959141808275".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808276".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808301".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808302".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808303".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808305".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808307".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808308".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808309".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808310".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808311".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808312".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808313".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808315".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808317".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808318".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808319".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808293".
+Reading "sky130_fd_pr__via_pol1__example_55959141808296".
+Reading "sky130_fd_pr__via_pol1__example_55959141808297".
+Reading "sky130_fd_pr__tpl1__example_55959141808299".
+Reading "sky130_fd_pr__tpl1__example_55959141808300".
+Reading "sky130_fd_io__feascom_pupredrvr_nbiasv2".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808144".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_5595914180899".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808142".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808101".
+Reading "sky130_fd_io__gpio_pupredrvr_strongv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808365".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808366".
+Reading "sky130_fd_io__com_pdpredrvr_weakv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808361".
+Reading "sky130_fd_io__feas_com_pupredrvr_weak".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808266".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808267".
+Reading "sky130_fd_io__gpiov2_obpredrvr".
+Reading "sky130_fd_io__gpiov2_octl_dat".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418082".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418083".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpiov2_pddrvr_strong".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808655".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808654".
+Reading "sky130_fd_io__com_pudrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808656".
+Reading "sky130_fd_io__com_pudrvr_weakv2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180850".
+Reading "sky130_fd_io__gpio_pddrvr_weakv2".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418085".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpio_pudrvr_strongv2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_slowv2".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180852".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180853".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180855".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180856".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180832".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418080".
+Reading "sky130_fd_io__gpio_odrvr_subv2".
+Reading "sky130_fd_io__gpio_odrvrv2".
+Reading "sky130_fd_io__gpio_opathv2".
+Reading "sky130_fd_io__top_gpiov2".
+Reading "sky130_ef_io__gpiov2_pad".
+Reading "sky130_ef_io__gpiov2_pad_wrapped".
+Reading "sky130_ef_io__lvc_vccdx_overlay".
+Reading "sky130_fd_io__overlay_vssd_lvc".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808683".
+Reading "sky130_fd_io__gnd2gnd_strap".
+Reading "sky130_fd_io__gnd2gnd_tap".
+Reading "sky130_fd_io__gnd2gnd_diff".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808684".
+Reading "sky130_fd_pr__tpl1__example_55959141808685".
+Reading "sky130_fd_pr__tpl1__example_55959141808686".
+Reading "sky130_fd_io__gnd2gnd_sub_dnwl".
+Reading "sky130_fd_io__gnd2gnd_120x2_lv_isosub".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808687".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808691".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808690".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808702".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808705".
+Reading "sky130_fd_pr__dfl1__example_55959141808682".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808694".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808693".
+Reading "sky130_fd_pr__dfl1__example_55959141808681".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808688".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808696".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808697".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808698".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808699".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808695".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808704".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808703".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808701".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808692".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808689".
+Reading "sky130_fd_io__top_ground_lvc_wpad".
+Reading "sky130_ef_io__vssd_lvc_clamped_pad".
+Reading "sky130_ef_io__hvc_vssio_overlay".
+Reading "sky130_fd_io__overlay_vssio_hvc".
+Reading "sky130_ef_io__vssio_hvc_clamped_pad".
+Reading "sky130_fd_io__overlay_vdda_hvc".
+Reading "sky130_fd_io__hvc_clampv2".
+Reading "sky130_fd_io__top_power_hvc_wpadv2".
+Reading "sky130_ef_io__vdda_hvc_clamped_pad".
+Reading "sky130_fd_io__overlay_vccd_lvc".
+Reading "sky130_fd_io__top_power_lvc_wpad".
+Reading "sky130_ef_io__vccd_lvc_clamped_pad".
+Reading "sky130_ef_io__disconnect_vdda_slice_5um".
+Reading "sky130_ef_io__hvc_vddio_overlay".
+Reading "sky130_fd_io__overlay_vddio_hvc".
+Reading "sky130_ef_io__vddio_hvc_clamped_pad".
+Reading "sky130_ef_io__lvc_vccdy_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped3_pad".
+Reading "sky130_ef_io__vccd_lvc_clamped3_pad".
+Reading "chip_io".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_11$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_12$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_360_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w1_120_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_15$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_29$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_28$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m2_w0_740_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m2_w1_260_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_13$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_14$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_16$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w7_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w7_000_sli_dli_da_p$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_nand2_dec$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_dec$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_nand3_dec$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_740_sactive_dli$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_740_sli_dactive$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w1_120_sli_dli$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m22_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m22_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m7_w1_680_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m7_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m18_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m18_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m3_w1_680_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m3_w1_680_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_dec_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_20$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_and2_dec$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_17$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_and3_dec$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w2_880_sli_dli$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pnand2$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_23$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_22$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_21$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_19$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w0_550_sli_dli$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_7$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_15$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m40_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m40_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_3$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m12_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m12_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m4_w1_260_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m4_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_16$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_740_sactive_dactive$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m24_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m24_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m8_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m8_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m3_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m3_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m39_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m39_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m13_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m13_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m5_w1_680_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m5_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m2_w1_260_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m2_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_fd_bd_sram__openram_dff$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_2$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_1$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_wordline_driver$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_hierarchical_predecode3x8$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_hierarchical_predecode2x4$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_column_mux_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_precharge_1$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_27$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_26$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_25$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_24$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_column_mux$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pand2$1".
+Reading "KP_sky130_fd_bd_sram__openram_write_driver$1".
+Reading "KP_sky130_fd_bd_sram__openram_sense_amp$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_precharge_0$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_cell_cap_row$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_cell_cap_col$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_cell_dummy$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_cell_replica$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_cell$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_3$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_10$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pnand2_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_dff_buf_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_18$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_17$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_19$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_4$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pnand3$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_14$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_13$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_12$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_11$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_20$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_9$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_8$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_7$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_6$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_and2_dec_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_wordline_driver_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_hierarchical_decoder$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_column_mux_array_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_precharge_array_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_column_mux_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_write_mask_and_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_write_driver_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_sense_amp_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_precharge_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_9$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_8$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_row_cap_array_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_row_cap_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_col_cap_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_col_cap_array_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_dummy_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_replica_column_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_replica_column$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_bitcell_array$1".
+    5000 uses
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_dff_buf_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pand3$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_1$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_33$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pnand2_1$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pand2_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_dff_buf_array_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_5$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_delay_chain$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pand3_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_2$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_6$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_34$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinvbuf$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_port_address_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_port_address$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_port_data_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_port_data$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_replica_bitcell_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_wmask_dff$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_cr_3$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_row_addr_dff$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_control_logic_rw$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_col_addr_dff$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_cr_5$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_40$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_39$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_control_logic_r$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_cr_4$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_data_dff$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_bank$1".
+Reading "KP_sky130_fd_sc_hd__decap_6$1".
+Reading "KP_sky130_fd_sc_hd__fill_2$1".
+Reading "KP_sky130_fd_sc_hd__fill_4$1".
+Reading "KP_sky130_fd_sc_hd__decap_6$2".
+Reading "KP_sky130_fd_sc_hd__fill_4$2".
+Reading "KP_sky130_fd_sc_hd__fill_2$2".
+Reading "KP_sky130_fd_sc_hd__decap_6_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__nand2_2$1".
+Reading "KP_sky130_fd_sc_hd__o21ai_2$1".
+Reading "KP_sky130_fd_sc_hd__nor2b_2$1".
+Reading "KP_sky130_fd_sc_hd__or2_2$3".
+Reading "KP_sky130_fd_sc_hd__dlxtn_1$1".
+Reading "KP_sky130_fd_sc_hd__nor2_2$1".
+Reading "KP_sky130_fd_sc_hd__and2_2$1".
+Reading "KP_sky130_fd_sc_hd__mux4_1$2".
+Reading "KP_M1M2_PR_M$3".
+Reading "KP_sky130_fd_sc_hd__decap_3$3".
+Reading "KP_sky130_fd_sc_hd__decap_4$3".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2$3".
+Reading "KP_BlockRAM_1KB_VIA3$1".
+Reading "KP_BlockRAM_1KB_VIA2$1".
+Reading "KP_BlockRAM_1KB_VIA1$1".
+Reading "KP_BlockRAM_1KB_VIA0$1".
+Reading "KP_M3M4_PR$3".
+Reading "KP_sky130_fd_sc_hd__diode_2$3".
+Reading "KP_M2M3_PR$3".
+Reading "KP_sky130_fd_sc_hd__conb_1$2".
+Reading "KP_sky130_fd_sc_hd__decap_6$3".
+Reading "KP_M1M2_PR$3".
+Reading "KP_L1M1_PR$3".
+Reading "KP_sky130_fd_sc_hd__fill_1$3".
+Reading "KP_sky130_fd_sc_hd__fill_4$3".
+Reading "KP_sky130_fd_sc_hd__fill_8$1".
+Reading "KP_sky130_fd_sc_hd__fill_2$3".
+Reading "KP_sky130_fd_sc_hd__decap_8$3".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1$3".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8$1".
+    5000 uses
+Reading "KP_sky130_fd_sc_hd__mux2_1$3".
+Reading "KP_sky130_fd_sc_hd__inv_2$3".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_N_term_RAM_IO_gds".
+Reading "KP_M3M4_PR_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1_N_term_RAM_IO_gds".
+Reading "KP_N_term_RAM_IO_VIA4".
+Reading "KP_N_term_RAM_IO_VIA5".
+Reading "KP_N_term_RAM_IO_VIA6".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_N_term_RAM_IO_gds".
+Reading "KP_M1M2_PR_M_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_RAM_IO_gds".
+Reading "KP_L1M1_PR_N_term_RAM_IO_gds".
+Reading "KP_M2M3_PR_N_term_RAM_IO_gds".
+Reading "KP_N_term_RAM_IO_VIA1".
+Reading "KP_N_term_RAM_IO_VIA2".
+Reading "KP_N_term_RAM_IO_VIA3".
+Reading "KP_N_term_RAM_IO_VIA0".
+Reading "KP_M1M2_PR_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_N_term_DSP_gds".
+Reading "KP_M1M2_PR_M_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__buf_2_N_term_DSP_gds".
+Reading "KP_N_term_DSP_VIA6".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_N_term_DSP_gds".
+Reading "KP_N_term_DSP_VIA4".
+Reading "KP_N_term_DSP_VIA5".
+Reading "KP_sky130_fd_sc_hd__fill_4_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_N_term_DSP_gds".
+Reading "KP_N_term_DSP_VIA0".
+Reading "KP_N_term_DSP_VIA1".
+Reading "KP_N_term_DSP_VIA2".
+Reading "KP_N_term_DSP_VIA3".
+Reading "KP_M2M3_PR_N_term_DSP_gds".
+Reading "KP_M1M2_PR_N_term_DSP_gds".
+Reading "KP_L1M1_PR_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_N_term_single2_gds".
+Reading "KP_M1M2_PR_M_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__buf_2_N_term_single2_gds".
+Reading "KP_N_term_single2_VIA6".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_N_term_single2_gds".
+Reading "KP_N_term_single2_VIA4".
+Reading "KP_N_term_single2_VIA5".
+Reading "KP_sky130_fd_sc_hd__fill_4_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_N_term_single2_gds".
+Reading "KP_N_term_single2_VIA0".
+Reading "KP_N_term_single2_VIA1".
+Reading "KP_N_term_single2_VIA2".
+Reading "KP_N_term_single2_VIA3".
+Reading "KP_M2M3_PR_N_term_single2_gds".
+Reading "KP_M1M2_PR_N_term_single2_gds".
+Reading "KP_L1M1_PR_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__buf_2_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_N_term_single_gds".
+Reading "KP_N_term_single_VIA4".
+Reading "KP_N_term_single_VIA5".
+Reading "KP_N_term_single_VIA6".
+Reading "KP_sky130_fd_sc_hd__decap_8_N_term_single_gds".
+Reading "KP_M1M2_PR_M_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_N_term_single_gds".
+Reading "KP_N_term_single_VIA1".
+Reading "KP_N_term_single_VIA2".
+Reading "KP_N_term_single_VIA3".
+Reading "KP_N_term_single_VIA0".
+Reading "KP_L1M1_PR_N_term_single_gds".
+Reading "KP_M1M2_PR_N_term_single_gds".
+Reading "KP_M2M3_PR_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s25_1$1".
+Reading "KP_sky130_fd_sc_hd__clkbuf_4$1".
+Reading "KP_M1M2_PR_R$1".
+Reading "KP_M2M3_PR_R$1".
+Reading "KP_sky130_ef_sc_hd__fill_12$1".
+Reading "KP_sky130_fd_sc_hd__clkinv_4$1".
+Reading "KP_RegFile_VIA6$1".
+Reading "KP_RegFile_VIA5$1".
+Reading "KP_RegFile_VIA4$1".
+Reading "KP_sky130_ef_sc_hd__fill_8$1".
+Reading "KP_sky130_fd_sc_hd__buf_2$1".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_1$1".
+Reading "KP_sky130_fd_sc_hd__buf_4$1".
+Reading "KP_sky130_ef_sc_hd__decap_12$1".
+Moving label "VGND" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12$1.
+Moving label "VNB" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12$1.
+Moving label "decap_12" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12$1.
+Reading "KP_sky130_fd_sc_hd__decap_8$1".
+Reading "KP_sky130_fd_sc_hd__mux2_4$1".
+Reading "KP_sky130_fd_sc_hd__or3_1$1".
+Reading "KP_sky130_fd_sc_hd__mux4_4$1".
+Reading "KP_sky130_fd_sc_hd__mux2_1$1".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1$1".
+Reading "KP_sky130_fd_sc_hd__buf_12$1".
+Reading "KP_sky130_fd_sc_hd__mux4_1$1".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1$1".
+Reading "KP_M1M2_PR_MR$1".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1$1".
+Reading "KP_sky130_fd_sc_hd__clkinv_8$1".
+Reading "KP_sky130_fd_sc_hd__mux4_2$1".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1$1".
+Reading "KP_sky130_fd_sc_hd__or2_2$1".
+Reading "KP_sky130_fd_sc_hd__clkinv_16$1".
+Reading "KP_sky130_fd_sc_hd__buf_1$1".
+Reading "KP_sky130_fd_sc_hd__decap_3$1".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2$1".
+Reading "KP_sky130_fd_sc_hd__diode_2$1".
+Reading "KP_sky130_fd_sc_hd__inv_2$1".
+Reading "KP_M1M2_PR_M$1".
+Reading "KP_sky130_fd_sc_hd__buf_8$1".
+Reading "KP_sky130_fd_sc_hd__a22o_1$1".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1$1".
+Reading "KP_RegFile_VIA3$1".
+Reading "KP_sky130_fd_sc_hd__decap_4$1".
+Reading "KP_sky130_fd_sc_hd__fill_1$1".
+Reading "KP_RegFile_VIA0$1".
+Reading "KP_RegFile_VIA1$1".
+Reading "KP_M3M4_PR$1".
+Reading "KP_RegFile_VIA2$1".
+Reading "KP_M1M2_PR$1".
+Reading "KP_M2M3_PR$1".
+Reading "KP_L1M1_PR$1".
+Reading "KP_sky130_fd_sc_hd__buf_1_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__decap_6_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_S_term_single2_gds".
+Reading "KP_S_term_single2_VIA4".
+Reading "KP_S_term_single2_VIA5".
+Reading "KP_S_term_single2_VIA6".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_S_term_single2_gds".
+Reading "KP_L1M1_PR_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_S_term_single2_gds".
+Reading "KP_M1M2_PR_M_S_term_single2_gds".
+Reading "KP_S_term_single2_VIA2".
+Reading "KP_S_term_single2_VIA3".
+Reading "KP_M2M3_PR_S_term_single2_gds".
+Reading "KP_S_term_single2_VIA0".
+Reading "KP_S_term_single2_VIA1".
+Reading "KP_M1M2_PR_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__buf_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1_W_IO_gds".
+Reading "KP_M1M2_PR_MR_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__conb_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__inv_2_W_IO_gds".
+Reading "KP_W_IO_VIA6".
+Reading "KP_W_IO_VIA4".
+Reading "KP_W_IO_VIA5".
+Reading "KP_sky130_fd_sc_hd__buf_8_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__mux4_2_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__mux2_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_6_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__diode_2_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_4_W_IO_gds".
+Reading "KP_M1M2_PR_M_W_IO_gds".
+Reading "KP_M3M4_PR_W_IO_gds".
+Reading "KP_L1M1_PR_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_W_IO_gds".
+Reading "KP_M1M2_PR_W_IO_gds".
+Reading "KP_W_IO_VIA0".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_W_IO_gds".
+Reading "KP_M2M3_PR_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_3_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_W_IO_gds".
+Reading "KP_W_IO_VIA1".
+Reading "KP_W_IO_VIA2".
+Reading "KP_W_IO_VIA3".
+Reading "KP_sky130_fd_sc_hd__clkinv_8_RAM_IO_gds".
+Reading "KP_M2M3_PR_R".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_RAM_IO_gds".
+Reading "KP_RAM_IO_VIA4".
+Reading "KP_RAM_IO_VIA5".
+Reading "KP_RAM_IO_VIA6".
+Reading "KP_sky130_fd_sc_hd__dfxtp_1".
+Reading "KP_sky130_fd_sc_hd__buf_4_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s25_1_RAM_IO_gds".
+Reading "KP_M1M2_PR_R_RAM_IO_gds".
+Reading "KP_L1M1_PR_R_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__conb_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__mux4_2_RAM_IO_gds".
+Reading "KP_M1M2_PR_MR_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__buf_2_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_16_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__diode_2_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_4_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_3_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_4_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__buf_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_RAM_IO_gds".
+Reading "KP_M1M2_PR_M_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__mux2_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_RAM_IO_gds".
+Reading "KP_RAM_IO_VIA1".
+Reading "KP_L1M1_PR_RAM_IO_gds".
+Reading "KP_RAM_IO_VIA2".
+Reading "KP_M2M3_PR_RAM_IO_gds".
+Reading "KP_RAM_IO_VIA3".
+Reading "KP_sky130_fd_sc_hd__fill_1_RAM_IO_gds".
+Reading "KP_RAM_IO_VIA0".
+Reading "KP_M1M2_PR_RAM_IO_gds".
+Reading "KP_M3M4_PR_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_4_S_term_RAM_IO_gds".
+Reading "KP_M1M2_PR_M_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_S_term_RAM_IO_gds".
+Reading "KP_S_term_RAM_IO_VIA4".
+Reading "KP_S_term_RAM_IO_VIA5".
+Reading "KP_S_term_RAM_IO_VIA6".
+Reading "KP_sky130_fd_sc_hd__decap_6_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__diode_2_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_S_term_RAM_IO_gds".
+Reading "KP_M2M3_PR_S_term_RAM_IO_gds".
+Reading "KP_L1M1_PR_S_term_RAM_IO_gds".
+Reading "KP_M1M2_PR_S_term_RAM_IO_gds".
+Reading "KP_S_term_RAM_IO_VIA0".
+Reading "KP_S_term_RAM_IO_VIA1".
+Reading "KP_S_term_RAM_IO_VIA2".
+Reading "KP_S_term_RAM_IO_VIA3".
+Reading "KP_sky130_fd_sc_hd__o31a_1$1".
+Reading "KP_sky130_fd_sc_hd__and2b_1$1".
+Reading "KP_sky130_fd_sc_hd__a2bb2oi_1$1".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1$2".
+Reading "KP_sky130_fd_sc_hd__clkbuf_4$2".
+Reading "KP_sky130_fd_sc_hd__xor2_1$1".
+Reading "KP_sky130_fd_sc_hd__o22ai_1$1".
+Reading "KP_sky130_fd_sc_hd__a31oi_1$1".
+Reading "KP_sky130_fd_sc_hd__a21oi_1$1".
+Reading "KP_sky130_fd_sc_hd__a22o_1$2".
+Reading "KP_sky130_fd_sc_hd__o221a_2$1".
+Reading "KP_sky130_fd_sc_hd__a22oi_1$1".
+Reading "KP_sky130_fd_sc_hd__mux2_2$1".
+Reading "KP_sky130_fd_sc_hd__o21ai_1$1".
+Reading "KP_sky130_fd_sc_hd__buf_12$2".
+Reading "KP_sky130_fd_sc_hd__a221o_1$1".
+Reading "KP_sky130_fd_sc_hd__o2bb2a_1$1".
+Reading "KP_sky130_fd_sc_hd__a32o_1$1".
+Reading "KP_sky130_fd_sc_hd__a31o_2$1".
+Reading "KP_sky130_fd_sc_hd__and4_1$1".
+Reading "KP_sky130_fd_sc_hd__or3_1$2".
+Reading "KP_sky130_fd_sc_hd__o32a_1$1".
+Reading "KP_DSP_VIA5$1".
+Reading "KP_DSP_VIA4$1".
+Reading "KP_DSP_VIA6$1".
+Reading "KP_sky130_fd_sc_hd__conb_1$1".
+Reading "KP_M1M2_PR_MR$2".
+Reading "KP_sky130_fd_sc_hd__o21a_1$1".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1$2".
+Reading "KP_sky130_fd_sc_hd__buf_2$2".
+Reading "KP_sky130_fd_sc_hd__decap_3$2".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_1$2".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s25_1$2".
+Reading "KP_sky130_fd_sc_hd__nand2_1$1".
+Reading "KP_sky130_fd_sc_hd__mux2_4$2".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2$2".
+Reading "KP_sky130_fd_sc_hd__a2bb2o_1$1".
+Reading "KP_sky130_fd_sc_hd__a21o_1$1".
+Reading "KP_sky130_fd_sc_hd__a21bo_2$1".
+Reading "KP_sky130_fd_sc_hd__and2_1$1".
+Reading "KP_sky130_fd_sc_hd__o21ba_2$1".
+Reading "KP_sky130_fd_sc_hd__o22a_1$1".
+Reading "KP_sky130_fd_sc_hd__or4_1$1".
+Reading "KP_sky130_fd_sc_hd__xnor2_1$1".
+Reading "KP_sky130_fd_sc_hd__or2b_1$1".
+Reading "KP_sky130_fd_sc_hd__nor2_1$1".
+Reading "KP_sky130_fd_sc_hd__or2_2$2".
+Reading "KP_sky130_fd_sc_hd__inv_2$2".
+Reading "KP_sky130_fd_sc_hd__mux2_1$2".
+Reading "KP_sky130_fd_sc_hd__buf_1$2".
+Reading "KP_L1M1_PR_R$1".
+Reading "KP_sky130_fd_sc_hd__clkinv_4$2".
+Reading "KP_sky130_fd_sc_hd__mux4_2$2".
+Reading "KP_M1M2_PR_R$2".
+Reading "KP_sky130_fd_sc_hd__decap_4$2".
+Reading "KP_sky130_fd_sc_hd__buf_8$2".
+Reading "KP_sky130_ef_sc_hd__fill_12$2".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1$2".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1$2".
+Reading "KP_M1M2_PR_M$2".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1$2".
+Reading "KP_sky130_ef_sc_hd__fill_8$2".
+Reading "KP_sky130_ef_sc_hd__decap_12$2".
+Moving label "VGND" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12$2.
+Moving label "VNB" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12$2.
+Moving label "decap_12" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12$2.
+Reading "KP_sky130_fd_sc_hd__diode_2$2".
+Reading "KP_sky130_fd_sc_hd__decap_8$2".
+Reading "KP_M3M4_PR$2".
+Reading "KP_DSP_VIA0$1".
+Reading "KP_DSP_VIA2$1".
+Reading "KP_DSP_VIA3$1".
+Reading "KP_M2M3_PR$2".
+Reading "KP_M1M2_PR$2".
+Reading "KP_DSP_VIA1$1".
+Reading "KP_L1M1_PR$2".
+Reading "KP_sky130_fd_sc_hd__fill_1$2".
+Reading "KP_sky130_fd_sc_hd__buf_1_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__decap_6_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_S_term_DSP_gds".
+Reading "KP_S_term_DSP_VIA4".
+Reading "KP_S_term_DSP_VIA5".
+Reading "KP_S_term_DSP_VIA6".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_S_term_DSP_gds".
+Reading "KP_L1M1_PR_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_S_term_DSP_gds".
+Reading "KP_M1M2_PR_M_S_term_DSP_gds".
+Reading "KP_S_term_DSP_VIA2".
+Reading "KP_S_term_DSP_VIA3".
+Reading "KP_M2M3_PR_S_term_DSP_gds".
+Reading "KP_S_term_DSP_VIA0".
+Reading "KP_S_term_DSP_VIA1".
+Reading "KP_M1M2_PR_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_16_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_LUT4AB_gds".
+Reading "KP_L1M1_PR_R_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__buf_2_LUT4AB_gds".
+Reading "KP_LUT4AB_VIA4".
+Reading "KP_LUT4AB_VIA5".
+Reading "KP_LUT4AB_VIA6".
+Reading "KP_sky130_fd_sc_hd__clkinv_8_LUT4AB_gds".
+Reading "KP_M1M2_PR_R_LUT4AB_gds".
+Reading "KP_M1M2_PR_MR_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__decap_4_LUT4AB_gds".
+Reading "KP_sky130_ef_sc_hd__fill_12_LUT4AB_gds".
+Reading "KP_sky130_ef_sc_hd__decap_12_LUT4AB_gds".
+Moving label "VGND" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12_LUT4AB_gds.
+Moving label "VNB" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12_LUT4AB_gds.
+Moving label "decap_12" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12_LUT4AB_gds.
+Reading "KP_sky130_fd_sc_hd__conb_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__mux2_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__mux2_4_LUT4AB_gds".
+Reading "KP_sky130_ef_sc_hd__fill_8_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__inv_2_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__nor2_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__mux4_2_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__decap_3_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__o22a_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__mux2_2_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_LUT4AB_gds".
+Reading "KP_M3M4_PR_LUT4AB_gds".
+Reading "KP_M1M2_PR_M_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_LUT4AB_gds".
+Reading "KP_M2M3_PR_LUT4AB_gds".
+Reading "KP_M1M2_PR_LUT4AB_gds".
+Reading "KP_LUT4AB_VIA1".
+Reading "KP_LUT4AB_VIA2".
+Reading "KP_LUT4AB_VIA0".
+Reading "KP_sky130_fd_sc_hd__diode_2_LUT4AB_gds".
+Reading "KP_L1M1_PR_LUT4AB_gds".
+Reading "KP_LUT4AB_VIA3".
+Reading "KP_sky130_fd_sc_hd__conb_1_S_term_single_gds".
+Reading "KP_M1M2_PR_M_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__buf_1_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__decap_6_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_S_term_single_gds".
+Reading "KP_S_term_single_VIA4".
+Reading "KP_S_term_single_VIA5".
+Reading "KP_S_term_single_VIA6".
+Reading "KP_S_term_single_VIA0".
+Reading "KP_sky130_fd_sc_hd__fill_4_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_S_term_single_gds".
+Reading "KP_M2M3_PR_S_term_single_gds".
+Reading "KP_M1M2_PR_S_term_single_gds".
+Reading "KP_S_term_single_VIA1".
+Reading "KP_S_term_single_VIA2".
+Reading "KP_S_term_single_VIA3".
+Reading "KP_L1M1_PR_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4".
+Reading "KP_sky130_fd_sc_hd__fill_2".
+Reading "KP_sky130_fd_sc_hd__decap_6".
+Reading "KP_BlockRAM_1KB".
+    5000 uses
+Reading "KP_N_term_RAM_IO".
+Reading "KP_eFPGA_top_VIA7".
+Reading "KP_eFPGA_top_VIA23".
+Reading "KP_eFPGA_top_VIA24".
+Reading "KP_eFPGA_top_VIA25".
+Reading "KP_eFPGA_top_VIA6".
+Reading "KP_eFPGA_top_VIA8".
+Reading "KP_eFPGA_top_VIA19".
+Reading "KP_N_term_DSP".
+Reading "KP_eFPGA_top_VIA11".
+Reading "KP_N_term_single2".
+Reading "KP_N_term_single".
+Reading "KP_eFPGA_top_VIA22".
+Reading "KP_eFPGA_top_VIA36".
+Reading "KP_eFPGA_top_VIA20".
+Reading "KP_eFPGA_top_VIA21".
+Reading "KP_sky130_fd_sc_hd__inv_8".
+Reading "KP_sky130_fd_sc_hd__buf_16".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s25_2".
+Reading "KP_RegFile".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+Reading "KP_S_term_single2".
+Reading "KP_sky130_fd_sc_hd__a211o_2".
+Reading "KP_sky130_fd_sc_hd__a221oi_1".
+Reading "KP_sky130_fd_sc_hd__o21ba_2".
+Reading "KP_sky130_fd_sc_hd__or2_4".
+Reading "KP_sky130_fd_sc_hd__or2b_1".
+Reading "KP_sky130_fd_sc_hd__nand4_1".
+Reading "KP_sky130_fd_sc_hd__a32o_1".
+Reading "KP_sky130_fd_sc_hd__o21bai_1".
+Reading "KP_sky130_fd_sc_hd__a2bb2oi_1".
+Reading "KP_sky130_fd_sc_hd__a31oi_1".
+Reading "KP_sky130_fd_sc_hd__a2111o_1".
+Reading "KP_sky130_fd_sc_hd__and4_1".
+Reading "KP_sky130_fd_sc_hd__and3b_1".
+Reading "KP_sky130_fd_sc_hd__a2bb2oi_2".
+Reading "KP_sky130_fd_sc_hd__o22ai_1".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1".
+Reading "KP_sky130_fd_sc_hd__nand2b_1".
+Reading "KP_sky130_fd_sc_hd__a21oi_1".
+Reading "KP_sky130_fd_sc_hd__and4b_1".
+Reading "KP_sky130_fd_sc_hd__and3_1".
+Reading "KP_sky130_fd_sc_hd__o2111a_1".
+Reading "KP_sky130_fd_sc_hd__or3b_2".
+Reading "KP_sky130_fd_sc_hd__a211oi_1".
+Reading "KP_sky130_fd_sc_hd__xnor2_1".
+Reading "KP_sky130_fd_sc_hd__o32a_1".
+Reading "KP_sky130_fd_sc_hd__a211o_1".
+Reading "KP_sky130_fd_sc_hd__o221ai_1".
+Reading "KP_sky130_fd_sc_hd__a31o_2".
+Reading "KP_sky130_fd_sc_hd__xor2_1".
+Reading "KP_sky130_fd_sc_hd__a221o_1".
+Reading "KP_sky130_fd_sc_hd__o211a_2".
+Reading "KP_sky130_fd_sc_hd__and2b_1".
+Reading "KP_sky130_fd_sc_hd__o311a_1".
+Reading "KP_sky130_fd_sc_hd__o31a_1".
+Reading "KP_sky130_fd_sc_hd__nor3_1".
+Reading "KP_sky130_fd_sc_hd__o211ai_1".
+Reading "KP_sky130_fd_sc_hd__and2_1".
+Reading "KP_sky130_fd_sc_hd__nand3b_1".
+Reading "KP_sky130_fd_sc_hd__or4b_2".
+Reading "KP_sky130_fd_sc_hd__nand2_1".
+Reading "KP_sky130_fd_sc_hd__o221a_2".
+Reading "KP_sky130_fd_sc_hd__mux2_2".
+Reading "KP_sky130_fd_sc_hd__nand4b_1".
+Reading "KP_sky130_fd_sc_hd__nand2_2".
+Reading "KP_sky130_fd_sc_hd__or4bb_1".
+Reading "KP_sky130_fd_sc_hd__a2bb2o_1".
+Reading "KP_sky130_fd_sc_hd__o22a_1".
+Reading "KP_sky130_fd_sc_hd__o21a_1".
+Reading "KP_L1M1_PR_R".
+Reading "KP_W_IO".
+    5000 uses
+Reading "KP_sky130_fd_sc_hd__o21ai_1".
+Reading "KP_sky130_fd_sc_hd__a21o_1".
+Reading "KP_sky130_fd_sc_hd__or4_1".
+Reading "KP_sky130_fd_sc_hd__or3_1".
+Reading "KP_eFPGA_top_VIA35".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s15_1".
+Reading "KP_sky130_fd_sc_hd__a21bo_2".
+Reading "KP_sky130_fd_sc_hd__or2_2".
+Reading "KP_M1M2_PR_R".
+Reading "KP_sky130_fd_sc_hd__mux2_4".
+Reading "KP_sky130_fd_sc_hd__a22o_1".
+Reading "KP_M1M2_PR_MR".
+Reading "KP_sky130_fd_sc_hd__or4_4".
+Reading "KP_sky130_fd_sc_hd__or4_2".
+Reading "KP_eFPGA_top_VIA29".
+Reading "KP_eFPGA_top_VIA30".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s18_2".
+Reading "KP_sky130_fd_sc_hd__or3_4".
+Reading "KP_sky130_fd_sc_hd__or3_2".
+Reading "KP_RAM_IO".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "KP_S_term_RAM_IO".
+Reading "KP_sky130_fd_sc_hd__buf_12".
+Reading "KP_M1M2_PR_M".
+Reading "KP_sky130_fd_sc_hd__mux2_1".
+Reading "KP_DSP".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+Reading "KP_S_term_DSP".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1".
+Reading "KP_sky130_fd_sc_hd__inv_6".
+Reading "KP_eFPGA_top_VIA10".
+Reading "KP_sky130_fd_sc_hd__diode_2".
+Reading "KP_LUT4AB".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+Reading "KP_S_term_single".
+Reading "KP_sky130_fd_sc_hd__bufbuf_8".
+Reading "KP_sky130_fd_sc_hd__nor2_2".
+Reading "KP_sky130_fd_sc_hd__clkbuf_8".
+Reading "KP_sky130_fd_sc_hd__nor2_1".
+Reading "KP_sky130_fd_sc_hd__buf_4".
+Reading "KP_eFPGA_top_VIA9".
+Reading "KP_eFPGA_top_VIA34".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "KP_eFPGA_top_VIA37".
+Reading "KP_eFPGA_top_VIA38".
+Reading "KP_eFPGA_top_VIA39".
+Reading "KP_sky130_fd_sc_hd__inv_4".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_2".
+Reading "KP_sky130_fd_sc_hd__buf_2".
+Reading "KP_sky130_fd_sc_hd__clkbuf_4".
+Reading "KP_sky130_fd_sc_hd__bufbuf_16".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1".
+Reading "KP_sky130_fd_sc_hd__clkbuf_2".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "KP_sky130_fd_sc_hd__buf_6".
+Reading "KP_sky130_fd_sc_hd__mux2_8".
+Reading "KP_sky130_fd_sc_hd__inv_2".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2".
+Reading "KP_sky130_fd_sc_hd__clkinv_4".
+Reading "KP_eFPGA_top_VIA18".
+Reading "KP_eFPGA_top_VIA4".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "KP_eFPGA_top_VIA32".
+Reading "KP_eFPGA_top_VIA31".
+Reading "KP_eFPGA_top_VIA5".
+Reading "KP_eFPGA_top_VIA15".
+Reading "KP_eFPGA_top_VIA33".
+Reading "KP_eFPGA_top_VIA16".
+Reading "KP_eFPGA_top_VIA17".
+Reading "KP_eFPGA_top_VIA14".
+Reading "KP_eFPGA_top_VIA1".
+Reading "KP_eFPGA_top_VIA3".
+Reading "KP_eFPGA_top_VIA12".
+Reading "KP_eFPGA_top_VIA2".
+Reading "KP_eFPGA_top_VIA13".
+Reading "KP_sky130_fd_sc_hd__conb_1".
+Reading "KP_sky130_fd_sc_hd__buf_1".
+Reading "KP_sky130_fd_sc_hd__buf_8".
+Reading "KP_sky130_fd_sc_hd__clkinv_8".
+Reading "KP_sky130_fd_sc_hd__clkinv_16".
+Reading "KP_sky130_fd_sc_hd__decap_8".
+Reading "KP_eFPGA_top_VIA0".
+Reading "KP_sky130_fd_sc_hd__fill_1".
+Reading "KP_M2M3_PR".
+Reading "KP_sky130_ef_sc_hd__decap_12".
+Moving label "VGND" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12.
+Moving label "VNB" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12.
+Moving label "decap_12" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12.
+Reading "KP_M3M4_PR".
+Reading "KP_eFPGA_top_VIA27".
+Reading "KP_L1M1_PR".
+Reading "KP_eFPGA_top_VIA28".
+Reading "KP_sky130_ef_sc_hd__fill_12".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "KP_M1M2_PR".
+Reading "KP_sky130_ef_sc_hd__fill_8".
+Reading "KP_eFPGA_top_VIA26".
+Reading "KP_eFPGA_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+    105000 uses
+    110000 uses
+    115000 uses
+    120000 uses
+    125000 uses
+    130000 uses
+    135000 uses
+    140000 uses
+    145000 uses
+    150000 uses
+    155000 uses
+    160000 uses
+    165000 uses
+    170000 uses
+    175000 uses
+    180000 uses
+    185000 uses
+    190000 uses
+Reading "user_project_wrapper".
+Reading "caravel".
+Flattening layout of tile x=0 y=0. . . 
+Flattening layout of tile x=1 y=0. . . 
+Flattening layout of tile x=2 y=0. . . 
+Flattening layout of tile x=3 y=0. . . 
+Flattening layout of tile x=4 y=0. . . 
+Flattening layout of tile x=5 y=0. . . 
+Flattening layout of tile x=0 y=1. . . 
+Flattening layout of tile x=1 y=1. . . 
+Flattening layout of tile x=2 y=1. . . 
+Flattening layout of tile x=3 y=1. . . 
+Flattening layout of tile x=4 y=1. . . 
+Flattening layout of tile x=5 y=1. . . 
+Flattening layout of tile x=0 y=2. . . 
+Flattening layout of tile x=1 y=2. . . 
+Flattening layout of tile x=2 y=2. . . 
+Flattening layout of tile x=3 y=2. . . 
+Flattening layout of tile x=4 y=2. . . 
+Flattening layout of tile x=5 y=2. . . 
+Flattening layout of tile x=0 y=3. . . 
+Flattening layout of tile x=1 y=3. . . 
+Flattening layout of tile x=2 y=3. . . 
+Flattening layout of tile x=3 y=3. . . 
+Flattening layout of tile x=4 y=3. . . 
+Flattening layout of tile x=5 y=3. . . 
+Flattening layout of tile x=0 y=4. . . 
+Flattening layout of tile x=1 y=4. . . 
+Flattening layout of tile x=2 y=4. . . 
+Flattening layout of tile x=3 y=4. . . 
+Flattening layout of tile x=4 y=4. . . 
+Flattening layout of tile x=5 y=4. . . 
+Flattening layout of tile x=0 y=5. . . 
+Flattening layout of tile x=1 y=5. . . 
+Flattening layout of tile x=2 y=5. . . 
+Flattening layout of tile x=3 y=5. . . 
+Flattening layout of tile x=4 y=5. . . 
+Flattening layout of tile x=5 y=5. . . 
+Flattening layout of tile x=0 y=6. . . 
+Flattening layout of tile x=1 y=6. . . 
+Flattening layout of tile x=2 y=6. . . 
+Flattening layout of tile x=3 y=6. . . 
+Flattening layout of tile x=4 y=6. . . 
+Flattening layout of tile x=5 y=6. . . 
+Flattening layout of tile x=0 y=7. . . 
+Flattening layout of tile x=1 y=7. . . 
+Flattening layout of tile x=2 y=7. . . 
+Flattening layout of tile x=3 y=7. . . 
+Flattening layout of tile x=4 y=7. . . 
+Flattening layout of tile x=5 y=7. . . 
+Error message output from magic:
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228174798): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228174830): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228177422): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228177454): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228177486): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228177518): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228177550): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228177646): NODE elements not supported: skipping.
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_4_0: 10000 rects
+caravel_00020005_fill_pattern_4_0: 20000 rects
+caravel_00020005_fill_pattern_4_0: 30000 rects
+caravel_00020005_fill_pattern_4_0: 40000 rects
+caravel_00020005_fill_pattern_4_0: 50000 rects
+caravel_00020005_fill_pattern_4_0: 60000 rects
+caravel_00020005_fill_pattern_4_0: 70000 rects
+caravel_00020005_fill_pattern_4_0: 80000 rects
+caravel_00020005_fill_pattern_4_0: 90000 rects
+caravel_00020005_fill_pattern_4_0: 100000 rects
+caravel_00020005_fill_pattern_4_0: 110000 rects
+caravel_00020005_fill_pattern_4_0: 120000 rects
+caravel_00020005_fill_pattern_4_0: 130000 rects
+caravel_00020005_fill_pattern_4_0: 140000 rects
+caravel_00020005_fill_pattern_4_0: 150000 rects
+caravel_00020005_fill_pattern_4_0: 160000 rects
+caravel_00020005_fill_pattern_4_0: 170000 rects
+caravel_00020005_fill_pattern_4_0: 180000 rects
+caravel_00020005_fill_pattern_4_0: 190000 rects
+caravel_00020005_fill_pattern_4_0: 200000 rects
+caravel_00020005_fill_pattern_4_0: 210000 rects
+caravel_00020005_fill_pattern_4_0: 220000 rects
+caravel_00020005_fill_pattern_4_0: 230000 rects
+caravel_00020005_fill_pattern_4_0: 240000 rects
+caravel_00020005_fill_pattern_4_0: 250000 rects
+caravel_00020005_fill_pattern_4_0: 260000 rects
+caravel_00020005_fill_pattern_4_0: 270000 rects
+caravel_00020005_fill_pattern_4_0: 280000 rects
+caravel_00020005_fill_pattern_4_0: 290000 rects
+caravel_00020005_fill_pattern_4_0: 300000 rects
+caravel_00020005_fill_pattern_4_0: 310000 rects
+caravel_00020005_fill_pattern_4_0: 320000 rects
+caravel_00020005_fill_pattern_4_0: 330000 rects
+caravel_00020005_fill_pattern_4_0: 340000 rects
+caravel_00020005_fill_pattern_4_0: 350000 rects
+caravel_00020005_fill_pattern_4_0: 360000 rects
+caravel_00020005_fill_pattern_4_0: 370000 rects
+caravel_00020005_fill_pattern_4_0: 380000 rects
+caravel_00020005_fill_pattern_4_0: 390000 rects
+caravel_00020005_fill_pattern_4_0: 400000 rects
+caravel_00020005_fill_pattern_4_0: 410000 rects
+caravel_00020005_fill_pattern_4_0: 420000 rects
+caravel_00020005_fill_pattern_4_0: 430000 rects
+caravel_00020005_fill_pattern_4_0: 440000 rects
+caravel_00020005_fill_pattern_4_0: 450000 rects
+caravel_00020005_fill_pattern_4_0: 460000 rects
+caravel_00020005_fill_pattern_4_0: 470000 rects
+caravel_00020005_fill_pattern_4_0: 480000 rects
+caravel_00020005_fill_pattern_4_0: 490000 rects
+caravel_00020005_fill_pattern_4_0: 500000 rects
+caravel_00020005_fill_pattern_4_0: 510000 rects
+caravel_00020005_fill_pattern_4_0: 520000 rects
+caravel_00020005_fill_pattern_4_0: 530000 rects
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_4_1: 10000 rects
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+caravel_00020005_fill_pattern_4_1: 1550000 rects
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_0_6: 10000 rects
+caravel_00020005_fill_pattern_0_6: 20000 rects
+caravel_00020005_fill_pattern_0_6: 30000 rects
+caravel_00020005_fill_pattern_0_6: 40000 rects
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_4_3: 10000 rects
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+caravel_00020005_fill_pattern_1_5: 10470000 rects
+caravel_00020005_fill_pattern_1_5: 10480000 rects
+caravel_00020005_fill_pattern_1_5: 10490000 rects
+caravel_00020005_fill_pattern_1_5: 10500000 rects
+caravel_00020005_fill_pattern_1_5: 10510000 rects
+caravel_00020005_fill_pattern_1_5: 10520000 rects
+caravel_00020005_fill_pattern_1_5: 10530000 rects
+caravel_00020005_fill_pattern_1_5: 10540000 rects
+caravel_00020005_fill_pattern_1_5: 10550000 rects
+caravel_00020005_fill_pattern_1_5: 10560000 rects
+caravel_00020005_fill_pattern_1_5: 10570000 rects
+caravel_00020005_fill_pattern_1_5: 10580000 rects
+caravel_00020005_fill_pattern_1_5: 10590000 rects
+caravel_00020005_fill_pattern_1_5: 10600000 rects
+caravel_00020005_fill_pattern_1_5: 10610000 rects
+caravel_00020005_fill_pattern_1_5: 10620000 rects
+caravel_00020005_fill_pattern_1_5: 10630000 rects
+caravel_00020005_fill_pattern_1_5: 10640000 rects
+caravel_00020005_fill_pattern_1_5: 10650000 rects
+caravel_00020005_fill_pattern_1_5: 10660000 rects
+caravel_00020005_fill_pattern_1_5: 10670000 rects
+caravel_00020005_fill_pattern_1_5: 10680000 rects
+caravel_00020005_fill_pattern_1_5: 10690000 rects
+caravel_00020005_fill_pattern_1_5: 10700000 rects
+caravel_00020005_fill_pattern_1_5: 10710000 rects
+caravel_00020005_fill_pattern_1_5: 10720000 rects
+caravel_00020005_fill_pattern_1_5: 10730000 rects
+caravel_00020005_fill_pattern_1_5: 10740000 rects
+caravel_00020005_fill_pattern_1_5: 10750000 rects
+caravel_00020005_fill_pattern_1_5: 10760000 rects
+caravel_00020005_fill_pattern_1_5: 10770000 rects
+caravel_00020005_fill_pattern_1_5: 10780000 rects
+caravel_00020005_fill_pattern_1_5: 10790000 rects
+caravel_00020005_fill_pattern_1_5: 10800000 rects
+caravel_00020005_fill_pattern_1_5: 10810000 rects
+caravel_00020005_fill_pattern_1_5: 10820000 rects
+caravel_00020005_fill_pattern_1_5: 10830000 rects
+caravel_00020005_fill_pattern_1_5: 10840000 rects
+caravel_00020005_fill_pattern_1_5: 10850000 rects
+caravel_00020005_fill_pattern_1_5: 10860000 rects
+caravel_00020005_fill_pattern_1_5: 10870000 rects
+caravel_00020005_fill_pattern_1_5: 10880000 rects
+caravel_00020005_fill_pattern_1_5: 10890000 rects
+caravel_00020005_fill_pattern_1_5: 10900000 rects
+caravel_00020005_fill_pattern_1_5: 10910000 rects
+caravel_00020005_fill_pattern_1_5: 10920000 rects
+caravel_00020005_fill_pattern_1_5: 10930000 rects
+caravel_00020005_fill_pattern_1_5: 10940000 rects
+caravel_00020005_fill_pattern_1_5: 10950000 rects
+caravel_00020005_fill_pattern_1_5: 10960000 rects
+caravel_00020005_fill_pattern_1_5: 10970000 rects
+caravel_00020005_fill_pattern_1_5: 10980000 rects
+caravel_00020005_fill_pattern_1_5: 10990000 rects
+caravel_00020005_fill_pattern_1_5: 11000000 rects
+caravel_00020005_fill_pattern_1_5: 11010000 rects
+caravel_00020005_fill_pattern_1_5: 11020000 rects
+caravel_00020005_fill_pattern_1_5: 11030000 rects
+caravel_00020005_fill_pattern_1_5: 11040000 rects
+caravel_00020005_fill_pattern_1_5: 11050000 rects
+caravel_00020005_fill_pattern_1_5: 11060000 rects
+caravel_00020005_fill_pattern_1_5: 11070000 rects
+caravel_00020005_fill_pattern_1_5: 11080000 rects
+caravel_00020005_fill_pattern_1_5: 11090000 rects
+caravel_00020005_fill_pattern_1_5: 11100000 rects
+caravel_00020005_fill_pattern_1_5: 11110000 rects
+caravel_00020005_fill_pattern_1_5: 11120000 rects
+caravel_00020005_fill_pattern_1_5: 11130000 rects
+caravel_00020005_fill_pattern_1_5: 11140000 rects
+caravel_00020005_fill_pattern_1_5: 11150000 rects
+caravel_00020005_fill_pattern_1_5: 11160000 rects
+caravel_00020005_fill_pattern_1_5: 11170000 rects
+caravel_00020005_fill_pattern_1_5: 11180000 rects
+caravel_00020005_fill_pattern_1_5: 11190000 rects
+caravel_00020005_fill_pattern_1_5: 11200000 rects
+caravel_00020005_fill_pattern_1_5: 11210000 rects
+caravel_00020005_fill_pattern_1_5: 11220000 rects
+caravel_00020005_fill_pattern_1_5: 11230000 rects
+caravel_00020005_fill_pattern_1_5: 11240000 rects
+caravel_00020005_fill_pattern_1_5: 11250000 rects
+caravel_00020005_fill_pattern_1_5: 11260000 rects
+caravel_00020005_fill_pattern_1_5: 11270000 rects
+caravel_00020005_fill_pattern_1_5: 11280000 rects
+caravel_00020005_fill_pattern_1_5: 11290000 rects
+caravel_00020005_fill_pattern_1_5: 11300000 rects
+caravel_00020005_fill_pattern_1_5: 11310000 rects
+caravel_00020005_fill_pattern_1_5: 11320000 rects
+caravel_00020005_fill_pattern_1_5: 11330000 rects
+caravel_00020005_fill_pattern_1_5: 11340000 rects
+caravel_00020005_fill_pattern_1_5: 11350000 rects
+caravel_00020005_fill_pattern_1_5: 11360000 rects
+caravel_00020005_fill_pattern_1_5: 11370000 rects
+caravel_00020005_fill_pattern_1_5: 11380000 rects
+caravel_00020005_fill_pattern_1_5: 11390000 rects
+caravel_00020005_fill_pattern_1_5: 11400000 rects
+caravel_00020005_fill_pattern_1_5: 11410000 rects
+caravel_00020005_fill_pattern_1_5: 11420000 rects
+caravel_00020005_fill_pattern_1_5: 11430000 rects
+caravel_00020005_fill_pattern_1_5: 11440000 rects
+caravel_00020005_fill_pattern_1_5: 11450000 rects
+caravel_00020005_fill_pattern_1_5: 11460000 rects
+caravel_00020005_fill_pattern_1_5: 11470000 rects
+caravel_00020005_fill_pattern_1_5: 11480000 rects
+caravel_00020005_fill_pattern_1_5: 11490000 rects
+caravel_00020005_fill_pattern_1_5: 11500000 rects
+caravel_00020005_fill_pattern_1_5: 11510000 rects
+caravel_00020005_fill_pattern_1_5: 11520000 rects
+caravel_00020005_fill_pattern_1_5: 11530000 rects
+caravel_00020005_fill_pattern_1_5: 11540000 rects
+caravel_00020005_fill_pattern_1_5: 11550000 rects
+caravel_00020005_fill_pattern_1_5: 11560000 rects
+caravel_00020005_fill_pattern_1_5: 11570000 rects
+caravel_00020005_fill_pattern_1_5: 11580000 rects
+caravel_00020005_fill_pattern_1_5: 11590000 rects
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_final.tcl" from command line.
+CIF output style is now "wafflefill(tiled)"
+Writing final GDS
+   Generating output for cell caravel_00020005_fill_pattern_0_0
+Reading "caravel_00020005_fill_pattern_0_0".
+   Generating output for cell caravel_00020005_fill_pattern_1_0
+Reading "caravel_00020005_fill_pattern_1_0".
+   Generating output for cell caravel_00020005_fill_pattern_0_1
+Reading "caravel_00020005_fill_pattern_0_1".
+   Generating output for cell caravel_00020005_fill_pattern_1_1
+Reading "caravel_00020005_fill_pattern_1_1".
+   Generating output for cell caravel_00020005_fill_pattern_2_0
+Reading "caravel_00020005_fill_pattern_2_0".
+   Generating output for cell caravel_00020005_fill_pattern_2_1
+Reading "caravel_00020005_fill_pattern_2_1".
+   Generating output for cell caravel_00020005_fill_pattern_3_0
+Reading "caravel_00020005_fill_pattern_3_0".
+   Generating output for cell caravel_00020005_fill_pattern_3_1
+Reading "caravel_00020005_fill_pattern_3_1".
+   Generating output for cell caravel_00020005_fill_pattern_4_0
+Reading "caravel_00020005_fill_pattern_4_0".
+   Generating output for cell caravel_00020005_fill_pattern_4_1
+Reading "caravel_00020005_fill_pattern_4_1".
+   Generating output for cell caravel_00020005_fill_pattern_5_0
+Reading "caravel_00020005_fill_pattern_5_0".
+   Generating output for cell caravel_00020005_fill_pattern_5_1
+Reading "caravel_00020005_fill_pattern_5_1".
+   Generating output for cell caravel_00020005_fill_pattern_0_2
+Reading "caravel_00020005_fill_pattern_0_2".
+   Generating output for cell caravel_00020005_fill_pattern_1_2
+Reading "caravel_00020005_fill_pattern_1_2".
+   Generating output for cell caravel_00020005_fill_pattern_2_2
+Reading "caravel_00020005_fill_pattern_2_2".
+   Generating output for cell caravel_00020005_fill_pattern_3_2
+Reading "caravel_00020005_fill_pattern_3_2".
+   Generating output for cell caravel_00020005_fill_pattern_4_2
+Reading "caravel_00020005_fill_pattern_4_2".
+   Generating output for cell caravel_00020005_fill_pattern_5_2
+Reading "caravel_00020005_fill_pattern_5_2".
+   Generating output for cell caravel_00020005_fill_pattern_0_3
+Reading "caravel_00020005_fill_pattern_0_3".
+   Generating output for cell caravel_00020005_fill_pattern_1_3
+Reading "caravel_00020005_fill_pattern_1_3".
+   Generating output for cell caravel_00020005_fill_pattern_2_3
+Reading "caravel_00020005_fill_pattern_2_3".
+   Generating output for cell caravel_00020005_fill_pattern_3_3
+Reading "caravel_00020005_fill_pattern_3_3".
+   Generating output for cell caravel_00020005_fill_pattern_4_3
+Reading "caravel_00020005_fill_pattern_4_3".
+   Generating output for cell caravel_00020005_fill_pattern_5_3
+Reading "caravel_00020005_fill_pattern_5_3".
+   Generating output for cell caravel_00020005_fill_pattern_0_4
+Reading "caravel_00020005_fill_pattern_0_4".
+   Generating output for cell caravel_00020005_fill_pattern_1_4
+   Generating output for cell caravel_00020005_fill_pattern_2_4
+Reading "caravel_00020005_fill_pattern_2_4".
+   Generating output for cell caravel_00020005_fill_pattern_3_4
+Reading "caravel_00020005_fill_pattern_3_4".
+   Generating output for cell caravel_00020005_fill_pattern_4_4
+Reading "caravel_00020005_fill_pattern_4_4".
+   Generating output for cell caravel_00020005_fill_pattern_5_4
+Reading "caravel_00020005_fill_pattern_5_4".
+   Generating output for cell caravel_00020005_fill_pattern_0_5
+Reading "caravel_00020005_fill_pattern_0_5".
+   Generating output for cell caravel_00020005_fill_pattern_1_5
+Reading "caravel_00020005_fill_pattern_1_5".
+   Generating output for cell caravel_00020005_fill_pattern_2_5
+Reading "caravel_00020005_fill_pattern_2_5".
+   Generating output for cell caravel_00020005_fill_pattern_3_5
+Reading "caravel_00020005_fill_pattern_3_5".
+   Generating output for cell caravel_00020005_fill_pattern_4_5
+Reading "caravel_00020005_fill_pattern_4_5".
+   Generating output for cell caravel_00020005_fill_pattern_5_5
+Reading "caravel_00020005_fill_pattern_5_5".
+   Generating output for cell caravel_00020005_fill_pattern_0_6
+Reading "caravel_00020005_fill_pattern_0_6".
+   Generating output for cell caravel_00020005_fill_pattern_1_6
+Reading "caravel_00020005_fill_pattern_1_6".
+   Generating output for cell caravel_00020005_fill_pattern_2_6
+Reading "caravel_00020005_fill_pattern_2_6".
+   Generating output for cell caravel_00020005_fill_pattern_3_6
+Reading "caravel_00020005_fill_pattern_3_6".
+   Generating output for cell caravel_00020005_fill_pattern_4_6
+Reading "caravel_00020005_fill_pattern_4_6".
+   Generating output for cell caravel_00020005_fill_pattern_5_6
+Reading "caravel_00020005_fill_pattern_5_6".
+   Generating output for cell caravel_00020005_fill_pattern_0_7
+Reading "caravel_00020005_fill_pattern_0_7".
+   Generating output for cell caravel_00020005_fill_pattern_1_7
+Reading "caravel_00020005_fill_pattern_1_7".
+   Generating output for cell caravel_00020005_fill_pattern_2_7
+Reading "caravel_00020005_fill_pattern_2_7".
+   Generating output for cell caravel_00020005_fill_pattern_3_7
+Reading "caravel_00020005_fill_pattern_3_7".
+   Generating output for cell caravel_00020005_fill_pattern_4_7
+Reading "caravel_00020005_fill_pattern_4_7".
+   Generating output for cell caravel_00020005_fill_pattern_5_7
+Reading "caravel_00020005_fill_pattern_5_7".
+   Generating output for cell caravel_00020005_fill_pattern
+Ended: 12/09/2021 16:57:04
+Error message output from magic:
+Error while reading cell "caravel_00020005_fill_pattern_1_4" (byte position 0): Unexpected EOF.
+Done!
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_7
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_5_3: 10000 rects
+caravel_00020005_fill_pattern_5_3: 20000 rects
+caravel_00020005_fill_pattern_5_3: 30000 rects
+caravel_00020005_fill_pattern_5_3: 40000 rects
+caravel_00020005_fill_pattern_5_3: 50000 rects
+caravel_00020005_fill_pattern_5_3: 60000 rects
+caravel_00020005_fill_pattern_5_3: 70000 rects
+caravel_00020005_fill_pattern_5_3: 80000 rects
+caravel_00020005_fill_pattern_5_3: 90000 rects
+caravel_00020005_fill_pattern_5_3: 100000 rects
+caravel_00020005_fill_pattern_5_3: 110000 rects
+caravel_00020005_fill_pattern_5_3: 120000 rects
+caravel_00020005_fill_pattern_5_3: 130000 rects
+caravel_00020005_fill_pattern_5_3: 140000 rects
+caravel_00020005_fill_pattern_5_3: 150000 rects
+caravel_00020005_fill_pattern_5_3: 160000 rects
+caravel_00020005_fill_pattern_5_3: 170000 rects
+caravel_00020005_fill_pattern_5_3: 180000 rects
+caravel_00020005_fill_pattern_5_3: 190000 rects
+caravel_00020005_fill_pattern_5_3: 200000 rects
+caravel_00020005_fill_pattern_5_3: 210000 rects
+caravel_00020005_fill_pattern_5_3: 220000 rects
+caravel_00020005_fill_pattern_5_3: 230000 rects
+caravel_00020005_fill_pattern_5_3: 240000 rects
+caravel_00020005_fill_pattern_5_3: 250000 rects
+caravel_00020005_fill_pattern_5_3: 260000 rects
+caravel_00020005_fill_pattern_5_3: 270000 rects
+caravel_00020005_fill_pattern_5_3: 280000 rects
+caravel_00020005_fill_pattern_5_3: 290000 rects
+caravel_00020005_fill_pattern_5_3: 300000 rects
+caravel_00020005_fill_pattern_5_3: 310000 rects
+caravel_00020005_fill_pattern_5_3: 320000 rects
+caravel_00020005_fill_pattern_5_3: 330000 rects
+caravel_00020005_fill_pattern_5_3: 340000 rects
+caravel_00020005_fill_pattern_5_3: 350000 rects
+caravel_00020005_fill_pattern_5_3: 360000 rects
+caravel_00020005_fill_pattern_5_3: 370000 rects
+caravel_00020005_fill_pattern_5_3: 380000 rects
+caravel_00020005_fill_pattern_5_3: 390000 rects
+caravel_00020005_fill_pattern_5_3: 400000 rects
+caravel_00020005_fill_pattern_5_3: 410000 rects
+caravel_00020005_fill_pattern_5_3: 420000 rects
+caravel_00020005_fill_pattern_5_3: 430000 rects
+caravel_00020005_fill_pattern_5_3: 440000 rects
+caravel_00020005_fill_pattern_5_3: 450000 rects
+caravel_00020005_fill_pattern_5_3: 460000 rects
+caravel_00020005_fill_pattern_5_3: 470000 rects
+caravel_00020005_fill_pattern_5_3: 480000 rects
+caravel_00020005_fill_pattern_5_3: 490000 rects
+caravel_00020005_fill_pattern_5_3: 500000 rects
+caravel_00020005_fill_pattern_5_3: 510000 rects
+caravel_00020005_fill_pattern_5_3: 520000 rects
+caravel_00020005_fill_pattern_5_3: 530000 rects
+caravel_00020005_fill_pattern_5_3: 540000 rects
+caravel_00020005_fill_pattern_5_3: 550000 rects
+caravel_00020005_fill_pattern_5_3: 560000 rects
+caravel_00020005_fill_pattern_5_3: 570000 rects
+caravel_00020005_fill_pattern_5_3: 580000 rects
+caravel_00020005_fill_pattern_5_3: 590000 rects
+caravel_00020005_fill_pattern_5_3: 600000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_3
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_5_0: 10000 rects
+caravel_00020005_fill_pattern_5_0: 20000 rects
+caravel_00020005_fill_pattern_5_0: 30000 rects
+caravel_00020005_fill_pattern_5_0: 40000 rects
+caravel_00020005_fill_pattern_5_0: 50000 rects
+caravel_00020005_fill_pattern_5_0: 60000 rects
+caravel_00020005_fill_pattern_5_0: 70000 rects
+caravel_00020005_fill_pattern_5_0: 80000 rects
+caravel_00020005_fill_pattern_5_0: 90000 rects
+caravel_00020005_fill_pattern_5_0: 100000 rects
+caravel_00020005_fill_pattern_5_0: 110000 rects
+caravel_00020005_fill_pattern_5_0: 120000 rects
+caravel_00020005_fill_pattern_5_0: 130000 rects
+caravel_00020005_fill_pattern_5_0: 140000 rects
+caravel_00020005_fill_pattern_5_0: 150000 rects
+caravel_00020005_fill_pattern_5_0: 160000 rects
+caravel_00020005_fill_pattern_5_0: 170000 rects
+caravel_00020005_fill_pattern_5_0: 180000 rects
+caravel_00020005_fill_pattern_5_0: 190000 rects
+caravel_00020005_fill_pattern_5_0: 200000 rects
+caravel_00020005_fill_pattern_5_0: 210000 rects
+caravel_00020005_fill_pattern_5_0: 220000 rects
+caravel_00020005_fill_pattern_5_0: 230000 rects
+caravel_00020005_fill_pattern_5_0: 240000 rects
+caravel_00020005_fill_pattern_5_0: 250000 rects
+caravel_00020005_fill_pattern_5_0: 260000 rects
+caravel_00020005_fill_pattern_5_0: 270000 rects
+caravel_00020005_fill_pattern_5_0: 280000 rects
+caravel_00020005_fill_pattern_5_0: 290000 rects
+caravel_00020005_fill_pattern_5_0: 300000 rects
+caravel_00020005_fill_pattern_5_0: 310000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_0
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_5_6: 10000 rects
+caravel_00020005_fill_pattern_5_6: 20000 rects
+caravel_00020005_fill_pattern_5_6: 30000 rects
+caravel_00020005_fill_pattern_5_6: 40000 rects
+caravel_00020005_fill_pattern_5_6: 50000 rects
+caravel_00020005_fill_pattern_5_6: 60000 rects
+caravel_00020005_fill_pattern_5_6: 70000 rects
+caravel_00020005_fill_pattern_5_6: 80000 rects
+caravel_00020005_fill_pattern_5_6: 90000 rects
+caravel_00020005_fill_pattern_5_6: 100000 rects
+caravel_00020005_fill_pattern_5_6: 110000 rects
+caravel_00020005_fill_pattern_5_6: 120000 rects
+caravel_00020005_fill_pattern_5_6: 130000 rects
+caravel_00020005_fill_pattern_5_6: 140000 rects
+caravel_00020005_fill_pattern_5_6: 150000 rects
+caravel_00020005_fill_pattern_5_6: 160000 rects
+caravel_00020005_fill_pattern_5_6: 170000 rects
+caravel_00020005_fill_pattern_5_6: 180000 rects
+caravel_00020005_fill_pattern_5_6: 190000 rects
+caravel_00020005_fill_pattern_5_6: 200000 rects
+caravel_00020005_fill_pattern_5_6: 210000 rects
+caravel_00020005_fill_pattern_5_6: 220000 rects
+caravel_00020005_fill_pattern_5_6: 230000 rects
+caravel_00020005_fill_pattern_5_6: 240000 rects
+caravel_00020005_fill_pattern_5_6: 250000 rects
+caravel_00020005_fill_pattern_5_6: 260000 rects
+caravel_00020005_fill_pattern_5_6: 270000 rects
+caravel_00020005_fill_pattern_5_6: 280000 rects
+caravel_00020005_fill_pattern_5_6: 290000 rects
+caravel_00020005_fill_pattern_5_6: 300000 rects
+caravel_00020005_fill_pattern_5_6: 310000 rects
+caravel_00020005_fill_pattern_5_6: 320000 rects
+caravel_00020005_fill_pattern_5_6: 330000 rects
+caravel_00020005_fill_pattern_5_6: 340000 rects
+caravel_00020005_fill_pattern_5_6: 350000 rects
+caravel_00020005_fill_pattern_5_6: 360000 rects
+caravel_00020005_fill_pattern_5_6: 370000 rects
+caravel_00020005_fill_pattern_5_6: 380000 rects
+caravel_00020005_fill_pattern_5_6: 390000 rects
+caravel_00020005_fill_pattern_5_6: 400000 rects
+caravel_00020005_fill_pattern_5_6: 410000 rects
+caravel_00020005_fill_pattern_5_6: 420000 rects
+caravel_00020005_fill_pattern_5_6: 430000 rects
+caravel_00020005_fill_pattern_5_6: 440000 rects
+caravel_00020005_fill_pattern_5_6: 450000 rects
+caravel_00020005_fill_pattern_5_6: 460000 rects
+caravel_00020005_fill_pattern_5_6: 470000 rects
+caravel_00020005_fill_pattern_5_6: 480000 rects
+caravel_00020005_fill_pattern_5_6: 490000 rects
+caravel_00020005_fill_pattern_5_6: 500000 rects
+caravel_00020005_fill_pattern_5_6: 510000 rects
+caravel_00020005_fill_pattern_5_6: 520000 rects
+caravel_00020005_fill_pattern_5_6: 530000 rects
+caravel_00020005_fill_pattern_5_6: 540000 rects
+caravel_00020005_fill_pattern_5_6: 550000 rects
+caravel_00020005_fill_pattern_5_6: 560000 rects
+caravel_00020005_fill_pattern_5_6: 570000 rects
+caravel_00020005_fill_pattern_5_6: 580000 rects
+caravel_00020005_fill_pattern_5_6: 590000 rects
+caravel_00020005_fill_pattern_5_6: 600000 rects
+caravel_00020005_fill_pattern_5_6: 610000 rects
+caravel_00020005_fill_pattern_5_6: 620000 rects
+caravel_00020005_fill_pattern_5_6: 630000 rects
+caravel_00020005_fill_pattern_5_6: 640000 rects
+caravel_00020005_fill_pattern_5_6: 650000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_6
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_5_5: 10000 rects
+caravel_00020005_fill_pattern_5_5: 20000 rects
+caravel_00020005_fill_pattern_5_5: 30000 rects
+caravel_00020005_fill_pattern_5_5: 40000 rects
+caravel_00020005_fill_pattern_5_5: 50000 rects
+caravel_00020005_fill_pattern_5_5: 60000 rects
+caravel_00020005_fill_pattern_5_5: 70000 rects
+caravel_00020005_fill_pattern_5_5: 80000 rects
+caravel_00020005_fill_pattern_5_5: 90000 rects
+caravel_00020005_fill_pattern_5_5: 100000 rects
+caravel_00020005_fill_pattern_5_5: 110000 rects
+caravel_00020005_fill_pattern_5_5: 120000 rects
+caravel_00020005_fill_pattern_5_5: 130000 rects
+caravel_00020005_fill_pattern_5_5: 140000 rects
+caravel_00020005_fill_pattern_5_5: 150000 rects
+caravel_00020005_fill_pattern_5_5: 160000 rects
+caravel_00020005_fill_pattern_5_5: 170000 rects
+caravel_00020005_fill_pattern_5_5: 180000 rects
+caravel_00020005_fill_pattern_5_5: 190000 rects
+caravel_00020005_fill_pattern_5_5: 200000 rects
+caravel_00020005_fill_pattern_5_5: 210000 rects
+caravel_00020005_fill_pattern_5_5: 220000 rects
+caravel_00020005_fill_pattern_5_5: 230000 rects
+caravel_00020005_fill_pattern_5_5: 240000 rects
+caravel_00020005_fill_pattern_5_5: 250000 rects
+caravel_00020005_fill_pattern_5_5: 260000 rects
+caravel_00020005_fill_pattern_5_5: 270000 rects
+caravel_00020005_fill_pattern_5_5: 280000 rects
+caravel_00020005_fill_pattern_5_5: 290000 rects
+caravel_00020005_fill_pattern_5_5: 300000 rects
+caravel_00020005_fill_pattern_5_5: 310000 rects
+caravel_00020005_fill_pattern_5_5: 320000 rects
+caravel_00020005_fill_pattern_5_5: 330000 rects
+caravel_00020005_fill_pattern_5_5: 340000 rects
+caravel_00020005_fill_pattern_5_5: 350000 rects
+caravel_00020005_fill_pattern_5_5: 360000 rects
+caravel_00020005_fill_pattern_5_5: 370000 rects
+caravel_00020005_fill_pattern_5_5: 380000 rects
+caravel_00020005_fill_pattern_5_5: 390000 rects
+caravel_00020005_fill_pattern_5_5: 400000 rects
+caravel_00020005_fill_pattern_5_5: 410000 rects
+caravel_00020005_fill_pattern_5_5: 420000 rects
+caravel_00020005_fill_pattern_5_5: 430000 rects
+caravel_00020005_fill_pattern_5_5: 440000 rects
+caravel_00020005_fill_pattern_5_5: 450000 rects
+caravel_00020005_fill_pattern_5_5: 460000 rects
+caravel_00020005_fill_pattern_5_5: 470000 rects
+caravel_00020005_fill_pattern_5_5: 480000 rects
+caravel_00020005_fill_pattern_5_5: 490000 rects
+caravel_00020005_fill_pattern_5_5: 500000 rects
+caravel_00020005_fill_pattern_5_5: 510000 rects
+caravel_00020005_fill_pattern_5_5: 520000 rects
+caravel_00020005_fill_pattern_5_5: 530000 rects
+caravel_00020005_fill_pattern_5_5: 540000 rects
+caravel_00020005_fill_pattern_5_5: 550000 rects
+caravel_00020005_fill_pattern_5_5: 560000 rects
+caravel_00020005_fill_pattern_5_5: 570000 rects
+caravel_00020005_fill_pattern_5_5: 580000 rects
+caravel_00020005_fill_pattern_5_5: 590000 rects
+caravel_00020005_fill_pattern_5_5: 600000 rects
+caravel_00020005_fill_pattern_5_5: 610000 rects
+caravel_00020005_fill_pattern_5_5: 620000 rects
+caravel_00020005_fill_pattern_5_5: 630000 rects
+caravel_00020005_fill_pattern_5_5: 640000 rects
+caravel_00020005_fill_pattern_5_5: 650000 rects
+caravel_00020005_fill_pattern_5_5: 660000 rects
+caravel_00020005_fill_pattern_5_5: 670000 rects
+caravel_00020005_fill_pattern_5_5: 680000 rects
+caravel_00020005_fill_pattern_5_5: 690000 rects
+caravel_00020005_fill_pattern_5_5: 700000 rects
+caravel_00020005_fill_pattern_5_5: 710000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_5
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_5_1: 10000 rects
+caravel_00020005_fill_pattern_5_1: 20000 rects
+caravel_00020005_fill_pattern_5_1: 30000 rects
+caravel_00020005_fill_pattern_5_1: 40000 rects
+caravel_00020005_fill_pattern_5_1: 50000 rects
+caravel_00020005_fill_pattern_5_1: 60000 rects
+caravel_00020005_fill_pattern_5_1: 70000 rects
+caravel_00020005_fill_pattern_5_1: 80000 rects
+caravel_00020005_fill_pattern_5_1: 90000 rects
+caravel_00020005_fill_pattern_5_1: 100000 rects
+caravel_00020005_fill_pattern_5_1: 110000 rects
+caravel_00020005_fill_pattern_5_1: 120000 rects
+caravel_00020005_fill_pattern_5_1: 130000 rects
+caravel_00020005_fill_pattern_5_1: 140000 rects
+caravel_00020005_fill_pattern_5_1: 150000 rects
+caravel_00020005_fill_pattern_5_1: 160000 rects
+caravel_00020005_fill_pattern_5_1: 170000 rects
+caravel_00020005_fill_pattern_5_1: 180000 rects
+caravel_00020005_fill_pattern_5_1: 190000 rects
+caravel_00020005_fill_pattern_5_1: 200000 rects
+caravel_00020005_fill_pattern_5_1: 210000 rects
+caravel_00020005_fill_pattern_5_1: 220000 rects
+caravel_00020005_fill_pattern_5_1: 230000 rects
+caravel_00020005_fill_pattern_5_1: 240000 rects
+caravel_00020005_fill_pattern_5_1: 250000 rects
+caravel_00020005_fill_pattern_5_1: 260000 rects
+caravel_00020005_fill_pattern_5_1: 270000 rects
+caravel_00020005_fill_pattern_5_1: 280000 rects
+caravel_00020005_fill_pattern_5_1: 290000 rects
+caravel_00020005_fill_pattern_5_1: 300000 rects
+caravel_00020005_fill_pattern_5_1: 310000 rects
+caravel_00020005_fill_pattern_5_1: 320000 rects
+caravel_00020005_fill_pattern_5_1: 330000 rects
+caravel_00020005_fill_pattern_5_1: 340000 rects
+caravel_00020005_fill_pattern_5_1: 350000 rects
+caravel_00020005_fill_pattern_5_1: 360000 rects
+caravel_00020005_fill_pattern_5_1: 370000 rects
+caravel_00020005_fill_pattern_5_1: 380000 rects
+caravel_00020005_fill_pattern_5_1: 390000 rects
+caravel_00020005_fill_pattern_5_1: 400000 rects
+caravel_00020005_fill_pattern_5_1: 410000 rects
+caravel_00020005_fill_pattern_5_1: 420000 rects
+caravel_00020005_fill_pattern_5_1: 430000 rects
+caravel_00020005_fill_pattern_5_1: 440000 rects
+caravel_00020005_fill_pattern_5_1: 450000 rects
+caravel_00020005_fill_pattern_5_1: 460000 rects
+caravel_00020005_fill_pattern_5_1: 470000 rects
+caravel_00020005_fill_pattern_5_1: 480000 rects
+caravel_00020005_fill_pattern_5_1: 490000 rects
+caravel_00020005_fill_pattern_5_1: 500000 rects
+caravel_00020005_fill_pattern_5_1: 510000 rects
+caravel_00020005_fill_pattern_5_1: 520000 rects
+caravel_00020005_fill_pattern_5_1: 530000 rects
+caravel_00020005_fill_pattern_5_1: 540000 rects
+caravel_00020005_fill_pattern_5_1: 550000 rects
+caravel_00020005_fill_pattern_5_1: 560000 rects
+caravel_00020005_fill_pattern_5_1: 570000 rects
+caravel_00020005_fill_pattern_5_1: 580000 rects
+caravel_00020005_fill_pattern_5_1: 590000 rects
+caravel_00020005_fill_pattern_5_1: 600000 rects
+caravel_00020005_fill_pattern_5_1: 610000 rects
+caravel_00020005_fill_pattern_5_1: 620000 rects
+caravel_00020005_fill_pattern_5_1: 630000 rects
+caravel_00020005_fill_pattern_5_1: 640000 rects
+caravel_00020005_fill_pattern_5_1: 650000 rects
+caravel_00020005_fill_pattern_5_1: 660000 rects
+caravel_00020005_fill_pattern_5_1: 670000 rects
+caravel_00020005_fill_pattern_5_1: 680000 rects
+caravel_00020005_fill_pattern_5_1: 690000 rects
+caravel_00020005_fill_pattern_5_1: 700000 rects
+caravel_00020005_fill_pattern_5_1: 710000 rects
+caravel_00020005_fill_pattern_5_1: 720000 rects
+caravel_00020005_fill_pattern_5_1: 730000 rects
+caravel_00020005_fill_pattern_5_1: 740000 rects
+caravel_00020005_fill_pattern_5_1: 750000 rects
+caravel_00020005_fill_pattern_5_1: 760000 rects
+caravel_00020005_fill_pattern_5_1: 770000 rects
+caravel_00020005_fill_pattern_5_1: 780000 rects
+caravel_00020005_fill_pattern_5_1: 790000 rects
+caravel_00020005_fill_pattern_5_1: 800000 rects
+caravel_00020005_fill_pattern_5_1: 810000 rects
+caravel_00020005_fill_pattern_5_1: 820000 rects
+caravel_00020005_fill_pattern_5_1: 830000 rects
+caravel_00020005_fill_pattern_5_1: 840000 rects
+caravel_00020005_fill_pattern_5_1: 850000 rects
+caravel_00020005_fill_pattern_5_1: 860000 rects
+caravel_00020005_fill_pattern_5_1: 870000 rects
+caravel_00020005_fill_pattern_5_1: 880000 rects
+caravel_00020005_fill_pattern_5_1: 890000 rects
+caravel_00020005_fill_pattern_5_1: 900000 rects
+caravel_00020005_fill_pattern_5_1: 910000 rects
+caravel_00020005_fill_pattern_5_1: 920000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_1
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_5_2: 10000 rects
+caravel_00020005_fill_pattern_5_2: 20000 rects
+caravel_00020005_fill_pattern_5_2: 30000 rects
+caravel_00020005_fill_pattern_5_2: 40000 rects
+caravel_00020005_fill_pattern_5_2: 50000 rects
+caravel_00020005_fill_pattern_5_2: 60000 rects
+caravel_00020005_fill_pattern_5_2: 70000 rects
+caravel_00020005_fill_pattern_5_2: 80000 rects
+caravel_00020005_fill_pattern_5_2: 90000 rects
+caravel_00020005_fill_pattern_5_2: 100000 rects
+caravel_00020005_fill_pattern_5_2: 110000 rects
+caravel_00020005_fill_pattern_5_2: 120000 rects
+caravel_00020005_fill_pattern_5_2: 130000 rects
+caravel_00020005_fill_pattern_5_2: 140000 rects
+caravel_00020005_fill_pattern_5_2: 150000 rects
+caravel_00020005_fill_pattern_5_2: 160000 rects
+caravel_00020005_fill_pattern_5_2: 170000 rects
+caravel_00020005_fill_pattern_5_2: 180000 rects
+caravel_00020005_fill_pattern_5_2: 190000 rects
+caravel_00020005_fill_pattern_5_2: 200000 rects
+caravel_00020005_fill_pattern_5_2: 210000 rects
+caravel_00020005_fill_pattern_5_2: 220000 rects
+caravel_00020005_fill_pattern_5_2: 230000 rects
+caravel_00020005_fill_pattern_5_2: 240000 rects
+caravel_00020005_fill_pattern_5_2: 250000 rects
+caravel_00020005_fill_pattern_5_2: 260000 rects
+caravel_00020005_fill_pattern_5_2: 270000 rects
+caravel_00020005_fill_pattern_5_2: 280000 rects
+caravel_00020005_fill_pattern_5_2: 290000 rects
+caravel_00020005_fill_pattern_5_2: 300000 rects
+caravel_00020005_fill_pattern_5_2: 310000 rects
+caravel_00020005_fill_pattern_5_2: 320000 rects
+caravel_00020005_fill_pattern_5_2: 330000 rects
+caravel_00020005_fill_pattern_5_2: 340000 rects
+caravel_00020005_fill_pattern_5_2: 350000 rects
+caravel_00020005_fill_pattern_5_2: 360000 rects
+caravel_00020005_fill_pattern_5_2: 370000 rects
+caravel_00020005_fill_pattern_5_2: 380000 rects
+caravel_00020005_fill_pattern_5_2: 390000 rects
+caravel_00020005_fill_pattern_5_2: 400000 rects
+caravel_00020005_fill_pattern_5_2: 410000 rects
+caravel_00020005_fill_pattern_5_2: 420000 rects
+caravel_00020005_fill_pattern_5_2: 430000 rects
+caravel_00020005_fill_pattern_5_2: 440000 rects
+caravel_00020005_fill_pattern_5_2: 450000 rects
+caravel_00020005_fill_pattern_5_2: 460000 rects
+caravel_00020005_fill_pattern_5_2: 470000 rects
+caravel_00020005_fill_pattern_5_2: 480000 rects
+caravel_00020005_fill_pattern_5_2: 490000 rects
+caravel_00020005_fill_pattern_5_2: 500000 rects
+caravel_00020005_fill_pattern_5_2: 510000 rects
+caravel_00020005_fill_pattern_5_2: 520000 rects
+caravel_00020005_fill_pattern_5_2: 530000 rects
+caravel_00020005_fill_pattern_5_2: 540000 rects
+caravel_00020005_fill_pattern_5_2: 550000 rects
+caravel_00020005_fill_pattern_5_2: 560000 rects
+caravel_00020005_fill_pattern_5_2: 570000 rects
+caravel_00020005_fill_pattern_5_2: 580000 rects
+caravel_00020005_fill_pattern_5_2: 590000 rects
+caravel_00020005_fill_pattern_5_2: 600000 rects
+caravel_00020005_fill_pattern_5_2: 610000 rects
+caravel_00020005_fill_pattern_5_2: 620000 rects
+caravel_00020005_fill_pattern_5_2: 630000 rects
+caravel_00020005_fill_pattern_5_2: 640000 rects
+caravel_00020005_fill_pattern_5_2: 650000 rects
+caravel_00020005_fill_pattern_5_2: 660000 rects
+caravel_00020005_fill_pattern_5_2: 670000 rects
+caravel_00020005_fill_pattern_5_2: 680000 rects
+caravel_00020005_fill_pattern_5_2: 690000 rects
+caravel_00020005_fill_pattern_5_2: 700000 rects
+caravel_00020005_fill_pattern_5_2: 710000 rects
+caravel_00020005_fill_pattern_5_2: 720000 rects
+caravel_00020005_fill_pattern_5_2: 730000 rects
+caravel_00020005_fill_pattern_5_2: 740000 rects
+caravel_00020005_fill_pattern_5_2: 750000 rects
+caravel_00020005_fill_pattern_5_2: 760000 rects
+caravel_00020005_fill_pattern_5_2: 770000 rects
+caravel_00020005_fill_pattern_5_2: 780000 rects
+caravel_00020005_fill_pattern_5_2: 790000 rects
+caravel_00020005_fill_pattern_5_2: 800000 rects
+caravel_00020005_fill_pattern_5_2: 810000 rects
+caravel_00020005_fill_pattern_5_2: 820000 rects
+caravel_00020005_fill_pattern_5_2: 830000 rects
+caravel_00020005_fill_pattern_5_2: 840000 rects
+caravel_00020005_fill_pattern_5_2: 850000 rects
+caravel_00020005_fill_pattern_5_2: 860000 rects
+caravel_00020005_fill_pattern_5_2: 870000 rects
+caravel_00020005_fill_pattern_5_2: 880000 rects
+caravel_00020005_fill_pattern_5_2: 890000 rects
+caravel_00020005_fill_pattern_5_2: 900000 rects
+caravel_00020005_fill_pattern_5_2: 910000 rects
+caravel_00020005_fill_pattern_5_2: 920000 rects
+caravel_00020005_fill_pattern_5_2: 930000 rects
+caravel_00020005_fill_pattern_5_2: 940000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_2
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_5_4: 10000 rects
+caravel_00020005_fill_pattern_5_4: 20000 rects
+caravel_00020005_fill_pattern_5_4: 30000 rects
+caravel_00020005_fill_pattern_5_4: 40000 rects
+caravel_00020005_fill_pattern_5_4: 50000 rects
+caravel_00020005_fill_pattern_5_4: 60000 rects
+caravel_00020005_fill_pattern_5_4: 70000 rects
+caravel_00020005_fill_pattern_5_4: 80000 rects
+caravel_00020005_fill_pattern_5_4: 90000 rects
+caravel_00020005_fill_pattern_5_4: 100000 rects
+caravel_00020005_fill_pattern_5_4: 110000 rects
+caravel_00020005_fill_pattern_5_4: 120000 rects
+caravel_00020005_fill_pattern_5_4: 130000 rects
+caravel_00020005_fill_pattern_5_4: 140000 rects
+caravel_00020005_fill_pattern_5_4: 150000 rects
+caravel_00020005_fill_pattern_5_4: 160000 rects
+caravel_00020005_fill_pattern_5_4: 170000 rects
+caravel_00020005_fill_pattern_5_4: 180000 rects
+caravel_00020005_fill_pattern_5_4: 190000 rects
+caravel_00020005_fill_pattern_5_4: 200000 rects
+caravel_00020005_fill_pattern_5_4: 210000 rects
+caravel_00020005_fill_pattern_5_4: 220000 rects
+caravel_00020005_fill_pattern_5_4: 230000 rects
+caravel_00020005_fill_pattern_5_4: 240000 rects
+caravel_00020005_fill_pattern_5_4: 250000 rects
+caravel_00020005_fill_pattern_5_4: 260000 rects
+caravel_00020005_fill_pattern_5_4: 270000 rects
+caravel_00020005_fill_pattern_5_4: 280000 rects
+caravel_00020005_fill_pattern_5_4: 290000 rects
+caravel_00020005_fill_pattern_5_4: 300000 rects
+caravel_00020005_fill_pattern_5_4: 310000 rects
+caravel_00020005_fill_pattern_5_4: 320000 rects
+caravel_00020005_fill_pattern_5_4: 330000 rects
+caravel_00020005_fill_pattern_5_4: 340000 rects
+caravel_00020005_fill_pattern_5_4: 350000 rects
+caravel_00020005_fill_pattern_5_4: 360000 rects
+caravel_00020005_fill_pattern_5_4: 370000 rects
+caravel_00020005_fill_pattern_5_4: 380000 rects
+caravel_00020005_fill_pattern_5_4: 390000 rects
+caravel_00020005_fill_pattern_5_4: 400000 rects
+caravel_00020005_fill_pattern_5_4: 410000 rects
+caravel_00020005_fill_pattern_5_4: 420000 rects
+caravel_00020005_fill_pattern_5_4: 430000 rects
+caravel_00020005_fill_pattern_5_4: 440000 rects
+caravel_00020005_fill_pattern_5_4: 450000 rects
+caravel_00020005_fill_pattern_5_4: 460000 rects
+caravel_00020005_fill_pattern_5_4: 470000 rects
+caravel_00020005_fill_pattern_5_4: 480000 rects
+caravel_00020005_fill_pattern_5_4: 490000 rects
+caravel_00020005_fill_pattern_5_4: 500000 rects
+caravel_00020005_fill_pattern_5_4: 510000 rects
+caravel_00020005_fill_pattern_5_4: 520000 rects
+caravel_00020005_fill_pattern_5_4: 530000 rects
+caravel_00020005_fill_pattern_5_4: 540000 rects
+caravel_00020005_fill_pattern_5_4: 550000 rects
+caravel_00020005_fill_pattern_5_4: 560000 rects
+caravel_00020005_fill_pattern_5_4: 570000 rects
+caravel_00020005_fill_pattern_5_4: 580000 rects
+caravel_00020005_fill_pattern_5_4: 590000 rects
+caravel_00020005_fill_pattern_5_4: 600000 rects
+caravel_00020005_fill_pattern_5_4: 610000 rects
+caravel_00020005_fill_pattern_5_4: 620000 rects
+caravel_00020005_fill_pattern_5_4: 630000 rects
+caravel_00020005_fill_pattern_5_4: 640000 rects
+caravel_00020005_fill_pattern_5_4: 650000 rects
+caravel_00020005_fill_pattern_5_4: 660000 rects
+caravel_00020005_fill_pattern_5_4: 670000 rects
+caravel_00020005_fill_pattern_5_4: 680000 rects
+caravel_00020005_fill_pattern_5_4: 690000 rects
+caravel_00020005_fill_pattern_5_4: 700000 rects
+caravel_00020005_fill_pattern_5_4: 710000 rects
+caravel_00020005_fill_pattern_5_4: 720000 rects
+caravel_00020005_fill_pattern_5_4: 730000 rects
+caravel_00020005_fill_pattern_5_4: 740000 rects
+caravel_00020005_fill_pattern_5_4: 750000 rects
+caravel_00020005_fill_pattern_5_4: 760000 rects
+caravel_00020005_fill_pattern_5_4: 770000 rects
+caravel_00020005_fill_pattern_5_4: 780000 rects
+caravel_00020005_fill_pattern_5_4: 790000 rects
+caravel_00020005_fill_pattern_5_4: 800000 rects
+caravel_00020005_fill_pattern_5_4: 810000 rects
+caravel_00020005_fill_pattern_5_4: 820000 rects
+caravel_00020005_fill_pattern_5_4: 830000 rects
+caravel_00020005_fill_pattern_5_4: 840000 rects
+caravel_00020005_fill_pattern_5_4: 850000 rects
+caravel_00020005_fill_pattern_5_4: 860000 rects
+caravel_00020005_fill_pattern_5_4: 870000 rects
+caravel_00020005_fill_pattern_5_4: 880000 rects
+caravel_00020005_fill_pattern_5_4: 890000 rects
+caravel_00020005_fill_pattern_5_4: 900000 rects
+caravel_00020005_fill_pattern_5_4: 910000 rects
+caravel_00020005_fill_pattern_5_4: 920000 rects
+caravel_00020005_fill_pattern_5_4: 930000 rects
+caravel_00020005_fill_pattern_5_4: 940000 rects
+caravel_00020005_fill_pattern_5_4: 950000 rects
+caravel_00020005_fill_pattern_5_4: 960000 rects
+caravel_00020005_fill_pattern_5_4: 970000 rects
+caravel_00020005_fill_pattern_5_4: 980000 rects
+caravel_00020005_fill_pattern_5_4: 990000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_4
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_4_7: 10000 rects
+caravel_00020005_fill_pattern_4_7: 20000 rects
+caravel_00020005_fill_pattern_4_7: 30000 rects
+caravel_00020005_fill_pattern_4_7: 40000 rects
+caravel_00020005_fill_pattern_4_7: 50000 rects
+caravel_00020005_fill_pattern_4_7: 60000 rects
+caravel_00020005_fill_pattern_4_7: 70000 rects
+caravel_00020005_fill_pattern_4_7: 80000 rects
+caravel_00020005_fill_pattern_4_7: 90000 rects
+caravel_00020005_fill_pattern_4_7: 100000 rects
+caravel_00020005_fill_pattern_4_7: 110000 rects
+caravel_00020005_fill_pattern_4_7: 120000 rects
+caravel_00020005_fill_pattern_4_7: 130000 rects
+caravel_00020005_fill_pattern_4_7: 140000 rects
+caravel_00020005_fill_pattern_4_7: 150000 rects
+caravel_00020005_fill_pattern_4_7: 160000 rects
+caravel_00020005_fill_pattern_4_7: 170000 rects
+caravel_00020005_fill_pattern_4_7: 180000 rects
+caravel_00020005_fill_pattern_4_7: 190000 rects
+caravel_00020005_fill_pattern_4_7: 200000 rects
+caravel_00020005_fill_pattern_4_7: 210000 rects
+caravel_00020005_fill_pattern_4_7: 220000 rects
+caravel_00020005_fill_pattern_4_7: 230000 rects
+caravel_00020005_fill_pattern_4_7: 240000 rects
+caravel_00020005_fill_pattern_4_7: 250000 rects
+caravel_00020005_fill_pattern_4_7: 260000 rects
+caravel_00020005_fill_pattern_4_7: 270000 rects
+caravel_00020005_fill_pattern_4_7: 280000 rects
+caravel_00020005_fill_pattern_4_7: 290000 rects
+caravel_00020005_fill_pattern_4_7: 300000 rects
+caravel_00020005_fill_pattern_4_7: 310000 rects
+caravel_00020005_fill_pattern_4_7: 320000 rects
+caravel_00020005_fill_pattern_4_7: 330000 rects
+caravel_00020005_fill_pattern_4_7: 340000 rects
+caravel_00020005_fill_pattern_4_7: 350000 rects
+caravel_00020005_fill_pattern_4_7: 360000 rects
+caravel_00020005_fill_pattern_4_7: 370000 rects
+caravel_00020005_fill_pattern_4_7: 380000 rects
+caravel_00020005_fill_pattern_4_7: 390000 rects
+caravel_00020005_fill_pattern_4_7: 400000 rects
+caravel_00020005_fill_pattern_4_7: 410000 rects
+caravel_00020005_fill_pattern_4_7: 420000 rects
+caravel_00020005_fill_pattern_4_7: 430000 rects
+caravel_00020005_fill_pattern_4_7: 440000 rects
+caravel_00020005_fill_pattern_4_7: 450000 rects
+caravel_00020005_fill_pattern_4_7: 460000 rects
+caravel_00020005_fill_pattern_4_7: 470000 rects
+caravel_00020005_fill_pattern_4_7: 480000 rects
+caravel_00020005_fill_pattern_4_7: 490000 rects
+caravel_00020005_fill_pattern_4_7: 500000 rects
+caravel_00020005_fill_pattern_4_7: 510000 rects
+caravel_00020005_fill_pattern_4_7: 520000 rects
+caravel_00020005_fill_pattern_4_7: 530000 rects
+caravel_00020005_fill_pattern_4_7: 540000 rects
+caravel_00020005_fill_pattern_4_7: 550000 rects
+caravel_00020005_fill_pattern_4_7: 560000 rects
+caravel_00020005_fill_pattern_4_7: 570000 rects
+caravel_00020005_fill_pattern_4_7: 580000 rects
+caravel_00020005_fill_pattern_4_7: 590000 rects
+caravel_00020005_fill_pattern_4_7: 600000 rects
+caravel_00020005_fill_pattern_4_7: 610000 rects
+caravel_00020005_fill_pattern_4_7: 620000 rects
+caravel_00020005_fill_pattern_4_7: 630000 rects
+caravel_00020005_fill_pattern_4_7: 640000 rects
+caravel_00020005_fill_pattern_4_7: 650000 rects
+caravel_00020005_fill_pattern_4_7: 660000 rects
+caravel_00020005_fill_pattern_4_7: 670000 rects
+caravel_00020005_fill_pattern_4_7: 680000 rects
+caravel_00020005_fill_pattern_4_7: 690000 rects
+caravel_00020005_fill_pattern_4_7: 700000 rects
+caravel_00020005_fill_pattern_4_7: 710000 rects
+caravel_00020005_fill_pattern_4_7: 720000 rects
+caravel_00020005_fill_pattern_4_7: 730000 rects
+caravel_00020005_fill_pattern_4_7: 740000 rects
+caravel_00020005_fill_pattern_4_7: 750000 rects
+caravel_00020005_fill_pattern_4_7: 760000 rects
+caravel_00020005_fill_pattern_4_7: 770000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_7
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_3_7: 10000 rects
+caravel_00020005_fill_pattern_3_7: 20000 rects
+caravel_00020005_fill_pattern_3_7: 30000 rects
+caravel_00020005_fill_pattern_3_7: 40000 rects
+caravel_00020005_fill_pattern_3_7: 50000 rects
+caravel_00020005_fill_pattern_3_7: 60000 rects
+caravel_00020005_fill_pattern_3_7: 70000 rects
+caravel_00020005_fill_pattern_3_7: 80000 rects
+caravel_00020005_fill_pattern_3_7: 90000 rects
+caravel_00020005_fill_pattern_3_7: 100000 rects
+caravel_00020005_fill_pattern_3_7: 110000 rects
+caravel_00020005_fill_pattern_3_7: 120000 rects
+caravel_00020005_fill_pattern_3_7: 130000 rects
+caravel_00020005_fill_pattern_3_7: 140000 rects
+caravel_00020005_fill_pattern_3_7: 150000 rects
+caravel_00020005_fill_pattern_3_7: 160000 rects
+caravel_00020005_fill_pattern_3_7: 170000 rects
+caravel_00020005_fill_pattern_3_7: 180000 rects
+caravel_00020005_fill_pattern_3_7: 190000 rects
+caravel_00020005_fill_pattern_3_7: 200000 rects
+caravel_00020005_fill_pattern_3_7: 210000 rects
+caravel_00020005_fill_pattern_3_7: 220000 rects
+caravel_00020005_fill_pattern_3_7: 230000 rects
+caravel_00020005_fill_pattern_3_7: 240000 rects
+caravel_00020005_fill_pattern_3_7: 250000 rects
+caravel_00020005_fill_pattern_3_7: 260000 rects
+caravel_00020005_fill_pattern_3_7: 270000 rects
+caravel_00020005_fill_pattern_3_7: 280000 rects
+caravel_00020005_fill_pattern_3_7: 290000 rects
+caravel_00020005_fill_pattern_3_7: 300000 rects
+caravel_00020005_fill_pattern_3_7: 310000 rects
+caravel_00020005_fill_pattern_3_7: 320000 rects
+caravel_00020005_fill_pattern_3_7: 330000 rects
+caravel_00020005_fill_pattern_3_7: 340000 rects
+caravel_00020005_fill_pattern_3_7: 350000 rects
+caravel_00020005_fill_pattern_3_7: 360000 rects
+caravel_00020005_fill_pattern_3_7: 370000 rects
+caravel_00020005_fill_pattern_3_7: 380000 rects
+caravel_00020005_fill_pattern_3_7: 390000 rects
+caravel_00020005_fill_pattern_3_7: 400000 rects
+caravel_00020005_fill_pattern_3_7: 410000 rects
+caravel_00020005_fill_pattern_3_7: 420000 rects
+caravel_00020005_fill_pattern_3_7: 430000 rects
+caravel_00020005_fill_pattern_3_7: 440000 rects
+caravel_00020005_fill_pattern_3_7: 450000 rects
+caravel_00020005_fill_pattern_3_7: 460000 rects
+caravel_00020005_fill_pattern_3_7: 470000 rects
+caravel_00020005_fill_pattern_3_7: 480000 rects
+caravel_00020005_fill_pattern_3_7: 490000 rects
+caravel_00020005_fill_pattern_3_7: 500000 rects
+caravel_00020005_fill_pattern_3_7: 510000 rects
+caravel_00020005_fill_pattern_3_7: 520000 rects
+caravel_00020005_fill_pattern_3_7: 530000 rects
+caravel_00020005_fill_pattern_3_7: 540000 rects
+caravel_00020005_fill_pattern_3_7: 550000 rects
+caravel_00020005_fill_pattern_3_7: 560000 rects
+caravel_00020005_fill_pattern_3_7: 570000 rects
+caravel_00020005_fill_pattern_3_7: 580000 rects
+caravel_00020005_fill_pattern_3_7: 590000 rects
+caravel_00020005_fill_pattern_3_7: 600000 rects
+caravel_00020005_fill_pattern_3_7: 610000 rects
+caravel_00020005_fill_pattern_3_7: 620000 rects
+caravel_00020005_fill_pattern_3_7: 630000 rects
+caravel_00020005_fill_pattern_3_7: 640000 rects
+caravel_00020005_fill_pattern_3_7: 650000 rects
+caravel_00020005_fill_pattern_3_7: 660000 rects
+caravel_00020005_fill_pattern_3_7: 670000 rects
+caravel_00020005_fill_pattern_3_7: 680000 rects
+caravel_00020005_fill_pattern_3_7: 690000 rects
+caravel_00020005_fill_pattern_3_7: 700000 rects
+caravel_00020005_fill_pattern_3_7: 710000 rects
+caravel_00020005_fill_pattern_3_7: 720000 rects
+caravel_00020005_fill_pattern_3_7: 730000 rects
+caravel_00020005_fill_pattern_3_7: 740000 rects
+caravel_00020005_fill_pattern_3_7: 750000 rects
+caravel_00020005_fill_pattern_3_7: 760000 rects
+caravel_00020005_fill_pattern_3_7: 770000 rects
+caravel_00020005_fill_pattern_3_7: 780000 rects
+caravel_00020005_fill_pattern_3_7: 790000 rects
+caravel_00020005_fill_pattern_3_7: 800000 rects
+caravel_00020005_fill_pattern_3_7: 810000 rects
+caravel_00020005_fill_pattern_3_7: 820000 rects
+caravel_00020005_fill_pattern_3_7: 830000 rects
+caravel_00020005_fill_pattern_3_7: 840000 rects
+caravel_00020005_fill_pattern_3_7: 850000 rects
+caravel_00020005_fill_pattern_3_7: 860000 rects
+caravel_00020005_fill_pattern_3_7: 870000 rects
+caravel_00020005_fill_pattern_3_7: 880000 rects
+caravel_00020005_fill_pattern_3_7: 890000 rects
+caravel_00020005_fill_pattern_3_7: 900000 rects
+caravel_00020005_fill_pattern_3_7: 910000 rects
+caravel_00020005_fill_pattern_3_7: 920000 rects
+caravel_00020005_fill_pattern_3_7: 930000 rects
+caravel_00020005_fill_pattern_3_7: 940000 rects
+caravel_00020005_fill_pattern_3_7: 950000 rects
+caravel_00020005_fill_pattern_3_7: 960000 rects
+caravel_00020005_fill_pattern_3_7: 970000 rects
+caravel_00020005_fill_pattern_3_7: 980000 rects
+caravel_00020005_fill_pattern_3_7: 990000 rects
+caravel_00020005_fill_pattern_3_7: 1000000 rects
+caravel_00020005_fill_pattern_3_7: 1010000 rects
+caravel_00020005_fill_pattern_3_7: 1020000 rects
+caravel_00020005_fill_pattern_3_7: 1030000 rects
+caravel_00020005_fill_pattern_3_7: 1040000 rects
+caravel_00020005_fill_pattern_3_7: 1050000 rects
+caravel_00020005_fill_pattern_3_7: 1060000 rects
+caravel_00020005_fill_pattern_3_7: 1070000 rects
+caravel_00020005_fill_pattern_3_7: 1080000 rects
+caravel_00020005_fill_pattern_3_7: 1090000 rects
+caravel_00020005_fill_pattern_3_7: 1100000 rects
+caravel_00020005_fill_pattern_3_7: 1110000 rects
+caravel_00020005_fill_pattern_3_7: 1120000 rects
+caravel_00020005_fill_pattern_3_7: 1130000 rects
+caravel_00020005_fill_pattern_3_7: 1140000 rects
+caravel_00020005_fill_pattern_3_7: 1150000 rects
+caravel_00020005_fill_pattern_3_7: 1160000 rects
+caravel_00020005_fill_pattern_3_7: 1170000 rects
+caravel_00020005_fill_pattern_3_7: 1180000 rects
+caravel_00020005_fill_pattern_3_7: 1190000 rects
+caravel_00020005_fill_pattern_3_7: 1200000 rects
+caravel_00020005_fill_pattern_3_7: 1210000 rects
+caravel_00020005_fill_pattern_3_7: 1220000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_7
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_2_7: 10000 rects
+caravel_00020005_fill_pattern_2_7: 20000 rects
+caravel_00020005_fill_pattern_2_7: 30000 rects
+caravel_00020005_fill_pattern_2_7: 40000 rects
+caravel_00020005_fill_pattern_2_7: 50000 rects
+caravel_00020005_fill_pattern_2_7: 60000 rects
+caravel_00020005_fill_pattern_2_7: 70000 rects
+caravel_00020005_fill_pattern_2_7: 80000 rects
+caravel_00020005_fill_pattern_2_7: 90000 rects
+caravel_00020005_fill_pattern_2_7: 100000 rects
+caravel_00020005_fill_pattern_2_7: 110000 rects
+caravel_00020005_fill_pattern_2_7: 120000 rects
+caravel_00020005_fill_pattern_2_7: 130000 rects
+caravel_00020005_fill_pattern_2_7: 140000 rects
+caravel_00020005_fill_pattern_2_7: 150000 rects
+caravel_00020005_fill_pattern_2_7: 160000 rects
+caravel_00020005_fill_pattern_2_7: 170000 rects
+caravel_00020005_fill_pattern_2_7: 180000 rects
+caravel_00020005_fill_pattern_2_7: 190000 rects
+caravel_00020005_fill_pattern_2_7: 200000 rects
+caravel_00020005_fill_pattern_2_7: 210000 rects
+caravel_00020005_fill_pattern_2_7: 220000 rects
+caravel_00020005_fill_pattern_2_7: 230000 rects
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+caravel_00020005_fill_pattern_2_7: 1410000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_7
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_1_7: 10000 rects
+caravel_00020005_fill_pattern_1_7: 20000 rects
+caravel_00020005_fill_pattern_1_7: 30000 rects
+caravel_00020005_fill_pattern_1_7: 40000 rects
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+caravel_00020005_fill_pattern_1_7: 60000 rects
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+caravel_00020005_fill_pattern_1_7: 80000 rects
+caravel_00020005_fill_pattern_1_7: 90000 rects
+caravel_00020005_fill_pattern_1_7: 100000 rects
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+caravel_00020005_fill_pattern_1_7: 1340000 rects
+caravel_00020005_fill_pattern_1_7: 1350000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_7
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_0_7: 10000 rects
+caravel_00020005_fill_pattern_0_7: 20000 rects
+caravel_00020005_fill_pattern_0_7: 30000 rects
+caravel_00020005_fill_pattern_0_7: 40000 rects
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+caravel_00020005_fill_pattern_0_7: 90000 rects
+caravel_00020005_fill_pattern_0_7: 100000 rects
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+caravel_00020005_fill_pattern_0_7: 980000 rects
+caravel_00020005_fill_pattern_0_7: 990000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_0_7
+
+caravel_00020005_fill_pattern_4_0: 1560000 rects
+caravel_00020005_fill_pattern_4_0: 1570000 rects
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+caravel_00020005_fill_pattern_4_0: 2560000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_0
+
+caravel_00020005_fill_pattern_4_1: 1560000 rects
+caravel_00020005_fill_pattern_4_1: 1570000 rects
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+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_1
+
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+caravel_00020005_fill_pattern_0_6: 4240000 rects
+caravel_00020005_fill_pattern_0_6: 4250000 rects
+caravel_00020005_fill_pattern_0_6: 4260000 rects
+caravel_00020005_fill_pattern_0_6: 4270000 rects
+caravel_00020005_fill_pattern_0_6: 4280000 rects
+caravel_00020005_fill_pattern_0_6: 4290000 rects
+caravel_00020005_fill_pattern_0_6: 4300000 rects
+caravel_00020005_fill_pattern_0_6: 4310000 rects
+caravel_00020005_fill_pattern_0_6: 4320000 rects
+caravel_00020005_fill_pattern_0_6: 4330000 rects
+caravel_00020005_fill_pattern_0_6: 4340000 rects
+caravel_00020005_fill_pattern_0_6: 4350000 rects
+caravel_00020005_fill_pattern_0_6: 4360000 rects
+caravel_00020005_fill_pattern_0_6: 4370000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_0_6
+
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_4
+
+caravel_00020005_fill_pattern_1_1: 3240000 rects
+caravel_00020005_fill_pattern_1_1: 3250000 rects
+caravel_00020005_fill_pattern_1_1: 3260000 rects
+caravel_00020005_fill_pattern_1_1: 3270000 rects
+caravel_00020005_fill_pattern_1_1: 3280000 rects
+caravel_00020005_fill_pattern_1_1: 3290000 rects
+caravel_00020005_fill_pattern_1_1: 3300000 rects
+caravel_00020005_fill_pattern_1_1: 3310000 rects
+caravel_00020005_fill_pattern_1_1: 3320000 rects
+caravel_00020005_fill_pattern_1_1: 3330000 rects
+caravel_00020005_fill_pattern_1_1: 3340000 rects
+caravel_00020005_fill_pattern_1_1: 3350000 rects
+caravel_00020005_fill_pattern_1_1: 3360000 rects
+caravel_00020005_fill_pattern_1_1: 3370000 rects
+caravel_00020005_fill_pattern_1_1: 3380000 rects
+caravel_00020005_fill_pattern_1_1: 3390000 rects
+caravel_00020005_fill_pattern_1_1: 3400000 rects
+caravel_00020005_fill_pattern_1_1: 3410000 rects
+caravel_00020005_fill_pattern_1_1: 3420000 rects
+caravel_00020005_fill_pattern_1_1: 3430000 rects
+caravel_00020005_fill_pattern_1_1: 3440000 rects
+caravel_00020005_fill_pattern_1_1: 3450000 rects
+caravel_00020005_fill_pattern_1_1: 3460000 rects
+caravel_00020005_fill_pattern_1_1: 3470000 rects
+caravel_00020005_fill_pattern_1_1: 3480000 rects
+caravel_00020005_fill_pattern_1_1: 3490000 rects
+caravel_00020005_fill_pattern_1_1: 3500000 rects
+caravel_00020005_fill_pattern_1_1: 3510000 rects
+caravel_00020005_fill_pattern_1_1: 3520000 rects
+caravel_00020005_fill_pattern_1_1: 3530000 rects
+caravel_00020005_fill_pattern_1_1: 3540000 rects
+caravel_00020005_fill_pattern_1_1: 3550000 rects
+caravel_00020005_fill_pattern_1_1: 3560000 rects
+caravel_00020005_fill_pattern_1_1: 3570000 rects
+caravel_00020005_fill_pattern_1_1: 3580000 rects
+caravel_00020005_fill_pattern_1_1: 3590000 rects
+caravel_00020005_fill_pattern_1_1: 3600000 rects
+caravel_00020005_fill_pattern_1_1: 3610000 rects
+caravel_00020005_fill_pattern_1_1: 3620000 rects
+caravel_00020005_fill_pattern_1_1: 3630000 rects
+caravel_00020005_fill_pattern_1_1: 3640000 rects
+caravel_00020005_fill_pattern_1_1: 3650000 rects
+caravel_00020005_fill_pattern_1_1: 3660000 rects
+caravel_00020005_fill_pattern_1_1: 3670000 rects
+caravel_00020005_fill_pattern_1_1: 3680000 rects
+caravel_00020005_fill_pattern_1_1: 3690000 rects
+caravel_00020005_fill_pattern_1_1: 3700000 rects
+caravel_00020005_fill_pattern_1_1: 3710000 rects
+caravel_00020005_fill_pattern_1_1: 3720000 rects
+caravel_00020005_fill_pattern_1_1: 3730000 rects
+caravel_00020005_fill_pattern_1_1: 3740000 rects
+caravel_00020005_fill_pattern_1_1: 3750000 rects
+caravel_00020005_fill_pattern_1_1: 3760000 rects
+caravel_00020005_fill_pattern_1_1: 3770000 rects
+caravel_00020005_fill_pattern_1_1: 3780000 rects
+caravel_00020005_fill_pattern_1_1: 3790000 rects
+caravel_00020005_fill_pattern_1_1: 3800000 rects
+caravel_00020005_fill_pattern_1_1: 3810000 rects
+caravel_00020005_fill_pattern_1_1: 3820000 rects
+caravel_00020005_fill_pattern_1_1: 3830000 rects
+caravel_00020005_fill_pattern_1_1: 3840000 rects
+caravel_00020005_fill_pattern_1_1: 3850000 rects
+caravel_00020005_fill_pattern_1_1: 3860000 rects
+caravel_00020005_fill_pattern_1_1: 3870000 rects
+caravel_00020005_fill_pattern_1_1: 3880000 rects
+caravel_00020005_fill_pattern_1_1: 3890000 rects
+caravel_00020005_fill_pattern_1_1: 3900000 rects
+caravel_00020005_fill_pattern_1_1: 3910000 rects
+caravel_00020005_fill_pattern_1_1: 3920000 rects
+caravel_00020005_fill_pattern_1_1: 3930000 rects
+caravel_00020005_fill_pattern_1_1: 3940000 rects
+caravel_00020005_fill_pattern_1_1: 3950000 rects
+caravel_00020005_fill_pattern_1_1: 3960000 rects
+caravel_00020005_fill_pattern_1_1: 3970000 rects
+caravel_00020005_fill_pattern_1_1: 3980000 rects
+caravel_00020005_fill_pattern_1_1: 3990000 rects
+caravel_00020005_fill_pattern_1_1: 4000000 rects
+caravel_00020005_fill_pattern_1_1: 4010000 rects
+caravel_00020005_fill_pattern_1_1: 4020000 rects
+caravel_00020005_fill_pattern_1_1: 4030000 rects
+caravel_00020005_fill_pattern_1_1: 4040000 rects
+caravel_00020005_fill_pattern_1_1: 4050000 rects
+caravel_00020005_fill_pattern_1_1: 4060000 rects
+caravel_00020005_fill_pattern_1_1: 4070000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_1
+
+caravel_00020005_fill_pattern_0_4: 4920000 rects
+caravel_00020005_fill_pattern_0_4: 4930000 rects
+caravel_00020005_fill_pattern_0_4: 4940000 rects
+caravel_00020005_fill_pattern_0_4: 4950000 rects
+caravel_00020005_fill_pattern_0_4: 4960000 rects
+caravel_00020005_fill_pattern_0_4: 4970000 rects
+caravel_00020005_fill_pattern_0_4: 4980000 rects
+caravel_00020005_fill_pattern_0_4: 4990000 rects
+caravel_00020005_fill_pattern_0_4: 5000000 rects
+caravel_00020005_fill_pattern_0_4: 5010000 rects
+caravel_00020005_fill_pattern_0_4: 5020000 rects
+caravel_00020005_fill_pattern_0_4: 5030000 rects
+caravel_00020005_fill_pattern_0_4: 5040000 rects
+caravel_00020005_fill_pattern_0_4: 5050000 rects
+caravel_00020005_fill_pattern_0_4: 5060000 rects
+caravel_00020005_fill_pattern_0_4: 5070000 rects
+caravel_00020005_fill_pattern_0_4: 5080000 rects
+caravel_00020005_fill_pattern_0_4: 5090000 rects
+caravel_00020005_fill_pattern_0_4: 5100000 rects
+caravel_00020005_fill_pattern_0_4: 5110000 rects
+caravel_00020005_fill_pattern_0_4: 5120000 rects
+caravel_00020005_fill_pattern_0_4: 5130000 rects
+caravel_00020005_fill_pattern_0_4: 5140000 rects
+caravel_00020005_fill_pattern_0_4: 5150000 rects
+caravel_00020005_fill_pattern_0_4: 5160000 rects
+caravel_00020005_fill_pattern_0_4: 5170000 rects
+caravel_00020005_fill_pattern_0_4: 5180000 rects
+caravel_00020005_fill_pattern_0_4: 5190000 rects
+caravel_00020005_fill_pattern_0_4: 5200000 rects
+caravel_00020005_fill_pattern_0_4: 5210000 rects
+caravel_00020005_fill_pattern_0_4: 5220000 rects
+caravel_00020005_fill_pattern_0_4: 5230000 rects
+caravel_00020005_fill_pattern_0_4: 5240000 rects
+caravel_00020005_fill_pattern_0_4: 5250000 rects
+caravel_00020005_fill_pattern_0_4: 5260000 rects
+caravel_00020005_fill_pattern_0_4: 5270000 rects
+caravel_00020005_fill_pattern_0_4: 5280000 rects
+caravel_00020005_fill_pattern_0_4: 5290000 rects
+caravel_00020005_fill_pattern_0_4: 5300000 rects
+caravel_00020005_fill_pattern_0_4: 5310000 rects
+caravel_00020005_fill_pattern_0_4: 5320000 rects
+caravel_00020005_fill_pattern_0_4: 5330000 rects
+caravel_00020005_fill_pattern_0_4: 5340000 rects
+caravel_00020005_fill_pattern_0_4: 5350000 rects
+caravel_00020005_fill_pattern_0_4: 5360000 rects
+caravel_00020005_fill_pattern_0_4: 5370000 rects
+caravel_00020005_fill_pattern_0_4: 5380000 rects
+caravel_00020005_fill_pattern_0_4: 5390000 rects
+caravel_00020005_fill_pattern_0_4: 5400000 rects
+caravel_00020005_fill_pattern_0_4: 5410000 rects
+caravel_00020005_fill_pattern_0_4: 5420000 rects
+caravel_00020005_fill_pattern_0_4: 5430000 rects
+caravel_00020005_fill_pattern_0_4: 5440000 rects
+caravel_00020005_fill_pattern_0_4: 5450000 rects
+caravel_00020005_fill_pattern_0_4: 5460000 rects
+caravel_00020005_fill_pattern_0_4: 5470000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_0_4
+
+caravel_00020005_fill_pattern_0_1: 4920000 rects
+caravel_00020005_fill_pattern_0_1: 4930000 rects
+caravel_00020005_fill_pattern_0_1: 4940000 rects
+caravel_00020005_fill_pattern_0_1: 4950000 rects
+caravel_00020005_fill_pattern_0_1: 4960000 rects
+caravel_00020005_fill_pattern_0_1: 4970000 rects
+caravel_00020005_fill_pattern_0_1: 4980000 rects
+caravel_00020005_fill_pattern_0_1: 4990000 rects
+caravel_00020005_fill_pattern_0_1: 5000000 rects
+caravel_00020005_fill_pattern_0_1: 5010000 rects
+caravel_00020005_fill_pattern_0_1: 5020000 rects
+caravel_00020005_fill_pattern_0_1: 5030000 rects
+caravel_00020005_fill_pattern_0_1: 5040000 rects
+caravel_00020005_fill_pattern_0_1: 5050000 rects
+caravel_00020005_fill_pattern_0_1: 5060000 rects
+caravel_00020005_fill_pattern_0_1: 5070000 rects
+caravel_00020005_fill_pattern_0_1: 5080000 rects
+caravel_00020005_fill_pattern_0_1: 5090000 rects
+caravel_00020005_fill_pattern_0_1: 5100000 rects
+caravel_00020005_fill_pattern_0_1: 5110000 rects
+caravel_00020005_fill_pattern_0_1: 5120000 rects
+caravel_00020005_fill_pattern_0_1: 5130000 rects
+caravel_00020005_fill_pattern_0_1: 5140000 rects
+caravel_00020005_fill_pattern_0_1: 5150000 rects
+caravel_00020005_fill_pattern_0_1: 5160000 rects
+caravel_00020005_fill_pattern_0_1: 5170000 rects
+caravel_00020005_fill_pattern_0_1: 5180000 rects
+caravel_00020005_fill_pattern_0_1: 5190000 rects
+caravel_00020005_fill_pattern_0_1: 5200000 rects
+caravel_00020005_fill_pattern_0_1: 5210000 rects
+caravel_00020005_fill_pattern_0_1: 5220000 rects
+caravel_00020005_fill_pattern_0_1: 5230000 rects
+caravel_00020005_fill_pattern_0_1: 5240000 rects
+caravel_00020005_fill_pattern_0_1: 5250000 rects
+caravel_00020005_fill_pattern_0_1: 5260000 rects
+caravel_00020005_fill_pattern_0_1: 5270000 rects
+caravel_00020005_fill_pattern_0_1: 5280000 rects
+caravel_00020005_fill_pattern_0_1: 5290000 rects
+caravel_00020005_fill_pattern_0_1: 5300000 rects
+caravel_00020005_fill_pattern_0_1: 5310000 rects
+caravel_00020005_fill_pattern_0_1: 5320000 rects
+caravel_00020005_fill_pattern_0_1: 5330000 rects
+caravel_00020005_fill_pattern_0_1: 5340000 rects
+caravel_00020005_fill_pattern_0_1: 5350000 rects
+caravel_00020005_fill_pattern_0_1: 5360000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_0_1
+
+   Generating output for cell caravel_00020005_fill_pattern_0_2
+
+caravel_00020005_fill_pattern_0_5: 4920000 rects
+caravel_00020005_fill_pattern_0_5: 4930000 rects
+caravel_00020005_fill_pattern_0_5: 4940000 rects
+caravel_00020005_fill_pattern_0_5: 4950000 rects
+caravel_00020005_fill_pattern_0_5: 4960000 rects
+caravel_00020005_fill_pattern_0_5: 4970000 rects
+caravel_00020005_fill_pattern_0_5: 4980000 rects
+caravel_00020005_fill_pattern_0_5: 4990000 rects
+caravel_00020005_fill_pattern_0_5: 5000000 rects
+caravel_00020005_fill_pattern_0_5: 5010000 rects
+caravel_00020005_fill_pattern_0_5: 5020000 rects
+caravel_00020005_fill_pattern_0_5: 5030000 rects
+caravel_00020005_fill_pattern_0_5: 5040000 rects
+caravel_00020005_fill_pattern_0_5: 5050000 rects
+caravel_00020005_fill_pattern_0_5: 5060000 rects
+caravel_00020005_fill_pattern_0_5: 5070000 rects
+caravel_00020005_fill_pattern_0_5: 5080000 rects
+caravel_00020005_fill_pattern_0_5: 5090000 rects
+caravel_00020005_fill_pattern_0_5: 5100000 rects
+caravel_00020005_fill_pattern_0_5: 5110000 rects
+caravel_00020005_fill_pattern_0_5: 5120000 rects
+caravel_00020005_fill_pattern_0_5: 5130000 rects
+caravel_00020005_fill_pattern_0_5: 5140000 rects
+caravel_00020005_fill_pattern_0_5: 5150000 rects
+caravel_00020005_fill_pattern_0_5: 5160000 rects
+caravel_00020005_fill_pattern_0_5: 5170000 rects
+caravel_00020005_fill_pattern_0_5: 5180000 rects
+caravel_00020005_fill_pattern_0_5: 5190000 rects
+caravel_00020005_fill_pattern_0_5: 5200000 rects
+caravel_00020005_fill_pattern_0_5: 5210000 rects
+caravel_00020005_fill_pattern_0_5: 5220000 rects
+caravel_00020005_fill_pattern_0_5: 5230000 rects
+caravel_00020005_fill_pattern_0_5: 5240000 rects
+caravel_00020005_fill_pattern_0_5: 5250000 rects
+caravel_00020005_fill_pattern_0_5: 5260000 rects
+caravel_00020005_fill_pattern_0_5: 5270000 rects
+caravel_00020005_fill_pattern_0_5: 5280000 rects
+caravel_00020005_fill_pattern_0_5: 5290000 rects
+caravel_00020005_fill_pattern_0_5: 5300000 rects
+caravel_00020005_fill_pattern_0_5: 5310000 rects
+caravel_00020005_fill_pattern_0_5: 5320000 rects
+caravel_00020005_fill_pattern_0_5: 5330000 rects
+caravel_00020005_fill_pattern_0_5: 5340000 rects
+caravel_00020005_fill_pattern_0_5: 5350000 rects
+caravel_00020005_fill_pattern_0_5: 5360000 rects
+caravel_00020005_fill_pattern_0_5: 5370000 rects
+caravel_00020005_fill_pattern_0_5: 5380000 rects
+caravel_00020005_fill_pattern_0_5: 5390000 rects
+caravel_00020005_fill_pattern_0_5: 5400000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_0_5
+
+caravel_00020005_fill_pattern_0_3: 4920000 rects
+caravel_00020005_fill_pattern_0_3: 4930000 rects
+caravel_00020005_fill_pattern_0_3: 4940000 rects
+caravel_00020005_fill_pattern_0_3: 4950000 rects
+caravel_00020005_fill_pattern_0_3: 4960000 rects
+caravel_00020005_fill_pattern_0_3: 4970000 rects
+caravel_00020005_fill_pattern_0_3: 4980000 rects
+caravel_00020005_fill_pattern_0_3: 4990000 rects
+caravel_00020005_fill_pattern_0_3: 5000000 rects
+caravel_00020005_fill_pattern_0_3: 5010000 rects
+caravel_00020005_fill_pattern_0_3: 5020000 rects
+caravel_00020005_fill_pattern_0_3: 5030000 rects
+caravel_00020005_fill_pattern_0_3: 5040000 rects
+caravel_00020005_fill_pattern_0_3: 5050000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_0_3
+
+caravel_00020005_fill_pattern_3_1: 3240000 rects
+caravel_00020005_fill_pattern_3_1: 3250000 rects
+caravel_00020005_fill_pattern_3_1: 3260000 rects
+caravel_00020005_fill_pattern_3_1: 3270000 rects
+caravel_00020005_fill_pattern_3_1: 3280000 rects
+caravel_00020005_fill_pattern_3_1: 3290000 rects
+caravel_00020005_fill_pattern_3_1: 3300000 rects
+caravel_00020005_fill_pattern_3_1: 3310000 rects
+caravel_00020005_fill_pattern_3_1: 3320000 rects
+caravel_00020005_fill_pattern_3_1: 3330000 rects
+caravel_00020005_fill_pattern_3_1: 3340000 rects
+caravel_00020005_fill_pattern_3_1: 3350000 rects
+caravel_00020005_fill_pattern_3_1: 3360000 rects
+caravel_00020005_fill_pattern_3_1: 3370000 rects
+caravel_00020005_fill_pattern_3_1: 3380000 rects
+caravel_00020005_fill_pattern_3_1: 3390000 rects
+caravel_00020005_fill_pattern_3_1: 3400000 rects
+caravel_00020005_fill_pattern_3_1: 3410000 rects
+caravel_00020005_fill_pattern_3_1: 3420000 rects
+caravel_00020005_fill_pattern_3_1: 3430000 rects
+caravel_00020005_fill_pattern_3_1: 3440000 rects
+caravel_00020005_fill_pattern_3_1: 3450000 rects
+caravel_00020005_fill_pattern_3_1: 3460000 rects
+caravel_00020005_fill_pattern_3_1: 3470000 rects
+caravel_00020005_fill_pattern_3_1: 3480000 rects
+caravel_00020005_fill_pattern_3_1: 3490000 rects
+caravel_00020005_fill_pattern_3_1: 3500000 rects
+caravel_00020005_fill_pattern_3_1: 3510000 rects
+caravel_00020005_fill_pattern_3_1: 3520000 rects
+caravel_00020005_fill_pattern_3_1: 3530000 rects
+caravel_00020005_fill_pattern_3_1: 3540000 rects
+caravel_00020005_fill_pattern_3_1: 3550000 rects
+caravel_00020005_fill_pattern_3_1: 3560000 rects
+caravel_00020005_fill_pattern_3_1: 3570000 rects
+caravel_00020005_fill_pattern_3_1: 3580000 rects
+caravel_00020005_fill_pattern_3_1: 3590000 rects
+caravel_00020005_fill_pattern_3_1: 3600000 rects
+caravel_00020005_fill_pattern_3_1: 3610000 rects
+caravel_00020005_fill_pattern_3_1: 3620000 rects
+caravel_00020005_fill_pattern_3_1: 3630000 rects
+caravel_00020005_fill_pattern_3_1: 3640000 rects
+caravel_00020005_fill_pattern_3_1: 3650000 rects
+caravel_00020005_fill_pattern_3_1: 3660000 rects
+caravel_00020005_fill_pattern_3_1: 3670000 rects
+caravel_00020005_fill_pattern_3_1: 3680000 rects
+caravel_00020005_fill_pattern_3_1: 3690000 rects
+caravel_00020005_fill_pattern_3_1: 3700000 rects
+caravel_00020005_fill_pattern_3_1: 3710000 rects
+caravel_00020005_fill_pattern_3_1: 3720000 rects
+caravel_00020005_fill_pattern_3_1: 3730000 rects
+caravel_00020005_fill_pattern_3_1: 3740000 rects
+caravel_00020005_fill_pattern_3_1: 3750000 rects
+caravel_00020005_fill_pattern_3_1: 3760000 rects
+caravel_00020005_fill_pattern_3_1: 3770000 rects
+caravel_00020005_fill_pattern_3_1: 3780000 rects
+caravel_00020005_fill_pattern_3_1: 3790000 rects
+caravel_00020005_fill_pattern_3_1: 3800000 rects
+caravel_00020005_fill_pattern_3_1: 3810000 rects
+caravel_00020005_fill_pattern_3_1: 3820000 rects
+caravel_00020005_fill_pattern_3_1: 3830000 rects
+caravel_00020005_fill_pattern_3_1: 3840000 rects
+caravel_00020005_fill_pattern_3_1: 3850000 rects
+caravel_00020005_fill_pattern_3_1: 3860000 rects
+caravel_00020005_fill_pattern_3_1: 3870000 rects
+caravel_00020005_fill_pattern_3_1: 3880000 rects
+caravel_00020005_fill_pattern_3_1: 3890000 rects
+caravel_00020005_fill_pattern_3_1: 3900000 rects
+caravel_00020005_fill_pattern_3_1: 3910000 rects
+caravel_00020005_fill_pattern_3_1: 3920000 rects
+caravel_00020005_fill_pattern_3_1: 3930000 rects
+caravel_00020005_fill_pattern_3_1: 3940000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_1
+
+caravel_00020005_fill_pattern_4_3: 3240000 rects
+caravel_00020005_fill_pattern_4_3: 3250000 rects
+caravel_00020005_fill_pattern_4_3: 3260000 rects
+caravel_00020005_fill_pattern_4_3: 3270000 rects
+caravel_00020005_fill_pattern_4_3: 3280000 rects
+caravel_00020005_fill_pattern_4_3: 3290000 rects
+caravel_00020005_fill_pattern_4_3: 3300000 rects
+caravel_00020005_fill_pattern_4_3: 3310000 rects
+caravel_00020005_fill_pattern_4_3: 3320000 rects
+caravel_00020005_fill_pattern_4_3: 3330000 rects
+caravel_00020005_fill_pattern_4_3: 3340000 rects
+caravel_00020005_fill_pattern_4_3: 3350000 rects
+caravel_00020005_fill_pattern_4_3: 3360000 rects
+caravel_00020005_fill_pattern_4_3: 3370000 rects
+caravel_00020005_fill_pattern_4_3: 3380000 rects
+caravel_00020005_fill_pattern_4_3: 3390000 rects
+caravel_00020005_fill_pattern_4_3: 3400000 rects
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+caravel_00020005_fill_pattern_4_3: 3420000 rects
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+caravel_00020005_fill_pattern_4_3: 4180000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_3
+
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+caravel_00020005_fill_pattern_4_6: 3250000 rects
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+caravel_00020005_fill_pattern_4_6: 4190000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_6
+
+caravel_00020005_fill_pattern_0_0: 4920000 rects
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+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_0_0
+
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+caravel_00020005_fill_pattern_4_2: 4150000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_2
+
+caravel_00020005_fill_pattern_4_5: 3240000 rects
+caravel_00020005_fill_pattern_4_5: 3250000 rects
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+caravel_00020005_fill_pattern_4_5: 4090000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_5
+
+caravel_00020005_fill_pattern_2_1: 3240000 rects
+caravel_00020005_fill_pattern_2_1: 3250000 rects
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+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_1
+
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+caravel_00020005_fill_pattern_3_0: 5770000 rects
+caravel_00020005_fill_pattern_3_0: 5780000 rects
+caravel_00020005_fill_pattern_3_0: 5790000 rects
+caravel_00020005_fill_pattern_3_0: 5800000 rects
+caravel_00020005_fill_pattern_3_0: 5810000 rects
+caravel_00020005_fill_pattern_3_0: 5820000 rects
+caravel_00020005_fill_pattern_3_0: 5830000 rects
+caravel_00020005_fill_pattern_3_0: 5840000 rects
+caravel_00020005_fill_pattern_3_0: 5850000 rects
+caravel_00020005_fill_pattern_3_0: 5860000 rects
+caravel_00020005_fill_pattern_3_0: 5870000 rects
+caravel_00020005_fill_pattern_3_0: 5880000 rects
+caravel_00020005_fill_pattern_3_0: 5890000 rects
+caravel_00020005_fill_pattern_3_0: 5900000 rects
+caravel_00020005_fill_pattern_3_0: 5910000 rects
+caravel_00020005_fill_pattern_3_0: 5920000 rects
+caravel_00020005_fill_pattern_3_0: 5930000 rects
+caravel_00020005_fill_pattern_3_0: 5940000 rects
+caravel_00020005_fill_pattern_3_0: 5950000 rects
+caravel_00020005_fill_pattern_3_0: 5960000 rects
+caravel_00020005_fill_pattern_3_0: 5970000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_0
+
+caravel_00020005_fill_pattern_3_2: 8280000 rects
+caravel_00020005_fill_pattern_3_2: 8290000 rects
+caravel_00020005_fill_pattern_3_2: 8300000 rects
+caravel_00020005_fill_pattern_3_2: 8310000 rects
+caravel_00020005_fill_pattern_3_2: 8320000 rects
+caravel_00020005_fill_pattern_3_2: 8330000 rects
+caravel_00020005_fill_pattern_3_2: 8340000 rects
+caravel_00020005_fill_pattern_3_2: 8350000 rects
+caravel_00020005_fill_pattern_3_2: 8360000 rects
+caravel_00020005_fill_pattern_3_2: 8370000 rects
+caravel_00020005_fill_pattern_3_2: 8380000 rects
+caravel_00020005_fill_pattern_3_2: 8390000 rects
+caravel_00020005_fill_pattern_3_2: 8400000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_2
+
+caravel_00020005_fill_pattern_4_4: 4920000 rects
+caravel_00020005_fill_pattern_4_4: 4930000 rects
+caravel_00020005_fill_pattern_4_4: 4940000 rects
+caravel_00020005_fill_pattern_4_4: 4950000 rects
+caravel_00020005_fill_pattern_4_4: 4960000 rects
+caravel_00020005_fill_pattern_4_4: 4970000 rects
+caravel_00020005_fill_pattern_4_4: 4980000 rects
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+caravel_00020005_fill_pattern_4_4: 5000000 rects
+caravel_00020005_fill_pattern_4_4: 5010000 rects
+caravel_00020005_fill_pattern_4_4: 5020000 rects
+caravel_00020005_fill_pattern_4_4: 5030000 rects
+caravel_00020005_fill_pattern_4_4: 5040000 rects
+caravel_00020005_fill_pattern_4_4: 5050000 rects
+caravel_00020005_fill_pattern_4_4: 5060000 rects
+caravel_00020005_fill_pattern_4_4: 5070000 rects
+caravel_00020005_fill_pattern_4_4: 5080000 rects
+caravel_00020005_fill_pattern_4_4: 5090000 rects
+caravel_00020005_fill_pattern_4_4: 5100000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_4
+
+caravel_00020005_fill_pattern_2_0: 4920000 rects
+caravel_00020005_fill_pattern_2_0: 4930000 rects
+caravel_00020005_fill_pattern_2_0: 4940000 rects
+caravel_00020005_fill_pattern_2_0: 4950000 rects
+caravel_00020005_fill_pattern_2_0: 4960000 rects
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+caravel_00020005_fill_pattern_2_0: 6170000 rects
+caravel_00020005_fill_pattern_2_0: 6180000 rects
+caravel_00020005_fill_pattern_2_0: 6190000 rects
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+caravel_00020005_fill_pattern_2_0: 6300000 rects
+caravel_00020005_fill_pattern_2_0: 6310000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_0
+
+caravel_00020005_fill_pattern_3_3: 9960000 rects
+caravel_00020005_fill_pattern_3_3: 9970000 rects
+caravel_00020005_fill_pattern_3_3: 9980000 rects
+caravel_00020005_fill_pattern_3_3: 9990000 rects
+caravel_00020005_fill_pattern_3_3: 10000000 rects
+caravel_00020005_fill_pattern_3_3: 10010000 rects
+caravel_00020005_fill_pattern_3_3: 10020000 rects
+caravel_00020005_fill_pattern_3_3: 10030000 rects
+caravel_00020005_fill_pattern_3_3: 10040000 rects
+caravel_00020005_fill_pattern_3_3: 10050000 rects
+caravel_00020005_fill_pattern_3_3: 10060000 rects
+caravel_00020005_fill_pattern_3_3: 10070000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_3
+
+caravel_00020005_fill_pattern_3_6: 8280000 rects
+caravel_00020005_fill_pattern_3_6: 8290000 rects
+caravel_00020005_fill_pattern_3_6: 8300000 rects
+caravel_00020005_fill_pattern_3_6: 8310000 rects
+caravel_00020005_fill_pattern_3_6: 8320000 rects
+caravel_00020005_fill_pattern_3_6: 8330000 rects
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+caravel_00020005_fill_pattern_3_6: 8460000 rects
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+caravel_00020005_fill_pattern_3_6: 9000000 rects
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+caravel_00020005_fill_pattern_3_6: 9020000 rects
+caravel_00020005_fill_pattern_3_6: 9030000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_6
+
+caravel_00020005_fill_pattern_3_5: 9960000 rects
+caravel_00020005_fill_pattern_3_5: 9970000 rects
+caravel_00020005_fill_pattern_3_5: 9980000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_5
+
+caravel_00020005_fill_pattern_2_2: 8280000 rects
+caravel_00020005_fill_pattern_2_2: 8290000 rects
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+caravel_00020005_fill_pattern_2_2: 9150000 rects
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+caravel_00020005_fill_pattern_2_2: 9230000 rects
+caravel_00020005_fill_pattern_2_2: 9240000 rects
+caravel_00020005_fill_pattern_2_2: 9250000 rects
+caravel_00020005_fill_pattern_2_2: 9260000 rects
+caravel_00020005_fill_pattern_2_2: 9270000 rects
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+caravel_00020005_fill_pattern_2_2: 9300000 rects
+caravel_00020005_fill_pattern_2_2: 9310000 rects
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+caravel_00020005_fill_pattern_2_2: 9360000 rects
+caravel_00020005_fill_pattern_2_2: 9370000 rects
+caravel_00020005_fill_pattern_2_2: 9380000 rects
+caravel_00020005_fill_pattern_2_2: 9390000 rects
+caravel_00020005_fill_pattern_2_2: 9400000 rects
+caravel_00020005_fill_pattern_2_2: 9410000 rects
+caravel_00020005_fill_pattern_2_2: 9420000 rects
+caravel_00020005_fill_pattern_2_2: 9430000 rects
+caravel_00020005_fill_pattern_2_2: 9440000 rects
+caravel_00020005_fill_pattern_2_2: 9450000 rects
+caravel_00020005_fill_pattern_2_2: 9460000 rects
+caravel_00020005_fill_pattern_2_2: 9470000 rects
+caravel_00020005_fill_pattern_2_2: 9480000 rects
+caravel_00020005_fill_pattern_2_2: 9490000 rects
+caravel_00020005_fill_pattern_2_2: 9500000 rects
+caravel_00020005_fill_pattern_2_2: 9510000 rects
+caravel_00020005_fill_pattern_2_2: 9520000 rects
+caravel_00020005_fill_pattern_2_2: 9530000 rects
+caravel_00020005_fill_pattern_2_2: 9540000 rects
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+caravel_00020005_fill_pattern_2_2: 9560000 rects
+caravel_00020005_fill_pattern_2_2: 9570000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_2
+
+caravel_00020005_fill_pattern_3_4: 9960000 rects
+caravel_00020005_fill_pattern_3_4: 9970000 rects
+caravel_00020005_fill_pattern_3_4: 9980000 rects
+caravel_00020005_fill_pattern_3_4: 9990000 rects
+caravel_00020005_fill_pattern_3_4: 10000000 rects
+caravel_00020005_fill_pattern_3_4: 10010000 rects
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+caravel_00020005_fill_pattern_3_4: 10070000 rects
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+caravel_00020005_fill_pattern_3_4: 10180000 rects
+caravel_00020005_fill_pattern_3_4: 10190000 rects
+caravel_00020005_fill_pattern_3_4: 10200000 rects
+caravel_00020005_fill_pattern_3_4: 10210000 rects
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+caravel_00020005_fill_pattern_3_4: 10230000 rects
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+caravel_00020005_fill_pattern_3_4: 10480000 rects
+caravel_00020005_fill_pattern_3_4: 10490000 rects
+caravel_00020005_fill_pattern_3_4: 10500000 rects
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+caravel_00020005_fill_pattern_3_4: 10520000 rects
+caravel_00020005_fill_pattern_3_4: 10530000 rects
+caravel_00020005_fill_pattern_3_4: 10540000 rects
+caravel_00020005_fill_pattern_3_4: 10550000 rects
+caravel_00020005_fill_pattern_3_4: 10560000 rects
+caravel_00020005_fill_pattern_3_4: 10570000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_4
+
+caravel_00020005_fill_pattern_2_6: 9960000 rects
+caravel_00020005_fill_pattern_2_6: 9970000 rects
+caravel_00020005_fill_pattern_2_6: 9980000 rects
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+caravel_00020005_fill_pattern_2_6: 10000000 rects
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+caravel_00020005_fill_pattern_2_6: 10380000 rects
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+caravel_00020005_fill_pattern_2_6: 10400000 rects
+caravel_00020005_fill_pattern_2_6: 10410000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_6
+
+caravel_00020005_fill_pattern_2_4: 11600000 rects
+caravel_00020005_fill_pattern_2_4: 11610000 rects
+caravel_00020005_fill_pattern_2_4: 11620000 rects
+caravel_00020005_fill_pattern_2_4: 11630000 rects
+caravel_00020005_fill_pattern_2_4: 11640000 rects
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+caravel_00020005_fill_pattern_2_4: 11740000 rects
+caravel_00020005_fill_pattern_2_4: 11750000 rects
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+caravel_00020005_fill_pattern_2_4: 11770000 rects
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+caravel_00020005_fill_pattern_2_4: 11790000 rects
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+caravel_00020005_fill_pattern_2_4: 12010000 rects
+caravel_00020005_fill_pattern_2_4: 12020000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_4
+
+caravel_00020005_fill_pattern_2_3: 11600000 rects
+caravel_00020005_fill_pattern_2_3: 11610000 rects
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+caravel_00020005_fill_pattern_2_3: 11870000 rects
+caravel_00020005_fill_pattern_2_3: 11880000 rects
+caravel_00020005_fill_pattern_2_3: 11890000 rects
+caravel_00020005_fill_pattern_2_3: 11900000 rects
+caravel_00020005_fill_pattern_2_3: 11910000 rects
+caravel_00020005_fill_pattern_2_3: 11920000 rects
+caravel_00020005_fill_pattern_2_3: 11930000 rects
+caravel_00020005_fill_pattern_2_3: 11940000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_3
+
+caravel_00020005_fill_pattern_1_6: 9960000 rects
+caravel_00020005_fill_pattern_1_6: 9970000 rects
+caravel_00020005_fill_pattern_1_6: 9980000 rects
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+caravel_00020005_fill_pattern_1_6: 10980000 rects
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+caravel_00020005_fill_pattern_1_6: 11000000 rects
+caravel_00020005_fill_pattern_1_6: 11010000 rects
+caravel_00020005_fill_pattern_1_6: 11020000 rects
+caravel_00020005_fill_pattern_1_6: 11030000 rects
+caravel_00020005_fill_pattern_1_6: 11040000 rects
+caravel_00020005_fill_pattern_1_6: 11050000 rects
+caravel_00020005_fill_pattern_1_6: 11060000 rects
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+caravel_00020005_fill_pattern_1_6: 11110000 rects
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+caravel_00020005_fill_pattern_1_6: 11130000 rects
+caravel_00020005_fill_pattern_1_6: 11140000 rects
+caravel_00020005_fill_pattern_1_6: 11150000 rects
+caravel_00020005_fill_pattern_1_6: 11160000 rects
+caravel_00020005_fill_pattern_1_6: 11170000 rects
+caravel_00020005_fill_pattern_1_6: 11180000 rects
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+caravel_00020005_fill_pattern_1_6: 11200000 rects
+caravel_00020005_fill_pattern_1_6: 11210000 rects
+caravel_00020005_fill_pattern_1_6: 11220000 rects
+caravel_00020005_fill_pattern_1_6: 11230000 rects
+caravel_00020005_fill_pattern_1_6: 11240000 rects
+caravel_00020005_fill_pattern_1_6: 11250000 rects
+caravel_00020005_fill_pattern_1_6: 11260000 rects
+caravel_00020005_fill_pattern_1_6: 11270000 rects
+caravel_00020005_fill_pattern_1_6: 11280000 rects
+caravel_00020005_fill_pattern_1_6: 11290000 rects
+caravel_00020005_fill_pattern_1_6: 11300000 rects
+caravel_00020005_fill_pattern_1_6: 11310000 rects
+caravel_00020005_fill_pattern_1_6: 11320000 rects
+caravel_00020005_fill_pattern_1_6: 11330000 rects
+caravel_00020005_fill_pattern_1_6: 11340000 rects
+caravel_00020005_fill_pattern_1_6: 11350000 rects
+caravel_00020005_fill_pattern_1_6: 11360000 rects
+caravel_00020005_fill_pattern_1_6: 11370000 rects
+caravel_00020005_fill_pattern_1_6: 11380000 rects
+caravel_00020005_fill_pattern_1_6: 11390000 rects
+caravel_00020005_fill_pattern_1_6: 11400000 rects
+caravel_00020005_fill_pattern_1_6: 11410000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_6
+
+caravel_00020005_fill_pattern_2_5: 11600000 rects
+caravel_00020005_fill_pattern_2_5: 11610000 rects
+caravel_00020005_fill_pattern_2_5: 11620000 rects
+caravel_00020005_fill_pattern_2_5: 11630000 rects
+caravel_00020005_fill_pattern_2_5: 11640000 rects
+caravel_00020005_fill_pattern_2_5: 11650000 rects
+caravel_00020005_fill_pattern_2_5: 11660000 rects
+caravel_00020005_fill_pattern_2_5: 11670000 rects
+caravel_00020005_fill_pattern_2_5: 11680000 rects
+caravel_00020005_fill_pattern_2_5: 11690000 rects
+caravel_00020005_fill_pattern_2_5: 11700000 rects
+caravel_00020005_fill_pattern_2_5: 11710000 rects
+caravel_00020005_fill_pattern_2_5: 11720000 rects
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+caravel_00020005_fill_pattern_2_5: 11750000 rects
+caravel_00020005_fill_pattern_2_5: 11760000 rects
+caravel_00020005_fill_pattern_2_5: 11770000 rects
+caravel_00020005_fill_pattern_2_5: 11780000 rects
+caravel_00020005_fill_pattern_2_5: 11790000 rects
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+caravel_00020005_fill_pattern_2_5: 11860000 rects
+caravel_00020005_fill_pattern_2_5: 11870000 rects
+caravel_00020005_fill_pattern_2_5: 11880000 rects
+caravel_00020005_fill_pattern_2_5: 11890000 rects
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+caravel_00020005_fill_pattern_2_5: 11910000 rects
+caravel_00020005_fill_pattern_2_5: 11920000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_5
+
+caravel_00020005_fill_pattern_1_2: 9960000 rects
+caravel_00020005_fill_pattern_1_2: 9970000 rects
+caravel_00020005_fill_pattern_1_2: 9980000 rects
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+caravel_00020005_fill_pattern_1_2: 10000000 rects
+caravel_00020005_fill_pattern_1_2: 10010000 rects
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+caravel_00020005_fill_pattern_1_2: 10190000 rects
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+caravel_00020005_fill_pattern_1_2: 10490000 rects
+caravel_00020005_fill_pattern_1_2: 10500000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_2
+
+caravel_00020005_fill_pattern_1_0: 6600000 rects
+caravel_00020005_fill_pattern_1_0: 6610000 rects
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+caravel_00020005_fill_pattern_1_0: 7540000 rects
+caravel_00020005_fill_pattern_1_0: 7550000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_0
+
+caravel_00020005_fill_pattern_1_3: 11600000 rects
+caravel_00020005_fill_pattern_1_3: 11610000 rects
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+caravel_00020005_fill_pattern_1_3: 12690000 rects
+caravel_00020005_fill_pattern_1_3: 12700000 rects
+caravel_00020005_fill_pattern_1_3: 12710000 rects
+caravel_00020005_fill_pattern_1_3: 12720000 rects
+caravel_00020005_fill_pattern_1_3: 12730000 rects
+caravel_00020005_fill_pattern_1_3: 12740000 rects
+caravel_00020005_fill_pattern_1_3: 12750000 rects
+caravel_00020005_fill_pattern_1_3: 12760000 rects
+caravel_00020005_fill_pattern_1_3: 12770000 rects
+caravel_00020005_fill_pattern_1_3: 12780000 rects
+caravel_00020005_fill_pattern_1_3: 12790000 rects
+caravel_00020005_fill_pattern_1_3: 12800000 rects
+caravel_00020005_fill_pattern_1_3: 12810000 rects
+caravel_00020005_fill_pattern_1_3: 12820000 rects
+caravel_00020005_fill_pattern_1_3: 12830000 rects
+caravel_00020005_fill_pattern_1_3: 12840000 rects
+caravel_00020005_fill_pattern_1_3: 12850000 rects
+caravel_00020005_fill_pattern_1_3: 12860000 rects
+caravel_00020005_fill_pattern_1_3: 12870000 rects
+caravel_00020005_fill_pattern_1_3: 12880000 rects
+caravel_00020005_fill_pattern_1_3: 12890000 rects
+caravel_00020005_fill_pattern_1_3: 12900000 rects
+caravel_00020005_fill_pattern_1_3: 12910000 rects
+caravel_00020005_fill_pattern_1_3: 12920000 rects
+caravel_00020005_fill_pattern_1_3: 12930000 rects
+caravel_00020005_fill_pattern_1_3: 12940000 rects
+caravel_00020005_fill_pattern_1_3: 12950000 rects
+caravel_00020005_fill_pattern_1_3: 12960000 rects
+caravel_00020005_fill_pattern_1_3: 12970000 rects
+caravel_00020005_fill_pattern_1_3: 12980000 rects
+caravel_00020005_fill_pattern_1_3: 12990000 rects
+caravel_00020005_fill_pattern_1_3: 13000000 rects
+caravel_00020005_fill_pattern_1_3: 13010000 rects
+caravel_00020005_fill_pattern_1_3: 13020000 rects
+caravel_00020005_fill_pattern_1_3: 13030000 rects
+caravel_00020005_fill_pattern_1_3: 13040000 rects
+caravel_00020005_fill_pattern_1_3: 13050000 rects
+caravel_00020005_fill_pattern_1_3: 13060000 rects
+caravel_00020005_fill_pattern_1_3: 13070000 rects
+caravel_00020005_fill_pattern_1_3: 13080000 rects
+caravel_00020005_fill_pattern_1_3: 13090000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_3
+
+caravel_00020005_fill_pattern_1_5: 11600000 rects
+caravel_00020005_fill_pattern_1_5: 11610000 rects
+caravel_00020005_fill_pattern_1_5: 11620000 rects
+caravel_00020005_fill_pattern_1_5: 11630000 rects
+caravel_00020005_fill_pattern_1_5: 11640000 rects
+caravel_00020005_fill_pattern_1_5: 11650000 rects
+caravel_00020005_fill_pattern_1_5: 11660000 rects
+caravel_00020005_fill_pattern_1_5: 11670000 rects
+caravel_00020005_fill_pattern_1_5: 11680000 rects
+caravel_00020005_fill_pattern_1_5: 11690000 rects
+caravel_00020005_fill_pattern_1_5: 11700000 rects
+caravel_00020005_fill_pattern_1_5: 11710000 rects
+caravel_00020005_fill_pattern_1_5: 11720000 rects
+caravel_00020005_fill_pattern_1_5: 11730000 rects
+caravel_00020005_fill_pattern_1_5: 11740000 rects
+caravel_00020005_fill_pattern_1_5: 11750000 rects
+caravel_00020005_fill_pattern_1_5: 11760000 rects
+caravel_00020005_fill_pattern_1_5: 11770000 rects
+caravel_00020005_fill_pattern_1_5: 11780000 rects
+caravel_00020005_fill_pattern_1_5: 11790000 rects
+caravel_00020005_fill_pattern_1_5: 11800000 rects
+caravel_00020005_fill_pattern_1_5: 11810000 rects
+caravel_00020005_fill_pattern_1_5: 11820000 rects
+caravel_00020005_fill_pattern_1_5: 11830000 rects
+caravel_00020005_fill_pattern_1_5: 11840000 rects
+caravel_00020005_fill_pattern_1_5: 11850000 rects
+caravel_00020005_fill_pattern_1_5: 11860000 rects
+caravel_00020005_fill_pattern_1_5: 11870000 rects
+caravel_00020005_fill_pattern_1_5: 11880000 rects
+caravel_00020005_fill_pattern_1_5: 11890000 rects
+caravel_00020005_fill_pattern_1_5: 11900000 rects
+caravel_00020005_fill_pattern_1_5: 11910000 rects
+caravel_00020005_fill_pattern_1_5: 11920000 rects
+caravel_00020005_fill_pattern_1_5: 11930000 rects
+caravel_00020005_fill_pattern_1_5: 11940000 rects
+caravel_00020005_fill_pattern_1_5: 11950000 rects
+caravel_00020005_fill_pattern_1_5: 11960000 rects
+caravel_00020005_fill_pattern_1_5: 11970000 rects
+caravel_00020005_fill_pattern_1_5: 11980000 rects
+caravel_00020005_fill_pattern_1_5: 11990000 rects
+caravel_00020005_fill_pattern_1_5: 12000000 rects
+caravel_00020005_fill_pattern_1_5: 12010000 rects
+caravel_00020005_fill_pattern_1_5: 12020000 rects
+caravel_00020005_fill_pattern_1_5: 12030000 rects
+caravel_00020005_fill_pattern_1_5: 12040000 rects
+caravel_00020005_fill_pattern_1_5: 12050000 rects
+caravel_00020005_fill_pattern_1_5: 12060000 rects
+caravel_00020005_fill_pattern_1_5: 12070000 rects
+caravel_00020005_fill_pattern_1_5: 12080000 rects
+caravel_00020005_fill_pattern_1_5: 12090000 rects
+caravel_00020005_fill_pattern_1_5: 12100000 rects
+caravel_00020005_fill_pattern_1_5: 12110000 rects
+caravel_00020005_fill_pattern_1_5: 12120000 rects
+caravel_00020005_fill_pattern_1_5: 12130000 rects
+caravel_00020005_fill_pattern_1_5: 12140000 rects
+caravel_00020005_fill_pattern_1_5: 12150000 rects
+caravel_00020005_fill_pattern_1_5: 12160000 rects
+caravel_00020005_fill_pattern_1_5: 12170000 rects
+caravel_00020005_fill_pattern_1_5: 12180000 rects
+caravel_00020005_fill_pattern_1_5: 12190000 rects
+caravel_00020005_fill_pattern_1_5: 12200000 rects
+caravel_00020005_fill_pattern_1_5: 12210000 rects
+caravel_00020005_fill_pattern_1_5: 12220000 rects
+caravel_00020005_fill_pattern_1_5: 12230000 rects
+caravel_00020005_fill_pattern_1_5: 12240000 rects
+caravel_00020005_fill_pattern_1_5: 12250000 rects
+caravel_00020005_fill_pattern_1_5: 12260000 rects
+caravel_00020005_fill_pattern_1_5: 12270000 rects
+caravel_00020005_fill_pattern_1_5: 12280000 rects
+caravel_00020005_fill_pattern_1_5: 12290000 rects
+caravel_00020005_fill_pattern_1_5: 12300000 rects
+caravel_00020005_fill_pattern_1_5: 12310000 rects
+caravel_00020005_fill_pattern_1_5: 12320000 rects
+caravel_00020005_fill_pattern_1_5: 12330000 rects
+caravel_00020005_fill_pattern_1_5: 12340000 rects
+caravel_00020005_fill_pattern_1_5: 12350000 rects
+caravel_00020005_fill_pattern_1_5: 12360000 rects
+caravel_00020005_fill_pattern_1_5: 12370000 rects
+caravel_00020005_fill_pattern_1_5: 12380000 rects
+caravel_00020005_fill_pattern_1_5: 12390000 rects
+caravel_00020005_fill_pattern_1_5: 12400000 rects
+caravel_00020005_fill_pattern_1_5: 12410000 rects
+caravel_00020005_fill_pattern_1_5: 12420000 rects
+caravel_00020005_fill_pattern_1_5: 12430000 rects
+caravel_00020005_fill_pattern_1_5: 12440000 rects
+caravel_00020005_fill_pattern_1_5: 12450000 rects
+caravel_00020005_fill_pattern_1_5: 12460000 rects
+caravel_00020005_fill_pattern_1_5: 12470000 rects
+caravel_00020005_fill_pattern_1_5: 12480000 rects
+caravel_00020005_fill_pattern_1_5: 12490000 rects
+caravel_00020005_fill_pattern_1_5: 12500000 rects
+caravel_00020005_fill_pattern_1_5: 12510000 rects
+caravel_00020005_fill_pattern_1_5: 12520000 rects
+caravel_00020005_fill_pattern_1_5: 12530000 rects
+caravel_00020005_fill_pattern_1_5: 12540000 rects
+caravel_00020005_fill_pattern_1_5: 12550000 rects
+caravel_00020005_fill_pattern_1_5: 12560000 rects
+caravel_00020005_fill_pattern_1_5: 12570000 rects
+caravel_00020005_fill_pattern_1_5: 12580000 rects
+caravel_00020005_fill_pattern_1_5: 12590000 rects
+caravel_00020005_fill_pattern_1_5: 12600000 rects
+caravel_00020005_fill_pattern_1_5: 12610000 rects
+caravel_00020005_fill_pattern_1_5: 12620000 rects
+caravel_00020005_fill_pattern_1_5: 12630000 rects
+caravel_00020005_fill_pattern_1_5: 12640000 rects
+caravel_00020005_fill_pattern_1_5: 12650000 rects
+caravel_00020005_fill_pattern_1_5: 12660000 rects
+caravel_00020005_fill_pattern_1_5: 12670000 rects
+caravel_00020005_fill_pattern_1_5: 12680000 rects
+caravel_00020005_fill_pattern_1_5: 12690000 rects
+caravel_00020005_fill_pattern_1_5: 12700000 rects
+caravel_00020005_fill_pattern_1_5: 12710000 rects
+caravel_00020005_fill_pattern_1_5: 12720000 rects
+caravel_00020005_fill_pattern_1_5: 12730000 rects
+caravel_00020005_fill_pattern_1_5: 12740000 rects
+caravel_00020005_fill_pattern_1_5: 12750000 rects
+caravel_00020005_fill_pattern_1_5: 12760000 rects
+caravel_00020005_fill_pattern_1_5: 12770000 rects
+caravel_00020005_fill_pattern_1_5: 12780000 rects
+caravel_00020005_fill_pattern_1_5: 12790000 rects
+caravel_00020005_fill_pattern_1_5: 12800000 rects
+caravel_00020005_fill_pattern_1_5: 12810000 rects
+caravel_00020005_fill_pattern_1_5: 12820000 rects
+caravel_00020005_fill_pattern_1_5: 12830000 rects
+caravel_00020005_fill_pattern_1_5: 12840000 rects
+caravel_00020005_fill_pattern_1_5: 12850000 rects
+caravel_00020005_fill_pattern_1_5: 12860000 rects
+caravel_00020005_fill_pattern_1_5: 12870000 rects
+caravel_00020005_fill_pattern_1_5: 12880000 rects
+caravel_00020005_fill_pattern_1_5: 12890000 rects
+caravel_00020005_fill_pattern_1_5: 12900000 rects
+caravel_00020005_fill_pattern_1_5: 12910000 rects
+caravel_00020005_fill_pattern_1_5: 12920000 rects
+caravel_00020005_fill_pattern_1_5: 12930000 rects
+caravel_00020005_fill_pattern_1_5: 12940000 rects
+caravel_00020005_fill_pattern_1_5: 12950000 rects
+caravel_00020005_fill_pattern_1_5: 12960000 rects
+caravel_00020005_fill_pattern_1_5: 12970000 rects
+caravel_00020005_fill_pattern_1_5: 12980000 rects
+caravel_00020005_fill_pattern_1_5: 12990000 rects
+caravel_00020005_fill_pattern_1_5: 13000000 rects
+caravel_00020005_fill_pattern_1_5: 13010000 rects
+caravel_00020005_fill_pattern_1_5: 13020000 rects
+caravel_00020005_fill_pattern_1_5: 13030000 rects
+caravel_00020005_fill_pattern_1_5: 13040000 rects
+caravel_00020005_fill_pattern_1_5: 13050000 rects
+caravel_00020005_fill_pattern_1_5: 13060000 rects
+caravel_00020005_fill_pattern_1_5: 13070000 rects
+caravel_00020005_fill_pattern_1_5: 13080000 rects
+caravel_00020005_fill_pattern_1_5: 13090000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_5
+Generate fill completed.
diff --git a/signoff/build/gpio_defaults.out b/signoff/build/gpio_defaults.out
new file mode 100644
index 0000000..22646d8
--- /dev/null
+++ b/signoff/build/gpio_defaults.out
@@ -0,0 +1,69 @@
+Step 1:  Create new cells for new GPIO default vectors.
+Creating new layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag
+Creating new gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Step 2:  Modify top-level layouts to use the specified defaults.
+Done.
diff --git a/signoff/build/make_ship.out b/signoff/build/make_ship.out
new file mode 100644
index 0000000..bf15c73
--- /dev/null
+++ b/signoff/build/make_ship.out
@@ -0,0 +1,3423 @@
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/mag2gds_caravel.tcl" from command line.
+Scaled magic input cell user_id_textblock geometry by factor of 2
+caravel: 10000 rects
+caravel: 20000 rects
+caravel: 30000 rects
+caravel: 40000 rects
+caravel: 50000 rects
+caravel: 60000 rects
+Processing timestamp mismatches: user_project_wrapper, user_id_programming.
+Warning:  Parent cell lists instance of "caravel_motto" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/caravel_motto.mag.
+The cell exists in the search paths at ../mag/caravel_motto.mag.
+The discovered version will be used.
+Scaled magic input cell caravel_motto geometry by factor of 2
+Warning:  Parent cell lists instance of "font_22" at bad file path ../mag/font_22.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_22.mag.
+The discovered version will be used.
+Scaled magic input cell font_22 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_73" at bad file path ../mag/font_73.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_73.mag.
+The discovered version will be used.
+Scaled magic input cell font_73 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_43" at bad file path ../mag/font_43.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_43.mag.
+The discovered version will be used.
+Scaled magic input cell font_43 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_49" at bad file path ../mag/font_49.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_49.mag.
+The discovered version will be used.
+Scaled magic input cell font_49 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_65" at bad file path ../mag/font_65.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_65.mag.
+The discovered version will be used.
+Scaled magic input cell font_65 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_68" at bad file path ../mag/font_68.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_68.mag.
+The discovered version will be used.
+Scaled magic input cell font_68 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_54" at bad file path ../mag/font_54.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_54.mag.
+The discovered version will be used.
+Scaled magic input cell font_54 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_67" at bad file path ../mag/font_67.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_67.mag.
+The discovered version will be used.
+Scaled magic input cell font_67 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_6E" at bad file path ../mag/font_6E.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_6E.mag.
+The discovered version will be used.
+Scaled magic input cell font_6E geometry by factor of 24
+Warning:  Parent cell lists instance of "font_69" at bad file path ../mag/font_69.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_69.mag.
+The discovered version will be used.
+Scaled magic input cell font_69 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_6C" at bad file path ../mag/font_6C.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_6C.mag.
+The discovered version will be used.
+Scaled magic input cell font_6C geometry by factor of 24
+Warning:  Parent cell lists instance of "font_61" at bad file path ../mag/font_61.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_61.mag.
+The discovered version will be used.
+Scaled magic input cell font_61 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_53" at bad file path ../mag/font_53.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_53.mag.
+The discovered version will be used.
+Scaled magic input cell font_53 geometry by factor of 24
+Warning:  Parent cell lists instance of "caravel_logo" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/caravel_logo.mag.
+The cell exists in the search paths at ../mag/caravel_logo.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "open_source" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/open_source.mag.
+The cell exists in the search paths at hexdigits/open_source.mag.
+The discovered version will be used.
+Scaled magic input cell open_source geometry by factor of 2
+Warning:  Parent cell lists instance of "xres_buf" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/xres_buf.mag.
+The cell exists in the search paths at ../mag/xres_buf.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__lsbufhv2lv_1" at bad file path ../mag/sky130_fd_sc_hvl__lsbufhv2lv_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__lsbufhv2lv_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__decap_8" at bad file path ../mag/sky130_fd_sc_hvl__decap_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__decap_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__diode_2" at bad file path ../mag/sky130_fd_sc_hvl__diode_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__diode_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__fill_2" at bad file path ../mag/sky130_fd_sc_hvl__fill_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__fill_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__fill_1" at bad file path ../mag/sky130_fd_sc_hvl__fill_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__fill_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__decap_4" at bad file path ../mag/sky130_fd_sc_hvl__decap_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__decap_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "alpha_0" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/hexdigits/alpha_0.mag.
+The cell exists in the search paths at hexdigits/alpha_0.mag.
+The discovered version will be used.
+Scaled magic input cell alpha_0 geometry by factor of 2
+Warning:  Parent cell lists instance of "alpha_2" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/hexdigits/alpha_2.mag.
+The cell exists in the search paths at hexdigits/alpha_2.mag.
+The discovered version will be used.
+Scaled magic input cell alpha_2 geometry by factor of 72
+Warning:  Parent cell lists instance of "alpha_5" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/hexdigits/alpha_5.mag.
+The cell exists in the search paths at hexdigits/alpha_5.mag.
+The discovered version will be used.
+Scaled magic input cell alpha_5 geometry by factor of 72
+Warning:  Parent cell lists instance of "copyright_block" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/copyright_block.mag.
+The cell exists in the search paths at ../mag/copyright_block.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "font_62" at bad file path ../mag/font_62.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_62.mag.
+The discovered version will be used.
+Scaled magic input cell font_62 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_66" at bad file path ../mag/font_66.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_66.mag.
+The discovered version will be used.
+Scaled magic input cell font_66 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_29" at bad file path ../mag/font_29.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_29.mag.
+The discovered version will be used.
+Scaled magic input cell font_29 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_20" at bad file path ../mag/font_20.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_20.mag.
+The discovered version will be used.
+Scaled magic input cell font_20 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_28" at bad file path ../mag/font_28.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_28.mag.
+The discovered version will be used.
+Scaled magic input cell font_28 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_33" at bad file path ../mag/font_33.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_33.mag.
+The discovered version will be used.
+Scaled magic input cell font_33 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_56" at bad file path ../mag/font_56.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_56.mag.
+The discovered version will be used.
+Scaled magic input cell font_56 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_76" at bad file path ../mag/font_76.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_76.mag.
+The discovered version will be used.
+Scaled magic input cell font_76 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_72" at bad file path ../mag/font_72.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_72.mag.
+The discovered version will be used.
+Scaled magic input cell font_72 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_2D" at bad file path ../mag/font_2D.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_2D.mag.
+The discovered version will be used.
+Scaled magic input cell font_2D geometry by factor of 24
+Warning:  Parent cell lists instance of "font_4B" at bad file path ../mag/font_4B.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_4B.mag.
+The discovered version will be used.
+Scaled magic input cell font_4B geometry by factor of 24
+Warning:  Parent cell lists instance of "font_44" at bad file path ../mag/font_44.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_44.mag.
+The discovered version will be used.
+Scaled magic input cell font_44 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_50" at bad file path ../mag/font_50.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_50.mag.
+The discovered version will be used.
+Scaled magic input cell font_50 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_70" at bad file path ../mag/font_70.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_70.mag.
+The discovered version will be used.
+Scaled magic input cell font_70 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_6F" at bad file path ../mag/font_6F.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_6F.mag.
+The discovered version will be used.
+Scaled magic input cell font_6F geometry by factor of 24
+Warning:  Parent cell lists instance of "font_74" at bad file path ../mag/font_74.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_74.mag.
+The discovered version will be used.
+Scaled magic input cell font_74 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_57" at bad file path ../mag/font_57.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_57.mag.
+The discovered version will be used.
+Scaled magic input cell font_57 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_6B" at bad file path ../mag/font_6B.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_6B.mag.
+The discovered version will be used.
+Scaled magic input cell font_6B geometry by factor of 24
+Warning:  Parent cell lists instance of "font_79" at bad file path ../mag/font_79.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_79.mag.
+The discovered version will be used.
+Scaled magic input cell font_79 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_47" at bad file path ../mag/font_47.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_47.mag.
+The discovered version will be used.
+Scaled magic input cell font_47 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_31" at bad file path ../mag/font_31.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_31.mag.
+The discovered version will be used.
+Scaled magic input cell font_31 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_32" at bad file path ../mag/font_32.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_32.mag.
+The discovered version will be used.
+Scaled magic input cell font_32 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_30" at bad file path ../mag/font_30.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_30.mag.
+The discovered version will be used.
+Scaled magic input cell font_30 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_6D" at bad file path ../mag/font_6D.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_6D.mag.
+The discovered version will be used.
+Scaled magic input cell font_6D geometry by factor of 24
+Warning:  Parent cell lists instance of "font_4E" at bad file path ../mag/font_4E.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_4E.mag.
+The discovered version will be used.
+Scaled magic input cell font_4E geometry by factor of 24
+Warning:  Parent cell lists instance of "caravel_clocking" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/caravel_clocking.mag.
+The cell exists in the search paths at ../mag/caravel_clocking.mag.
+The discovered version will be used.
+caravel_clocking: 10000 rects
+caravel_clocking: 20000 rects
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_1" at bad file path ../mag/sky130_fd_sc_hd__clkbuf_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor2_1" at bad file path ../mag/sky130_fd_sc_hd__nor2_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__inv_4" at bad file path ../mag/sky130_fd_sc_hd__inv_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__diode_2" at bad file path ../mag/sky130_fd_sc_hd__diode_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__diode_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__buf_2" at bad file path ../mag/sky130_fd_sc_hd__buf_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkdlybuf4s25_1" at bad file path ../mag/sky130_fd_sc_hd__clkdlybuf4s25_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkdlybuf4s25_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__mux2_1" at bad file path ../mag/sky130_fd_sc_hd__mux2_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__mux2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_2" at bad file path ../mag/sky130_fd_sc_hd__clkbuf_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__buf_1" at bad file path ../mag/sky130_fd_sc_hd__buf_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__mux2_2" at bad file path ../mag/sky130_fd_sc_hd__mux2_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__mux2_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__xor2_1" at bad file path ../mag/sky130_fd_sc_hd__xor2_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__xor2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand2_1" at bad file path ../mag/sky130_fd_sc_hd__nand2_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfstp_1" at bad file path ../mag/sky130_fd_sc_hd__dfstp_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfstp_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfrtp_1" at bad file path ../mag/sky130_fd_sc_hd__dfrtp_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfrtp_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfrtn_1" at bad file path ../mag/sky130_fd_sc_hd__dfrtn_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfrtn_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand3_1" at bad file path ../mag/sky130_fd_sc_hd__nand3_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand3_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_16" at bad file path ../mag/sky130_fd_sc_hd__clkbuf_16.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_16.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o21bai_1" at bad file path ../mag/sky130_fd_sc_hd__o21bai_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21bai_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__inv_2" at bad file path ../mag/sky130_fd_sc_hd__inv_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor3b_2" at bad file path ../mag/sky130_fd_sc_hd__nor3b_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor3b_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfrtp_4" at bad file path ../mag/sky130_fd_sc_hd__dfrtp_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfrtp_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a21bo_1" at bad file path ../mag/sky130_fd_sc_hd__a21bo_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21bo_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__buf_12" at bad file path ../mag/sky130_fd_sc_hd__buf_12.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_12.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__xnor2_1" at bad file path ../mag/sky130_fd_sc_hd__xnor2_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__xnor2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand3b_1" at bad file path ../mag/sky130_fd_sc_hd__nand3b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand3b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkinv_4" at bad file path ../mag/sky130_fd_sc_hd__clkinv_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinv_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfxtp_1" at bad file path ../mag/sky130_fd_sc_hd__dfxtp_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfxtp_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o21ai_1" at bad file path ../mag/sky130_fd_sc_hd__o21ai_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21ai_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfstp_4" at bad file path ../mag/sky130_fd_sc_hd__dfstp_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfstp_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2bb2ai_2" at bad file path ../mag/sky130_fd_sc_hd__o2bb2ai_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2bb2ai_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a21o_1" at bad file path ../mag/sky130_fd_sc_hd__a21o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o21a_1" at bad file path ../mag/sky130_fd_sc_hd__o21a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkinv_2" at bad file path ../mag/sky130_fd_sc_hd__clkinv_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinv_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand2_2" at bad file path ../mag/sky130_fd_sc_hd__nand2_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand2_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o211a_1" at bad file path ../mag/sky130_fd_sc_hd__o211a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o211a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor3_1" at bad file path ../mag/sky130_fd_sc_hd__nor3_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor3_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and2_1" at bad file path ../mag/sky130_fd_sc_hd__and2_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfrtp_2" at bad file path ../mag/sky130_fd_sc_hd__dfrtp_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfrtp_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o211ai_4" at bad file path ../mag/sky130_fd_sc_hd__o211ai_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o211ai_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or2b_1" at bad file path ../mag/sky130_fd_sc_hd__or2b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or2b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_4" at bad file path ../mag/sky130_fd_sc_hd__clkbuf_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor3b_1" at bad file path ../mag/sky130_fd_sc_hd__nor3b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor3b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dlygate4sd1_1" at bad file path ../mag/sky130_fd_sc_hd__dlygate4sd1_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dlygate4sd1_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfstp_2" at bad file path ../mag/sky130_fd_sc_hd__dfstp_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfstp_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dlymetal6s2s_1" at bad file path ../mag/sky130_fd_sc_hd__dlymetal6s2s_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dlymetal6s2s_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "housekeeping" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/housekeeping.mag.
+The cell exists in the search paths at ../mag/housekeeping.mag.
+The discovered version will be used.
+housekeeping: 10000 rects
+housekeeping: 20000 rects
+housekeeping: 30000 rects
+housekeeping: 40000 rects
+housekeeping: 50000 rects
+housekeeping: 60000 rects
+housekeeping: 70000 rects
+housekeeping: 80000 rects
+housekeeping: 90000 rects
+housekeeping: 100000 rects
+housekeeping: 110000 rects
+housekeeping: 120000 rects
+housekeeping: 130000 rects
+housekeeping: 140000 rects
+housekeeping: 150000 rects
+housekeeping: 160000 rects
+housekeeping: 170000 rects
+housekeeping: 180000 rects
+housekeeping: 190000 rects
+housekeeping: 200000 rects
+housekeeping: 210000 rects
+housekeeping: 220000 rects
+housekeeping: 230000 rects
+housekeeping: 240000 rects
+housekeeping: 250000 rects
+housekeeping: 260000 rects
+housekeeping: 270000 rects
+housekeeping: 280000 rects
+housekeeping: 290000 rects
+housekeeping: 300000 rects
+housekeeping: 310000 rects
+housekeeping: 320000 rects
+housekeeping: 330000 rects
+housekeeping: 340000 rects
+housekeeping: 350000 rects
+housekeeping: 360000 rects
+housekeeping: 370000 rects
+housekeeping: 380000 rects
+housekeeping: 390000 rects
+housekeeping: 400000 rects
+housekeeping: 410000 rects
+housekeeping: 420000 rects
+housekeeping: 430000 rects
+housekeeping: 440000 rects
+housekeeping: 450000 rects
+housekeeping: 460000 rects
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__buf_4" at bad file path ../mag/sky130_fd_sc_hd__buf_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__buf_6" at bad file path ../mag/sky130_fd_sc_hd__buf_6.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_6.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__ebufn_8" at bad file path ../mag/sky130_fd_sc_hd__ebufn_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__ebufn_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkinv_8" at bad file path ../mag/sky130_fd_sc_hd__clkinv_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinv_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__inv_6" at bad file path ../mag/sky130_fd_sc_hd__inv_6.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_6.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a221o_1" at bad file path ../mag/sky130_fd_sc_hd__a221o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a221o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4bb_1" at bad file path ../mag/sky130_fd_sc_hd__or4bb_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4bb_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or2_1" at bad file path ../mag/sky130_fd_sc_hd__or2_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4b_1" at bad file path ../mag/sky130_fd_sc_hd__or4b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a32o_2" at bad file path ../mag/sky130_fd_sc_hd__a32o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a32o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o21ai_2" at bad file path ../mag/sky130_fd_sc_hd__o21ai_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21ai_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4_2" at bad file path ../mag/sky130_fd_sc_hd__or4_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4_1" at bad file path ../mag/sky130_fd_sc_hd__or4_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand4_1" at bad file path ../mag/sky130_fd_sc_hd__nand4_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand4bb_1" at bad file path ../mag/sky130_fd_sc_hd__nand4bb_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4bb_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o22a_2" at bad file path ../mag/sky130_fd_sc_hd__o22a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o22a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a22o_1" at bad file path ../mag/sky130_fd_sc_hd__a22o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a22o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or3_1" at bad file path ../mag/sky130_fd_sc_hd__or3_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or3_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o22a_1" at bad file path ../mag/sky130_fd_sc_hd__o22a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o22a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2bb2a_1" at bad file path ../mag/sky130_fd_sc_hd__o2bb2a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2bb2a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__inv_8" at bad file path ../mag/sky130_fd_sc_hd__inv_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or3_2" at bad file path ../mag/sky130_fd_sc_hd__or3_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or3_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or3_4" at bad file path ../mag/sky130_fd_sc_hd__or3_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or3_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__mux2_8" at bad file path ../mag/sky130_fd_sc_hd__mux2_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__mux2_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__buf_8" at bad file path ../mag/sky130_fd_sc_hd__buf_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a22oi_4" at bad file path ../mag/sky130_fd_sc_hd__a22oi_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a22oi_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or3b_1" at bad file path ../mag/sky130_fd_sc_hd__or3b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or3b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a2bb2o_1" at bad file path ../mag/sky130_fd_sc_hd__a2bb2o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a2bb2o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and3_1" at bad file path ../mag/sky130_fd_sc_hd__and3_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and3_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a211o_1" at bad file path ../mag/sky130_fd_sc_hd__a211o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a211o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a21oi_1" at bad file path ../mag/sky130_fd_sc_hd__a21oi_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21oi_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or2_4" at bad file path ../mag/sky130_fd_sc_hd__or2_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or2_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4bb_4" at bad file path ../mag/sky130_fd_sc_hd__or4bb_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4bb_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand2_4" at bad file path ../mag/sky130_fd_sc_hd__nand2_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand2_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o22ai_1" at bad file path ../mag/sky130_fd_sc_hd__o22ai_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o22ai_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o32a_1" at bad file path ../mag/sky130_fd_sc_hd__o32a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o32a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or2_2" at bad file path ../mag/sky130_fd_sc_hd__or2_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or2_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a21bo_2" at bad file path ../mag/sky130_fd_sc_hd__a21bo_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21bo_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__inv_12" at bad file path ../mag/sky130_fd_sc_hd__inv_12.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_12.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o31ai_4" at bad file path ../mag/sky130_fd_sc_hd__o31ai_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o31ai_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or2b_2" at bad file path ../mag/sky130_fd_sc_hd__or2b_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or2b_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkinvlp_2" at bad file path ../mag/sky130_fd_sc_hd__clkinvlp_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinvlp_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o32a_2" at bad file path ../mag/sky130_fd_sc_hd__o32a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o32a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a311o_1" at bad file path ../mag/sky130_fd_sc_hd__a311o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a311o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and4b_1" at bad file path ../mag/sky130_fd_sc_hd__and4b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o221a_1" at bad file path ../mag/sky130_fd_sc_hd__o221a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o221a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor3_4" at bad file path ../mag/sky130_fd_sc_hd__nor3_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor3_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4_4" at bad file path ../mag/sky130_fd_sc_hd__or4_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4b_2" at bad file path ../mag/sky130_fd_sc_hd__or4b_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4b_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor2_4" at bad file path ../mag/sky130_fd_sc_hd__nor2_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor2_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a21o_2" at bad file path ../mag/sky130_fd_sc_hd__a21o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a31o_1" at bad file path ../mag/sky130_fd_sc_hd__a31o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a31o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor4_1" at bad file path ../mag/sky130_fd_sc_hd__nor4_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor4_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a32o_1" at bad file path ../mag/sky130_fd_sc_hd__a32o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a32o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__ebufn_2" at bad file path ../mag/sky130_fd_sc_hd__ebufn_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__ebufn_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand2_8" at bad file path ../mag/sky130_fd_sc_hd__nand2_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand2_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor2_2" at bad file path ../mag/sky130_fd_sc_hd__nor2_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor2_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or3b_2" at bad file path ../mag/sky130_fd_sc_hd__or3b_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or3b_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_8" at bad file path ../mag/sky130_fd_sc_hd__clkbuf_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a22oi_1" at bad file path ../mag/sky130_fd_sc_hd__a22oi_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a22oi_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o221a_2" at bad file path ../mag/sky130_fd_sc_hd__o221a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o221a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__mux2_4" at bad file path ../mag/sky130_fd_sc_hd__mux2_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__mux2_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o211a_2" at bad file path ../mag/sky130_fd_sc_hd__o211a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o211a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a41o_1" at bad file path ../mag/sky130_fd_sc_hd__a41o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a41o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o22ai_4" at bad file path ../mag/sky130_fd_sc_hd__o22ai_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o22ai_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a41o_2" at bad file path ../mag/sky130_fd_sc_hd__a41o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a41o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a311oi_1" at bad file path ../mag/sky130_fd_sc_hd__a311oi_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a311oi_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o21ba_1" at bad file path ../mag/sky130_fd_sc_hd__o21ba_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21ba_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2111ai_1" at bad file path ../mag/sky130_fd_sc_hd__o2111ai_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2111ai_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o311a_1" at bad file path ../mag/sky130_fd_sc_hd__o311a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o311a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a211o_4" at bad file path ../mag/sky130_fd_sc_hd__a211o_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a211o_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o221ai_1" at bad file path ../mag/sky130_fd_sc_hd__o221ai_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o221ai_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and3_2" at bad file path ../mag/sky130_fd_sc_hd__and3_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and3_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o31a_1" at bad file path ../mag/sky130_fd_sc_hd__o31a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o31a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o22ai_2" at bad file path ../mag/sky130_fd_sc_hd__o22ai_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o22ai_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o22a_4" at bad file path ../mag/sky130_fd_sc_hd__o22a_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o22a_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o211ai_1" at bad file path ../mag/sky130_fd_sc_hd__o211ai_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o211ai_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o221ai_2" at bad file path ../mag/sky130_fd_sc_hd__o221ai_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o221ai_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2111ai_2" at bad file path ../mag/sky130_fd_sc_hd__o2111ai_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2111ai_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand3_4" at bad file path ../mag/sky130_fd_sc_hd__nand3_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand3_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2111ai_4" at bad file path ../mag/sky130_fd_sc_hd__o2111ai_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2111ai_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and4_1" at bad file path ../mag/sky130_fd_sc_hd__and4_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2111a_1" at bad file path ../mag/sky130_fd_sc_hd__o2111a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2111a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o221ai_4" at bad file path ../mag/sky130_fd_sc_hd__o221ai_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o221ai_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor4_2" at bad file path ../mag/sky130_fd_sc_hd__nor4_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor4_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a2111o_2" at bad file path ../mag/sky130_fd_sc_hd__a2111o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a2111o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and3_4" at bad file path ../mag/sky130_fd_sc_hd__and3_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and3_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and4bb_1" at bad file path ../mag/sky130_fd_sc_hd__and4bb_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4bb_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o211ai_2" at bad file path ../mag/sky130_fd_sc_hd__o211ai_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o211ai_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and4_2" at bad file path ../mag/sky130_fd_sc_hd__and4_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2111a_2" at bad file path ../mag/sky130_fd_sc_hd__o2111a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2111a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand4_4" at bad file path ../mag/sky130_fd_sc_hd__nand4_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand4b_4" at bad file path ../mag/sky130_fd_sc_hd__nand4b_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4b_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a311oi_2" at bad file path ../mag/sky130_fd_sc_hd__a311oi_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a311oi_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a2111o_1" at bad file path ../mag/sky130_fd_sc_hd__a2111o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a2111o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor3_2" at bad file path ../mag/sky130_fd_sc_hd__nor3_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor3_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand4_2" at bad file path ../mag/sky130_fd_sc_hd__nand4_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2bb2a_2" at bad file path ../mag/sky130_fd_sc_hd__o2bb2a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2bb2a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4b_4" at bad file path ../mag/sky130_fd_sc_hd__or4b_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4b_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and3b_1" at bad file path ../mag/sky130_fd_sc_hd__and3b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and3b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a22o_2" at bad file path ../mag/sky130_fd_sc_hd__a22o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a22o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o221a_4" at bad file path ../mag/sky130_fd_sc_hd__o221a_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o221a_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or3b_4" at bad file path ../mag/sky130_fd_sc_hd__or3b_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or3b_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o21ai_4" at bad file path ../mag/sky130_fd_sc_hd__o21ai_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21ai_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor2_8" at bad file path ../mag/sky130_fd_sc_hd__nor2_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor2_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and2b_1" at bad file path ../mag/sky130_fd_sc_hd__and2b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o311a_2" at bad file path ../mag/sky130_fd_sc_hd__o311a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o311a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a31oi_1" at bad file path ../mag/sky130_fd_sc_hd__a31oi_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a31oi_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a221o_2" at bad file path ../mag/sky130_fd_sc_hd__a221o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a221o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "digital_pll" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/digital_pll.mag.
+The cell exists in the search paths at ../mag/digital_pll.mag.
+The discovered version will be used.
+digital_pll: 10000 rects
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvp_2" at bad file path ../mag/sky130_fd_sc_hd__einvp_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkinv_1" at bad file path ../mag/sky130_fd_sc_hd__clkinv_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinv_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvn_8" at bad file path ../mag/sky130_fd_sc_hd__einvn_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvn_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvn_4" at bad file path ../mag/sky130_fd_sc_hd__einvn_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvn_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o21a_2" at bad file path ../mag/sky130_fd_sc_hd__o21a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and2_2" at bad file path ../mag/sky130_fd_sc_hd__and2_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o31a_2" at bad file path ../mag/sky130_fd_sc_hd__o31a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o31a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o41a_2" at bad file path ../mag/sky130_fd_sc_hd__o41a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o41a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a31o_2" at bad file path ../mag/sky130_fd_sc_hd__a31o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a31o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvp_1" at bad file path ../mag/sky130_fd_sc_hd__einvp_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a2bb2o_2" at bad file path ../mag/sky130_fd_sc_hd__a2bb2o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a2bb2o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a311o_2" at bad file path ../mag/sky130_fd_sc_hd__a311o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a311o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a21oi_2" at bad file path ../mag/sky130_fd_sc_hd__a21oi_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21oi_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a22oi_2" at bad file path ../mag/sky130_fd_sc_hd__a22oi_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a22oi_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gpio_control_block" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_control_block.mag.
+The cell exists in the search paths at ../mag/gpio_control_block.mag.
+The discovered version will be used.
+gpio_control_block: 10000 rects
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfbbn_1" at bad file path ../mag/sky130_fd_sc_hd__dfbbn_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfbbn_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__ebufn_1" at bad file path ../mag/sky130_fd_sc_hd__ebufn_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__ebufn_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gpio_defaults_block_1803" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1803.mag.
+The cell exists in the search paths at ../mag/gpio_defaults_block_1803.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "mgmt_protect" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/mgmt_protect.mag.
+The cell exists in the search paths at ../mag/mgmt_protect.mag.
+The discovered version will be used.
+mgmt_protect: 10000 rects
+mgmt_protect: 20000 rects
+mgmt_protect: 30000 rects
+mgmt_protect: 40000 rects
+mgmt_protect: 50000 rects
+mgmt_protect: 60000 rects
+mgmt_protect: 70000 rects
+mgmt_protect: 80000 rects
+mgmt_protect: 90000 rects
+mgmt_protect: 100000 rects
+mgmt_protect: 110000 rects
+mgmt_protect: 120000 rects
+mgmt_protect: 130000 rects
+mgmt_protect: 140000 rects
+mgmt_protect: 150000 rects
+mgmt_protect: 160000 rects
+mgmt_protect: 170000 rects
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvp_4" at bad file path ../mag/sky130_fd_sc_hd__einvp_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvp_8" at bad file path ../mag/sky130_fd_sc_hd__einvp_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and2_4" at bad file path ../mag/sky130_fd_sc_hd__and2_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__conb_1" at bad file path ../mag/sky130_fd_sc_hvl__conb_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__conb_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "spare_logic_block" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/spare_logic_block.mag.
+The cell exists in the search paths at ../mag/spare_logic_block.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfbbp_1" at bad file path ../mag/sky130_fd_sc_hd__dfbbp_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfbbp_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gpio_defaults_block_0403" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_0403.mag.
+The cell exists in the search paths at ../mag/gpio_defaults_block_0403.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gpio_defaults_block" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block.mag.
+The cell exists in the search paths at ../mag/gpio_defaults_block.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "chip_io" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/chip_io.mag.
+The cell exists in the search paths at ../mag/chip_io.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__corner_pad" at bad file path ../mag/sky130_ef_io__corner_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__corner_pad.mag.
+The discovered version will be used.
+sky130_fd_io__corner_bus_overlay: 10000 rects
+Warning:  Parent cell lists instance of "sky130_ef_io__com_bus_slice_20um" at bad file path ../mag/sky130_ef_io__com_bus_slice_20um.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__com_bus_slice_20um.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__com_bus_slice_10um" at bad file path ../mag/sky130_ef_io__com_bus_slice_10um.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__com_bus_slice_10um.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__com_bus_slice_5um" at bad file path ../mag/sky130_ef_io__com_bus_slice_5um.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__com_bus_slice_5um.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__com_bus_slice_1um" at bad file path ../mag/sky130_ef_io__com_bus_slice_1um.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__com_bus_slice_1um.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um" at bad file path ../mag/sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__vssa_hvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vssa_hvc_clamped_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vssa_hvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__top_ground_hvc_wpad: 10000 rects
+sky130_fd_io__top_ground_hvc_wpad: 20000 rects
+sky130_fd_io__top_ground_hvc_wpad: 30000 rects
+sky130_fd_io__top_ground_hvc_wpad: 40000 rects
+sky130_fd_io__top_ground_hvc_wpad: 50000 rects
+sky130_fd_io__top_ground_hvc_wpad: 60000 rects
+sky130_fd_io__top_ground_hvc_wpad: 70000 rects
+sky130_fd_io__top_ground_hvc_wpad: 80000 rects
+sky130_fd_io__top_ground_hvc_wpad: 90000 rects
+sky130_fd_io__top_ground_hvc_wpad: 100000 rects
+sky130_fd_io__top_ground_hvc_wpad: 110000 rects
+sky130_fd_io__top_ground_hvc_wpad: 120000 rects
+sky130_fd_io__top_ground_hvc_wpad: 130000 rects
+sky130_fd_io__top_ground_hvc_wpad: 140000 rects
+sky130_fd_io__top_ground_hvc_wpad: 150000 rects
+sky130_fd_io__top_ground_hvc_wpad: 160000 rects
+sky130_fd_io__top_ground_hvc_wpad: 170000 rects
+sky130_fd_io__top_ground_hvc_wpad: 180000 rects
+sky130_fd_io__top_ground_hvc_wpad: 190000 rects
+sky130_fd_io__top_ground_hvc_wpad: 200000 rects
+sky130_fd_io__top_ground_hvc_wpad: 210000 rects
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_5595914180851 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808336 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808666 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808678 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808679 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_5595914180839 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808660 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808663 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s__example_55959141808671 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s2__example_55959141808672 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808662 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808661 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s__example_55959141808675 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s2__example_55959141808676 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_559591418084 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__gendlring__example_559591418081 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__genrivetdlring__example_559591418082 geometry by factor of 2
+Warning:  Parent cell lists instance of "sky130_fd_io__top_xres4v2" at bad file path ../mag/sky130_fd_io__top_xres4v2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_fd_io__top_xres4v2.mag.
+The discovered version will be used.
+sky130_fd_io__top_xres4v2: 10000 rects
+sky130_fd_io__top_xres4v2: 20000 rects
+sky130_fd_io__top_xres4v2: 30000 rects
+sky130_fd_io__top_xres4v2: 40000 rects
+sky130_fd_io__top_xres4v2: 50000 rects
+sky130_fd_io__top_xres4v2: 60000 rects
+sky130_fd_io__top_xres4v2: 70000 rects
+sky130_fd_io__top_xres4v2: 80000 rects
+sky130_fd_io__top_xres4v2: 90000 rects
+sky130_fd_io__top_xres4v2: 100000 rects
+sky130_fd_io__top_xres4v2: 110000 rects
+sky130_fd_io__top_xres4v2: 120000 rects
+sky130_fd_io__top_xres4v2: 130000 rects
+sky130_fd_io__top_xres4v2: 140000 rects
+sky130_fd_io__top_xres4v2: 150000 rects
+sky130_fd_io__top_xres4v2: 160000 rects
+sky130_fd_io__top_xres4v2: 170000 rects
+sky130_fd_io__top_xres4v2: 180000 rects
+sky130_fd_io__top_xres4v2: 190000 rects
+sky130_fd_io__top_xres4v2: 200000 rects
+sky130_fd_io__top_xres4v2: 210000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808717 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808719 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180890 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808243 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808765 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_5595914180833 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808264 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180858 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180819 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808147 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808148 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808149 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808150 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808151 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808152 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808153 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808154 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808155 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808156 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808157 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808158 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808274 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808400 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808128 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808372 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808326 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808290 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808127 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180897 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808551 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808552 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808350 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808260 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808402 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808724 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808259 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808261 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808553 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808725 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808554 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808726 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808727 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808728 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_5595914180848 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180849 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808370 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808137 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_559591418086 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_559591418083 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808385 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_559591418088 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808316 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808612 geometry by factor of 2
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 10000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 20000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 30000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 40000 rects
+Scaled magic input cell sky130_fd_pr__hvdftpm1s2__example_55959141808659 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808202 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_5595914180811 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_5595914180812 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418084 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418086 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1_centered__example_559591418081 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m2m3__example_55959141808714 geometry by factor of 2
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 10000 rects
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 20000 rects
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 30000 rects
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 40000 rects
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808187 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808700 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808559 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808338 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808337 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808729 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808730 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808731 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808732 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808733 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808734 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808735 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808736 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808737 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808738 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808739 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808740 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808273 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808741 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808742 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808743 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808744 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808324 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808745 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808746 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808747 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808748 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808749 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808270 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808750 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808751 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808752 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180857 geometry by factor of 2
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 10000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 20000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 30000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 40000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 50000 rects
+Scaled magic input cell sky130_fd_pr__hvdftpl1s__example_55959141808646 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpm1s2__example_55959141808649 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808378 geometry by factor of 2
+sky130_fd_io__xres4v2_in_buf: 10000 rects
+sky130_fd_io__xres4v2_in_buf: 20000 rects
+sky130_fd_io__xres4v2_in_buf: 30000 rects
+sky130_fd_io__xres4v2_in_buf: 40000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180827 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808233 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808237 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180829 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808242 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_5595914180835 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808782 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808452 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808449 geometry by factor of 2
+Warning:  Parent cell lists instance of "sky130_ef_io__gpiov2_pad_wrapped" at bad file path ../mag/sky130_ef_io__gpiov2_pad_wrapped.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__gpiov2_pad_wrapped.mag.
+The discovered version will be used.
+sky130_fd_io__top_gpiov2: 10000 rects
+sky130_fd_io__top_gpiov2: 20000 rects
+sky130_fd_io__top_gpiov2: 30000 rects
+sky130_fd_io__top_gpiov2: 40000 rects
+sky130_fd_io__top_gpiov2: 50000 rects
+sky130_fd_io__top_gpiov2: 60000 rects
+sky130_fd_io__top_gpiov2: 70000 rects
+sky130_fd_io__top_gpiov2: 80000 rects
+sky130_fd_io__top_gpiov2: 90000 rects
+sky130_fd_io__gpiov2_amux: 10000 rects
+sky130_fd_io__gpiov2_amux: 20000 rects
+sky130_fd_io__gpiov2_amux: 30000 rects
+sky130_fd_io__amux_switch_1v2b: 10000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808251 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfm1sd2__example_55959141808561 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808563 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180868 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180869 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180875 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808122 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808123 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180884 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808100 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180815 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180823 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808106 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808510 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808504 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808581 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808418 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808140 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808278 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808462 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_5595914180894 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808200 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfm1sd__example_55959141808258 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808476 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808115 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180816 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808178 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808488 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808306 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808517 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808518 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180811 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808190 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808191 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180812 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808280 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808425 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808102 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808434 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808440 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180878 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808394 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808298 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808373 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808272 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808271 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808374 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808194 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808294 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808322 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808395 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808396 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808397 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808295 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808398 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808399 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808325 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808292 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808269 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808401 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808368 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808625 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808633 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808320 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808321 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808323 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808291 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808143 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_5595914180854 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808275 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808276 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808293 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808296 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808297 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808299 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808300 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808266 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808267 geometry by factor of 2
+sky130_fd_io__gpio_odrvr_subv2: 10000 rects
+sky130_fd_io__gpio_odrvr_subv2: 20000 rects
+sky130_fd_io__gpio_odrvr_subv2: 30000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270v2: 10000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270v2: 20000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270v2: 30000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418082 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418083 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808655 geometry by factor of 2
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 10000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 20000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 30000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 40000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418085 geometry by factor of 2
+sky130_fd_io__gpio_pddrvr_strong_slowv2: 10000 rects
+sky130_fd_io__gpio_pddrvr_strong_slowv2: 20000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180832 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1_centered__example_559591418080 geometry by factor of 2
+Warning:  Parent cell lists instance of "sky130_ef_io__vssd_lvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vssd_lvc_clamped_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vssd_lvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__top_ground_lvc_wpad: 10000 rects
+sky130_fd_io__top_ground_lvc_wpad: 20000 rects
+sky130_fd_io__top_ground_lvc_wpad: 30000 rects
+sky130_fd_io__top_ground_lvc_wpad: 40000 rects
+sky130_fd_io__top_ground_lvc_wpad: 50000 rects
+sky130_fd_io__top_ground_lvc_wpad: 60000 rects
+sky130_fd_io__top_ground_lvc_wpad: 70000 rects
+sky130_fd_io__top_ground_lvc_wpad: 80000 rects
+sky130_fd_io__top_ground_lvc_wpad: 90000 rects
+sky130_fd_io__top_ground_lvc_wpad: 100000 rects
+sky130_fd_io__top_ground_lvc_wpad: 110000 rects
+sky130_fd_io__top_ground_lvc_wpad: 120000 rects
+sky130_fd_io__top_ground_lvc_wpad: 130000 rects
+sky130_fd_io__top_ground_lvc_wpad: 140000 rects
+sky130_fd_io__top_ground_lvc_wpad: 150000 rects
+sky130_fd_io__top_ground_lvc_wpad: 160000 rects
+sky130_fd_io__top_ground_lvc_wpad: 170000 rects
+sky130_fd_io__top_ground_lvc_wpad: 180000 rects
+sky130_fd_io__top_ground_lvc_wpad: 190000 rects
+sky130_fd_io__top_ground_lvc_wpad: 200000 rects
+sky130_fd_io__top_ground_lvc_wpad: 210000 rects
+sky130_fd_io__top_ground_lvc_wpad: 220000 rects
+Scaled magic input cell sky130_fd_io__gnd2gnd_tap geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808683 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__gnd2gnd_diff geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808684 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808685 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808686 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dftpl1s2__example_55959141808702 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808682 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dftpl1s2__example_55959141808694 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808681 geometry by factor of 2
+Warning:  Parent cell lists instance of "sky130_ef_io__vssio_hvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vssio_hvc_clamped_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vssio_hvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__overlay_vssio_hvc: 10000 rects
+Warning:  Parent cell lists instance of "sky130_ef_io__vdda_hvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vdda_hvc_clamped_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vdda_hvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__hvc_clampv2: 10000 rects
+sky130_fd_io__hvc_clampv2: 20000 rects
+sky130_fd_io__hvc_clampv2: 30000 rects
+sky130_fd_io__hvc_clampv2: 40000 rects
+sky130_fd_io__hvc_clampv2: 50000 rects
+sky130_fd_io__hvc_clampv2: 60000 rects
+sky130_fd_io__hvc_clampv2: 70000 rects
+sky130_fd_io__hvc_clampv2: 80000 rects
+sky130_fd_io__hvc_clampv2: 90000 rects
+sky130_fd_io__hvc_clampv2: 100000 rects
+sky130_fd_io__hvc_clampv2: 110000 rects
+sky130_fd_io__hvc_clampv2: 120000 rects
+sky130_fd_io__hvc_clampv2: 130000 rects
+sky130_fd_io__hvc_clampv2: 140000 rects
+sky130_fd_io__hvc_clampv2: 150000 rects
+sky130_fd_io__hvc_clampv2: 160000 rects
+sky130_fd_io__hvc_clampv2: 170000 rects
+sky130_fd_io__hvc_clampv2: 180000 rects
+sky130_fd_io__hvc_clampv2: 190000 rects
+sky130_fd_io__hvc_clampv2: 200000 rects
+sky130_fd_io__hvc_clampv2: 210000 rects
+sky130_fd_io__hvc_clampv2: 220000 rects
+sky130_fd_io__hvc_clampv2: 230000 rects
+sky130_fd_io__hvc_clampv2: 240000 rects
+sky130_fd_io__hvc_clampv2: 250000 rects
+sky130_fd_io__hvc_clampv2: 260000 rects
+sky130_fd_io__hvc_clampv2: 270000 rects
+sky130_fd_io__hvc_clampv2: 280000 rects
+Warning:  Parent cell lists instance of "sky130_ef_io__vccd_lvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vccd_lvc_clamped_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vccd_lvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__top_power_lvc_wpad: 10000 rects
+sky130_fd_io__top_power_lvc_wpad: 20000 rects
+sky130_fd_io__top_power_lvc_wpad: 30000 rects
+sky130_fd_io__top_power_lvc_wpad: 40000 rects
+sky130_fd_io__top_power_lvc_wpad: 50000 rects
+sky130_fd_io__top_power_lvc_wpad: 60000 rects
+sky130_fd_io__top_power_lvc_wpad: 70000 rects
+sky130_fd_io__top_power_lvc_wpad: 80000 rects
+sky130_fd_io__top_power_lvc_wpad: 90000 rects
+sky130_fd_io__top_power_lvc_wpad: 100000 rects
+sky130_fd_io__top_power_lvc_wpad: 110000 rects
+sky130_fd_io__top_power_lvc_wpad: 120000 rects
+sky130_fd_io__top_power_lvc_wpad: 130000 rects
+sky130_fd_io__top_power_lvc_wpad: 140000 rects
+sky130_fd_io__top_power_lvc_wpad: 150000 rects
+sky130_fd_io__top_power_lvc_wpad: 160000 rects
+sky130_fd_io__top_power_lvc_wpad: 170000 rects
+sky130_fd_io__top_power_lvc_wpad: 180000 rects
+sky130_fd_io__top_power_lvc_wpad: 190000 rects
+sky130_fd_io__top_power_lvc_wpad: 200000 rects
+sky130_fd_io__top_power_lvc_wpad: 210000 rects
+sky130_fd_io__top_power_lvc_wpad: 220000 rects
+sky130_fd_io__top_power_lvc_wpad: 230000 rects
+Warning:  Parent cell lists instance of "sky130_ef_io__disconnect_vdda_slice_5um" at bad file path ../mag/sky130_ef_io__disconnect_vdda_slice_5um.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__disconnect_vdda_slice_5um.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__vddio_hvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vddio_hvc_clamped_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vddio_hvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__overlay_vddio_hvc: 10000 rects
+Warning:  Parent cell lists instance of "sky130_ef_io__vssd_lvc_clamped3_pad" at bad file path ../mag/sky130_ef_io__vssd_lvc_clamped3_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vssd_lvc_clamped3_pad.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__vccd_lvc_clamped3_pad" at bad file path ../mag/sky130_ef_io__vccd_lvc_clamped3_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vccd_lvc_clamped3_pad.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "caravel_power_routing" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/caravel_power_routing.mag.
+The cell exists in the search paths at ../mag/caravel_power_routing.mag.
+The discovered version will be used.
+Processing timestamp mismatches: caravel_power_routing, sky130_ef_io__vccd_lvc_clamped3_pad, sky130_ef_io__vssd_lvc_clamped3_pad, sky130_ef_io__vddio_hvc_clamped_pad, sky130_ef_io__disconnect_vdda_slice_5um, sky130_ef_io__vccd_lvc_clamped_pad, sky130_ef_io__vdda_hvc_clamped_pad, sky130_ef_io__vssio_hvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped_pad, sky130_ef_io__gpiov2_pad_wrapped, sky130_fd_io__top_xres4v2, sky130_ef_io__vssa_hvc_clamped_pad, sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um, sky130_ef_io__com_bus_slice_1um, sky130_ef_io__com_bus_slice_5um, sky130_ef_io__com_bus_slice_10um, sky130_ef_io__com_bus_slice_20um, sky130_ef_io__corner_pad, gpio_defaults_block, sky130_fd_sc_hd__decap_3, sky130_fd_sc_hd__fill_1, sky130_fd_sc_hd__decap_4, sky130_fd_sc_hd__tapvpwrvgnd_1, sky130_fd_sc_hd__decap_12, sky130_fd_sc_hd__conb_1, sky130_fd_sc_hd__fill_2, sky130_fd_sc_hd__decap_6, gpio_defaults_block_0403, sky130_fd_sc_hd__dfbbp_1, spare_logic_block, sky130_fd_sc_hd__inv_2, sky130_fd_sc_hd__nand2_2, sky130_fd_sc_hd__inv_8, sky130_fd_sc_hd__decap_8, sky130_fd_sc_hd__nor2_2, sky130_fd_sc_hd__mux2_2, gpio_defaults_block_1800, sky130_fd_sc_hvl__conb_1, sky130_fd_sc_hvl__lsbufhv2lv_1, sky130_fd_sc_hvl__fill_1, sky130_fd_sc_hvl__fill_2, sky130_fd_sc_hd__and2_4, sky130_fd_sc_hd__einvp_8, sky130_fd_sc_hd__einvp_4, sky130_fd_sc_hd__clkbuf_4, sky130_fd_sc_hd__diode_2, sky130_fd_sc_hd__buf_2, sky130_fd_sc_hd__clkbuf_1, sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__and2_1, sky130_fd_sc_hd__nand2_1, sky130_fd_sc_hd__inv_6, sky130_fd_sc_hd__nand2_4, sky130_fd_sc_hd__clkinv_8, sky130_fd_sc_hd__nand2_8, sky130_fd_sc_hd__einvp_2, sky130_fd_sc_hd__clkbuf_2, sky130_fd_sc_hd__buf_6, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__clkbuf_16, sky130_fd_sc_hd__buf_12, sky130_fd_sc_hd__clkinv_4, sky130_fd_sc_hd__and2b_1, sky130_fd_sc_hd__clkinv_2, sky130_fd_sc_hd__inv_4, sky130_fd_sc_hd__inv_12, sky130_fd_sc_hd__dlymetal6s2s_1, gpio_defaults_block_1803, sky130_fd_sc_hd__ebufn_1, sky130_fd_sc_hd__dfbbn_1, gpio_control_block, sky130_fd_sc_hd__or2_1, sky130_fd_sc_hd__or2b_1, sky130_fd_sc_hd__dfrtp_1, sky130_fd_sc_hd__buf_1, sky130_fd_sc_hd__clkdlybuf4s25_1, sky130_fd_sc_hd__mux2_1, sky130_fd_sc_hd__a22oi_2, sky130_fd_sc_hd__a21oi_2, sky130_fd_sc_hd__a311o_2, sky130_fd_sc_hd__a2bb2o_2, sky130_fd_sc_hd__einvp_1, sky130_fd_sc_hd__a31o_2, sky130_fd_sc_hd__o41a_2, sky130_fd_sc_hd__o31a_2, sky130_fd_sc_hd__and2_2, sky130_fd_sc_hd__o21a_2, sky130_fd_sc_hd__einvn_4, sky130_fd_sc_hd__einvn_8, sky130_fd_sc_hd__clkinv_1, digital_pll, sky130_fd_sc_hd__o311a_2, sky130_fd_sc_hd__or2_2, sky130_fd_sc_hd__or3_2, sky130_fd_sc_hd__or4_2, sky130_fd_sc_hd__and3_2, sky130_fd_sc_hd__o21ai_2, sky130_fd_sc_hd__o32a_2, sky130_fd_sc_hd__a32o_2, sky130_fd_sc_hd__a22o_2, sky130_fd_sc_hd__o2bb2a_2, sky130_fd_sc_hd__o211a_2, sky130_fd_sc_hd__a221o_2, sky130_fd_sc_hd__o22a_2, sky130_fd_sc_hd__dfrtp_2, sky130_fd_sc_hd__o221ai_2, sky130_fd_sc_hd__o22ai_2, sky130_fd_sc_hd__o221a_2, sky130_fd_sc_hd__a21bo_2, sky130_fd_sc_hd__a21o_2, sky130_fd_sc_hd__and4_2, sky130_fd_sc_hd__o2111ai_2, sky130_fd_sc_hd__o2bb2ai_2, sky130_fd_sc_hd__a31oi_1, sky130_fd_sc_hd__nor2_8, sky130_fd_sc_hd__o21ai_4, sky130_fd_sc_hd__or3b_4, sky130_fd_sc_hd__o221a_4, sky130_fd_sc_hd__and3b_1, sky130_fd_sc_hd__or4b_4, sky130_fd_sc_hd__nand4_2, sky130_fd_sc_hd__nor3_2, sky130_fd_sc_hd__a2111o_1, sky130_fd_sc_hd__a311oi_2, sky130_fd_sc_hd__nand4b_4, sky130_fd_sc_hd__nand4_4, sky130_fd_sc_hd__o2111a_2, sky130_fd_sc_hd__o211ai_2, sky130_fd_sc_hd__and4bb_1, sky130_fd_sc_hd__and3_4, sky130_fd_sc_hd__a2111o_2, sky130_fd_sc_hd__nor4_2, sky130_fd_sc_hd__o221ai_4, sky130_fd_sc_hd__o2111a_1, sky130_fd_sc_hd__and4_1, sky130_fd_sc_hd__o2111ai_4, sky130_fd_sc_hd__nand3_4, sky130_fd_sc_hd__o211ai_1, sky130_fd_sc_hd__o22a_4, sky130_fd_sc_hd__o31a_1, sky130_fd_sc_hd__o221ai_1, sky130_fd_sc_hd__a211o_4, sky130_fd_sc_hd__o311a_1, sky130_fd_sc_hd__o2111ai_1, sky130_fd_sc_hd__o21ba_1, sky130_fd_sc_hd__a311oi_1, sky130_fd_sc_hd__a41o_2, sky130_fd_sc_hd__o22ai_4, sky130_fd_sc_hd__a41o_1, sky130_fd_sc_hd__mux2_4, sky130_fd_sc_hd__a22oi_1, sky130_fd_sc_hd__clkbuf_8, sky130_fd_sc_hd__or3b_2, sky130_fd_sc_hd__ebufn_2, sky130_fd_sc_hd__a32o_1, sky130_fd_sc_hd__nor4_1, sky130_fd_sc_hd__a31o_1, sky130_fd_sc_hd__nor2_4, sky130_fd_sc_hd__or4b_2, sky130_fd_sc_hd__or4_4, sky130_fd_sc_hd__nor3_4, sky130_fd_sc_hd__o221a_1, sky130_fd_sc_hd__and4b_1, sky130_fd_sc_hd__a311o_1, sky130_fd_sc_hd__clkinvlp_2, sky130_fd_sc_hd__or2b_2, sky130_fd_sc_hd__o31ai_4, sky130_fd_sc_hd__o32a_1, sky130_fd_sc_hd__o22ai_1, sky130_fd_sc_hd__or4bb_4, sky130_fd_sc_hd__or2_4, sky130_fd_sc_hd__a21oi_1, sky130_fd_sc_hd__a211o_1, sky130_fd_sc_hd__and3_1, sky130_fd_sc_hd__a2bb2o_1, sky130_fd_sc_hd__or3b_1, sky130_fd_sc_hd__a22oi_4, sky130_fd_sc_hd__mux2_8, sky130_fd_sc_hd__or3_4, sky130_fd_sc_hd__o2bb2a_1, sky130_fd_sc_hd__o22a_1, sky130_fd_sc_hd__or3_1, sky130_fd_sc_hd__a22o_1, sky130_fd_sc_hd__nand4bb_1, sky130_fd_sc_hd__nand4_1, sky130_fd_sc_hd__or4_1, sky130_fd_sc_hd__or4b_1, sky130_fd_sc_hd__or4bb_1, sky130_fd_sc_hd__a221o_1, sky130_fd_sc_hd__ebufn_8, housekeeping, sky130_fd_sc_hd__dfstp_1, sky130_fd_sc_hd__dfrtp_4, sky130_fd_sc_hd__dfxtp_1, sky130_fd_sc_hd__o21a_1, sky130_fd_sc_hd__nor2_1, sky130_fd_sc_hd__a21bo_1, sky130_fd_sc_hd__nor3_1, sky130_fd_sc_hd__o21ai_1, sky130_fd_sc_hd__nand3b_1, sky130_fd_sc_hd__o21bai_1, sky130_fd_sc_hd__a21o_1, sky130_fd_sc_hd__o211ai_4, sky130_fd_sc_hd__o211a_1, sky130_fd_sc_hd__dfrtn_1, sky130_fd_sc_hd__dfstp_2, sky130_fd_sc_hd__dfstp_4, sky130_fd_sc_hd__dlygate4sd1_1, sky130_fd_sc_hd__nor3b_1, sky130_fd_sc_hd__xnor2_1, sky130_fd_sc_hd__nor3b_2, sky130_fd_sc_hd__nand3_1, sky130_fd_sc_hd__xor2_1, caravel_clocking, alpha_5, alpha_2, sky130_fd_sc_hvl__decap_4, sky130_fd_sc_hvl__diode_2, sky130_fd_sc_hvl__decap_8, xres_buf, open_source, caravel_logo.
+   Generating output for cell caravel_logo
+   Generating output for cell open_source
+   Generating output for cell sky130_fd_sc_hvl__decap_8
+   Generating output for cell sky130_fd_sc_hvl__diode_2
+   Generating output for cell sky130_fd_sc_hvl__decap_4
+   Generating output for cell sky130_fd_sc_hvl__fill_2
+   Generating output for cell sky130_fd_sc_hvl__fill_1
+   Generating output for cell sky130_fd_sc_hvl__lsbufhv2lv_1
+   Generating output for cell xres_buf
+   Generating output for cell font_22
+   Generating output for cell font_73
+   Generating output for cell font_43
+   Generating output for cell font_49
+   Generating output for cell font_65
+   Generating output for cell font_68
+   Generating output for cell font_54
+   Generating output for cell font_67
+   Generating output for cell font_6E
+   Generating output for cell font_69
+   Generating output for cell font_6C
+   Generating output for cell font_61
+   Generating output for cell font_53
+   Generating output for cell caravel_motto
+   Generating output for cell alpha_2
+   Generating output for cell alpha_5
+   Generating output for cell alpha_0
+   Generating output for cell user_id_textblock
+   Generating output for cell font_62
+   Generating output for cell font_66
+   Generating output for cell font_29
+   Generating output for cell font_20
+   Generating output for cell font_28
+   Generating output for cell font_33
+   Generating output for cell font_56
+   Generating output for cell font_76
+   Generating output for cell font_72
+   Generating output for cell font_2D
+   Generating output for cell font_4B
+   Generating output for cell font_44
+   Generating output for cell font_50
+   Generating output for cell font_70
+   Generating output for cell font_6F
+   Generating output for cell font_74
+   Generating output for cell font_57
+   Generating output for cell font_6B
+   Generating output for cell font_79
+   Generating output for cell font_47
+   Generating output for cell font_31
+   Generating output for cell font_32
+   Generating output for cell font_30
+   Generating output for cell font_6D
+   Generating output for cell font_4E
+   Generating output for cell copyright_block
+   Generating output for cell sky130_fd_sc_hd__xor2_1
+   Generating output for cell sky130_fd_sc_hd__nand3_1
+   Generating output for cell sky130_fd_sc_hd__nor3b_2
+   Generating output for cell sky130_fd_sc_hd__xnor2_1
+   Generating output for cell sky130_fd_sc_hd__nor3b_1
+   Generating output for cell sky130_fd_sc_hd__dlygate4sd1_1
+   Generating output for cell sky130_fd_sc_hd__dfstp_4
+   Generating output for cell sky130_fd_sc_hd__dfstp_2
+   Generating output for cell sky130_fd_sc_hd__dfrtn_1
+   Generating output for cell sky130_fd_sc_hd__o211a_1
+   Generating output for cell sky130_fd_sc_hd__o211ai_4
+   Generating output for cell sky130_fd_sc_hd__a21o_1
+   Generating output for cell sky130_fd_sc_hd__o21bai_1
+   Generating output for cell sky130_fd_sc_hd__nand3b_1
+   Generating output for cell sky130_fd_sc_hd__o21ai_1
+   Generating output for cell sky130_fd_sc_hd__nor3_1
+   Generating output for cell sky130_fd_sc_hd__a21bo_1
+   Generating output for cell sky130_fd_sc_hd__nor2_1
+   Generating output for cell sky130_fd_sc_hd__o21a_1
+   Generating output for cell sky130_fd_sc_hd__dfxtp_1
+   Generating output for cell sky130_fd_sc_hd__dfrtp_4
+   Generating output for cell sky130_fd_sc_hd__dfstp_1
+   Generating output for cell sky130_fd_sc_hd__o2bb2ai_2
+   Generating output for cell sky130_fd_sc_hd__dfrtp_2
+   Generating output for cell sky130_fd_sc_hd__mux2_1
+   Generating output for cell sky130_fd_sc_hd__clkdlybuf4s25_1
+   Generating output for cell sky130_fd_sc_hd__buf_1
+   Generating output for cell sky130_fd_sc_hd__dfrtp_1
+   Generating output for cell sky130_fd_sc_hd__or2b_1
+   Generating output for cell sky130_fd_sc_hd__dlymetal6s2s_1
+   Generating output for cell sky130_fd_sc_hd__inv_4
+   Generating output for cell sky130_fd_sc_hd__clkinv_2
+   Generating output for cell sky130_fd_sc_hd__clkinv_4
+   Generating output for cell sky130_fd_sc_hd__buf_12
+   Generating output for cell sky130_fd_sc_hd__clkbuf_16
+   Generating output for cell sky130_fd_sc_hd__clkbuf_2
+   Generating output for cell sky130_fd_sc_hd__nand2_1
+   Generating output for cell sky130_fd_sc_hd__and2_1
+   Generating output for cell sky130_fd_sc_hd__clkbuf_1
+   Generating output for cell sky130_fd_sc_hd__buf_2
+   Generating output for cell sky130_fd_sc_hd__diode_2
+   Generating output for cell sky130_fd_sc_hd__clkbuf_4
+   Generating output for cell sky130_fd_sc_hd__mux2_2
+   Generating output for cell sky130_fd_sc_hd__decap_8
+   Generating output for cell sky130_fd_sc_hd__nand2_2
+   Generating output for cell sky130_fd_sc_hd__inv_2
+   Generating output for cell sky130_fd_sc_hd__decap_6
+   Generating output for cell sky130_fd_sc_hd__fill_2
+   Generating output for cell sky130_fd_sc_hd__conb_1
+   Generating output for cell sky130_fd_sc_hd__decap_12
+   Generating output for cell sky130_fd_sc_hd__tapvpwrvgnd_1
+   Generating output for cell sky130_fd_sc_hd__decap_4
+   Generating output for cell sky130_fd_sc_hd__fill_1
+   Generating output for cell sky130_fd_sc_hd__decap_3
+   Generating output for cell caravel_clocking
+   Generating output for cell sky130_fd_sc_hd__ebufn_8
+   Generating output for cell sky130_fd_sc_hd__a221o_1
+   Generating output for cell sky130_fd_sc_hd__or4bb_1
+   Generating output for cell sky130_fd_sc_hd__or4b_1
+   Generating output for cell sky130_fd_sc_hd__or4_1
+   Generating output for cell sky130_fd_sc_hd__nand4_1
+   Generating output for cell sky130_fd_sc_hd__nand4bb_1
+   Generating output for cell sky130_fd_sc_hd__a22o_1
+   Generating output for cell sky130_fd_sc_hd__or3_1
+   Generating output for cell sky130_fd_sc_hd__o22a_1
+   Generating output for cell sky130_fd_sc_hd__o2bb2a_1
+   Generating output for cell sky130_fd_sc_hd__or3_4
+   Generating output for cell sky130_fd_sc_hd__mux2_8
+   Generating output for cell sky130_fd_sc_hd__a22oi_4
+   Generating output for cell sky130_fd_sc_hd__or3b_1
+   Generating output for cell sky130_fd_sc_hd__a2bb2o_1
+   Generating output for cell sky130_fd_sc_hd__and3_1
+   Generating output for cell sky130_fd_sc_hd__a211o_1
+   Generating output for cell sky130_fd_sc_hd__a21oi_1
+   Generating output for cell sky130_fd_sc_hd__or2_4
+   Generating output for cell sky130_fd_sc_hd__or4bb_4
+   Generating output for cell sky130_fd_sc_hd__o22ai_1
+   Generating output for cell sky130_fd_sc_hd__o32a_1
+   Generating output for cell sky130_fd_sc_hd__o31ai_4
+   Generating output for cell sky130_fd_sc_hd__or2b_2
+   Generating output for cell sky130_fd_sc_hd__clkinvlp_2
+   Generating output for cell sky130_fd_sc_hd__a311o_1
+   Generating output for cell sky130_fd_sc_hd__and4b_1
+   Generating output for cell sky130_fd_sc_hd__o221a_1
+   Generating output for cell sky130_fd_sc_hd__nor3_4
+   Generating output for cell sky130_fd_sc_hd__or4_4
+   Generating output for cell sky130_fd_sc_hd__or4b_2
+   Generating output for cell sky130_fd_sc_hd__nor2_4
+   Generating output for cell sky130_fd_sc_hd__a31o_1
+   Generating output for cell sky130_fd_sc_hd__nor4_1
+   Generating output for cell sky130_fd_sc_hd__a32o_1
+   Generating output for cell sky130_fd_sc_hd__ebufn_2
+   Generating output for cell sky130_fd_sc_hd__or3b_2
+   Generating output for cell sky130_fd_sc_hd__clkbuf_8
+   Generating output for cell sky130_fd_sc_hd__a22oi_1
+   Generating output for cell sky130_fd_sc_hd__mux2_4
+   Generating output for cell sky130_fd_sc_hd__a41o_1
+   Generating output for cell sky130_fd_sc_hd__o22ai_4
+   Generating output for cell sky130_fd_sc_hd__a41o_2
+   Generating output for cell sky130_fd_sc_hd__a311oi_1
+   Generating output for cell sky130_fd_sc_hd__o21ba_1
+   Generating output for cell sky130_fd_sc_hd__o2111ai_1
+   Generating output for cell sky130_fd_sc_hd__o311a_1
+   Generating output for cell sky130_fd_sc_hd__a211o_4
+   Generating output for cell sky130_fd_sc_hd__o221ai_1
+   Generating output for cell sky130_fd_sc_hd__o31a_1
+   Generating output for cell sky130_fd_sc_hd__o22a_4
+   Generating output for cell sky130_fd_sc_hd__o211ai_1
+   Generating output for cell sky130_fd_sc_hd__nand3_4
+   Generating output for cell sky130_fd_sc_hd__o2111ai_4
+   Generating output for cell sky130_fd_sc_hd__and4_1
+   Generating output for cell sky130_fd_sc_hd__o2111a_1
+   Generating output for cell sky130_fd_sc_hd__o221ai_4
+   Generating output for cell sky130_fd_sc_hd__nor4_2
+   Generating output for cell sky130_fd_sc_hd__a2111o_2
+   Generating output for cell sky130_fd_sc_hd__and3_4
+   Generating output for cell sky130_fd_sc_hd__and4bb_1
+   Generating output for cell sky130_fd_sc_hd__o211ai_2
+   Generating output for cell sky130_fd_sc_hd__o2111a_2
+   Generating output for cell sky130_fd_sc_hd__nand4_4
+   Generating output for cell sky130_fd_sc_hd__nand4b_4
+   Generating output for cell sky130_fd_sc_hd__a311oi_2
+   Generating output for cell sky130_fd_sc_hd__a2111o_1
+   Generating output for cell sky130_fd_sc_hd__nor3_2
+   Generating output for cell sky130_fd_sc_hd__nand4_2
+   Generating output for cell sky130_fd_sc_hd__or4b_4
+   Generating output for cell sky130_fd_sc_hd__and3b_1
+   Generating output for cell sky130_fd_sc_hd__o221a_4
+   Generating output for cell sky130_fd_sc_hd__or3b_4
+   Generating output for cell sky130_fd_sc_hd__o21ai_4
+   Generating output for cell sky130_fd_sc_hd__nor2_8
+   Generating output for cell sky130_fd_sc_hd__a31oi_1
+   Generating output for cell sky130_fd_sc_hd__o2111ai_2
+   Generating output for cell sky130_fd_sc_hd__and4_2
+   Generating output for cell sky130_fd_sc_hd__a21o_2
+   Generating output for cell sky130_fd_sc_hd__a21bo_2
+   Generating output for cell sky130_fd_sc_hd__o221a_2
+   Generating output for cell sky130_fd_sc_hd__o22ai_2
+   Generating output for cell sky130_fd_sc_hd__o221ai_2
+   Generating output for cell sky130_fd_sc_hd__o22a_2
+   Generating output for cell sky130_fd_sc_hd__a221o_2
+   Generating output for cell sky130_fd_sc_hd__o211a_2
+   Generating output for cell sky130_fd_sc_hd__o2bb2a_2
+   Generating output for cell sky130_fd_sc_hd__a22o_2
+   Generating output for cell sky130_fd_sc_hd__a32o_2
+   Generating output for cell sky130_fd_sc_hd__o32a_2
+   Generating output for cell sky130_fd_sc_hd__o21ai_2
+   Generating output for cell sky130_fd_sc_hd__and3_2
+   Generating output for cell sky130_fd_sc_hd__or4_2
+   Generating output for cell sky130_fd_sc_hd__or3_2
+   Generating output for cell sky130_fd_sc_hd__or2_2
+   Generating output for cell sky130_fd_sc_hd__o311a_2
+   Generating output for cell sky130_fd_sc_hd__or2_1
+   Generating output for cell sky130_fd_sc_hd__inv_12
+   Generating output for cell sky130_fd_sc_hd__and2b_1
+   Generating output for cell sky130_fd_sc_hd__buf_8
+   Generating output for cell sky130_fd_sc_hd__buf_6
+   Generating output for cell sky130_fd_sc_hd__nand2_8
+   Generating output for cell sky130_fd_sc_hd__clkinv_8
+   Generating output for cell sky130_fd_sc_hd__nand2_4
+   Generating output for cell sky130_fd_sc_hd__inv_6
+   Generating output for cell sky130_fd_sc_hd__buf_4
+   Generating output for cell sky130_fd_sc_hd__nor2_2
+   Generating output for cell sky130_fd_sc_hd__inv_8
+   Generating output for cell housekeeping
+   Generating output for cell sky130_fd_sc_hd__clkinv_1
+   Generating output for cell sky130_fd_sc_hd__einvn_8
+   Generating output for cell sky130_fd_sc_hd__einvn_4
+   Generating output for cell sky130_fd_sc_hd__o21a_2
+   Generating output for cell sky130_fd_sc_hd__and2_2
+   Generating output for cell sky130_fd_sc_hd__o31a_2
+   Generating output for cell sky130_fd_sc_hd__o41a_2
+   Generating output for cell sky130_fd_sc_hd__a31o_2
+   Generating output for cell sky130_fd_sc_hd__einvp_1
+   Generating output for cell sky130_fd_sc_hd__a2bb2o_2
+   Generating output for cell sky130_fd_sc_hd__a311o_2
+   Generating output for cell sky130_fd_sc_hd__a21oi_2
+   Generating output for cell sky130_fd_sc_hd__a22oi_2
+   Generating output for cell sky130_fd_sc_hd__einvp_2
+   Generating output for cell digital_pll
+   Generating output for cell sky130_fd_sc_hd__dfbbn_1
+   Generating output for cell sky130_fd_sc_hd__ebufn_1
+   Generating output for cell gpio_logic_high
+   Generating output for cell gpio_control_block
+   Generating output for cell gpio_defaults_block_1803
+   Generating output for cell simple_por
+Reading "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "sky130_fd_sc_hvl__schmittbuf_1".
+Reading "sky130_fd_sc_hvl__buf_8".
+Reading "sky130_fd_sc_hvl__fill_4".
+Reading "sky130_fd_sc_hvl__inv_8".
+Reading "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "simple_por".
+   Generating output for cell user_id_programming
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "user_id_programming".
+   Generating output for cell mgmt_core_wrapper
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__ebufn_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__inv_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "DFFRAM".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__a41oi_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__o41ai_1".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__o2111a_4".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__nor2b_2".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__a32oi_2".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__nor2b_4".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__o311ai_1".
+Reading "sky130_fd_sc_hd__a41oi_2".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__clkinv_16".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__o311ai_4".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__a221oi_2".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__a32oi_1".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__o311ai_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__o41ai_4".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_4".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__a2bb2oi_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__o32ai_4".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+Reading "sky130_fd_sc_hd__inv_16".
+Reading "sky130_fd_sc_hd__o41ai_2".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "mgmt_core".
+Reading "mgmt_core_wrapper".
+   Generating output for cell gpio_defaults_block_1800
+   Generating output for cell sky130_fd_sc_hd__dfbbp_1
+   Generating output for cell spare_logic_block
+   Generating output for cell sky130_fd_sc_hd__einvp_4
+   Generating output for cell sky130_fd_sc_hd__einvp_8
+   Generating output for cell sky130_fd_sc_hd__and2_4
+   Generating output for cell sky130_fd_sc_hvl__conb_1
+   Generating output for cell mgmt_protect_hv
+   Generating output for cell mprj_logic_high
+   Generating output for cell mprj2_logic_high
+   Generating output for cell mgmt_protect
+   Generating output for cell gpio_defaults_block_0403
+   Generating output for cell gpio_defaults_block
+   Generating output for cell gpio_control_power_routing_right
+   Generating output for cell gpio_control_power_routing_top
+   Generating output for cell gpio_control_power_routing
+   Generating output for cell caravel_power_routing
+   Generating output for cell sky130_fd_io__corner_bus_overlay
+   Generating output for cell sky130_ef_io__corner_pad
+   Generating output for cell sky130_ef_io__com_bus_slice_20um
+   Generating output for cell sky130_ef_io__com_bus_slice_10um
+   Generating output for cell sky130_ef_io__com_bus_slice_5um
+   Generating output for cell sky130_ef_io__com_bus_slice_1um
+   Generating output for cell sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um
+   Generating output for cell sky130_ef_io__hvc_vdda_overlay
+   Generating output for cell sky130_fd_io__com_bus_slice
+   Generating output for cell sky130_fd_io__com_bus_hookup
+   Generating output for cell sky130_fd_io__overlay_vssa_hvc
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_5595914180851
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808664
+   Generating output for cell sky130_fd_io__sio_clamp_pcap_4x5
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808680
+   Generating output for cell sky130_fd_io__esd_rcclamp_nfetcap
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808336
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808666
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808665
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808678
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808679
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808677
+   Generating output for cell sky130_fd_pr__via_pol1__example_5595914180839
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808667
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808660
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808663
+   Generating output for cell sky130_fd_pr__hvdftpl1s__example_55959141808671
+   Generating output for cell sky130_fd_pr__hvdftpl1s2__example_55959141808672
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808673
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808668
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808670
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808662
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808661
+   Generating output for cell sky130_fd_pr__hvdftpl1s__example_55959141808675
+   Generating output for cell sky130_fd_pr__hvdftpl1s2__example_55959141808676
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808674
+   Generating output for cell sky130_fd_pr__via_l1m1__example_559591418084
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808669
+   Generating output for cell sky130_fd_pr__gendlring__example_559591418081
+   Generating output for cell sky130_fd_pr__genrivetdlring__example_559591418082
+   Generating output for cell sky130_fd_pr__padplhp__example_559591418080
+   Generating output for cell sky130_fd_io__pad_esd
+   Generating output for cell sky130_fd_io__com_busses_esd
+   Generating output for cell sky130_fd_io__top_ground_hvc_wpad
+   Generating output for cell sky130_ef_io__vssa_hvc_clamped_pad
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808717
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808716
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808719
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808718
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808720
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180890
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808721
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808243
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808722
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808723
+   Generating output for cell sky130_fd_io__xres_inv_hysv2
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180838
+   Generating output for cell sky130_fd_io__tk_tie_r_out_esd
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808765
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808764
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808767
+   Generating output for cell sky130_fd_io__res250_sub_small
+   Generating output for cell sky130_fd_io__res250only_small
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808289
+   Generating output for cell sky130_fd_pr__via_pol1__example_5595914180833
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808715
+   Generating output for cell sky130_fd_pr__res_bent_po__example_5595914180862
+   Generating output for cell sky130_fd_pr__res_bent_po__example_5595914180863
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_55959141808288
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180859
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180864
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808264
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180858
+   Generating output for cell sky130_fd_io__com_res_weak_v2
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180819
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808555
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808147
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808148
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808149
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808150
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808151
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808152
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808153
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808154
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808155
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808156
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808157
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808158
+   Generating output for cell sky130_fd_io__signal_5_sym_hv_local_5term
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808274
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808400
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808128
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808372
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808326
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808290
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808127
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180897
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808551
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808552
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808350
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808260
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808402
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808724
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808259
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808261
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808553
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808725
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808554
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808726
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808727
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808728
+   Generating output for cell sky130_fd_io__gpio_buf_localesdv2
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_5595914180848
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180849
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808766
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808370
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808369
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808137
+   Generating output for cell sky130_fd_pr__dfl1sd__example_559591418086
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808371
+   Generating output for cell sky130_fd_pr__via_pol1__example_559591418083
+   Generating output for cell sky130_fd_io__hvsbt_inv_x1
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808385
+   Generating output for cell sky130_fd_pr__dfl1sd__example_559591418088
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808615
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808316
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808616
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808612
+   Generating output for cell sky130_fd_io__hvsbt_inv_x4
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808422
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808421
+   Generating output for cell sky130_fd_io__hvsbt_inv_x2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808657
+   Generating output for cell sky130_fd_pr__hvdftpm1s2__example_55959141808659
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808658
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808202
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_5595914180811
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_5595914180812
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418084
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418086
+   Generating output for cell sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2
+   Generating output for cell sky130_fd_io__tk_em2o_cdns_55959141808653
+   Generating output for cell sky130_fd_io__tk_em2s_cdns_55959141808652
+   Generating output for cell sky130_fd_pr__via_pol1_centered__example_559591418081
+   Generating output for cell sky130_fd_io__gpio_pudrvr_strong_axres4v2
+   Generating output for cell sky130_fd_pr__via_m2m3__example_55959141808714
+   Generating output for cell sky130_fd_io__xres_p_em1c_cdns_55959141808753
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808187
+   Generating output for cell sky130_fd_pr__res_generic_nd__example_55959141808754
+   Generating output for cell sky130_fd_pr__res_generic_nd__example_55959141808755
+   Generating output for cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756
+   Generating output for cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757
+   Generating output for cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758
+   Generating output for cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759
+   Generating output for cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760
+   Generating output for cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808700
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808559
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808762
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808338
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808337
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808763
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808729
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808730
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808731
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808732
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808733
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808734
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808735
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808736
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808737
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808738
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808739
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808740
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808273
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808741
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808742
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808743
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808744
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808324
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808745
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808746
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808747
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808748
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808749
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808270
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808750
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808751
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808752
+   Generating output for cell sky130_fd_io__xres2v2_rcfilter_lpfv2
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_5595914180860
+   Generating output for cell sky130_fd_pr__res_bent_po__example_5595914180861
+   Generating output for cell sky130_fd_io__com_res_weak_bentbigres
+   Generating output for cell sky130_fd_io__com_res_weak
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180857
+   Generating output for cell sky130_fd_pr__hvdftpl1s__example_55959141808646
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808645
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808647
+   Generating output for cell sky130_fd_pr__hvdftpm1s2__example_55959141808649
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808648
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808650
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808651
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808378
+   Generating output for cell sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2
+   Generating output for cell sky130_fd_io__gpio_pddrvr_strong_xres4v2
+   Generating output for cell sky130_fd_io__top_gpio_pad
+   Generating output for cell sky130_fd_io__com_busses
+   Generating output for cell sky130_fd_io__tap_1
+   Generating output for cell sky130_fd_io__inv_1
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808768
+   Generating output for cell sky130_fd_pr__res_bent_nd__example_55959141808769
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_559591418085
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_559591418087
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_559591418089
+   Generating output for cell sky130_fd_io__hvsbt_nand2
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180827
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808770
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808233
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808771
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808237
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180829
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808772
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808773
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808242
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808774
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808775
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808776
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_5595914180835
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808777
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808778
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808779
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808780
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808782
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808781
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808452
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808783
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808449
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808784
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808785
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808786
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808787
+   Generating output for cell sky130_fd_io__xres4v2_in_buf
+   Generating output for cell sky130_fd_io__top_xres4v2
+   Generating output for cell sky130_fd_io__com_bus_slice_m4
+   Generating output for cell sky130_fd_io__overlay_gpiov2_m4
+   Generating output for cell sky130_fd_io__overlay_gpiov2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808558
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808251
+   Generating output for cell sky130_fd_pr__dfm1sd2__example_55959141808561
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808560
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808563
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808562
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808564
+   Generating output for cell sky130_fd_io__amux_switch_1v2b
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180868
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180869
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808565
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180875
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808566
+   Generating output for cell sky130_fd_io__gpiov2_amx_pucsd_inv
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808567
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808122
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808123
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808477
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808568
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180884
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808569
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808100
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180815
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808570
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr_lshv2hv2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808571
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808441
+   Generating output for cell sky130_fd_io__gpiov2_amx_inv4
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr_lshv2hv
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180823
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808572
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808573
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808106
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808574
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808510
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808575
+   Generating output for cell sky130_fd_io__amx_inv1
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808576
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808504
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808577
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808578
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808579
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808581
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808418
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808580
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808140
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808496
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808497
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808278
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808462
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808582
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808583
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808498
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr_ls
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr
+   Generating output for cell sky130_fd_io__xor2_1
+   Generating output for cell sky130_fd_io__nand2_1
+   Generating output for cell sky130_fd_io__nor2_1
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808419
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808420
+   Generating output for cell sky130_fd_io__hvsbt_nor
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_5595914180894
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808584
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808455
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808445
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808447
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808248
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808200
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808457
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808450
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808451
+   Generating output for cell sky130_fd_io__gpiov2_amux_nand5
+   Generating output for cell sky130_fd_pr__dfm1sd__example_55959141808258
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808585
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808446
+   Generating output for cell sky130_fd_io__gpiov2_amux_nand4
+   Generating output for cell sky130_fd_io__gpiov2_amux_decoder
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808586
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808587
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808476
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808588
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808475
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808115
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808589
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_lshv2hv2
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_lshv2hv
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808460
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808590
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180816
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808463
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808464
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808465
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808466
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808467
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808468
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_ls
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_inv_1
+   Generating output for cell sky130_fd_io__gpiov2_amux_ls
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_logic
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808178
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808591
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808488
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808592
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808306
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808593
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808594
+   Generating output for cell sky130_fd_io__res75only_small
+   Generating output for cell sky130_fd_io__gpiov2_amux
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808608
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808517
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808533
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808230
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808529
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808518
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808609
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808604
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808610
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180811
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808549
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808190
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808548
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808611
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808191
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808189
+   Generating output for cell sky130_fd_io__gpiov2_in_buf
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808481
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808537
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808600
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808528
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808550
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808607
+   Generating output for cell sky130_fd_io__gpiov2_ipath_hvls
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808601
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_5595914180825
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808602
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808603
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808527
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808535
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808540
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808598
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808605
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808596
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808606
+   Generating output for cell sky130_fd_io__gpiov2_vcchib_in_buf
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180812
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808597
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808599
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808546
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808547
+   Generating output for cell sky130_fd_io__gpiov2_ipath_lvls
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808595
+   Generating output for cell sky130_fd_io__gpiov2_inbuf_lvinv_x1
+   Generating output for cell sky130_fd_io__gpiov2_ibuf_se
+   Generating output for cell sky130_fd_io__gpiov2_buf_localesd
+   Generating output for cell sky130_fd_io__hvsbt_nand2v2
+   Generating output for cell sky130_fd_io__gpiov2_ictl_logic
+   Generating output for cell sky130_fd_io__gpiov2_ipath
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808613
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808614
+   Generating output for cell sky130_fd_io__hvsbt_inv_x8v2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808423
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808280
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808425
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808424
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808426
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808379
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808380
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808382
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808383
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808427
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808428
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808429
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808430
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808102
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808431
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808432
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808434
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808433
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808435
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808440
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180878
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808394
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808298
+   Generating output for cell sky130_fd_io__com_ctl_ls
+   Generating output for cell sky130_fd_io__hvsbt_inv_x8
+   Generating output for cell sky130_fd_io__com_ctl_hldv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808617
+   Generating output for cell sky130_fd_io__com_ctl_ls_en_1_v2
+   Generating output for cell sky130_fd_io__com_ctl_ls_v2
+   Generating output for cell sky130_fd_io__tk_em2o_cdns_55959141808439
+   Generating output for cell sky130_fd_io__tk_em2s_cdns_55959141808438
+   Generating output for cell sky130_fd_io__com_ctl_ls_1v2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_5595914180813
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_5595914180822
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808618
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808619
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808620
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808621
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808622
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808623
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808116
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808624
+   Generating output for cell sky130_fd_io__com_ctl_lsv2
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_5595914180880
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_5595914180879
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180882
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180881
+   Generating output for cell sky130_fd_io__gpiov2_ctl_lsbank
+   Generating output for cell sky130_fd_io__gpiov2_ctl
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808375
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808376
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808377
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808381
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808384
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808386
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808387
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808388
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808389
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808390
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808391
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808392
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808393
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808373
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808272
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808271
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808374
+   Generating output for cell sky130_fd_io__gpio_dat_ls_1v2
+   Generating output for cell sky130_fd_io__gpio_dat_lsv2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808360
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808403
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808362
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808404
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808405
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808406
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808194
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808346
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808407
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808408
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808409
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808410
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808294
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808322
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808395
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808396
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808397
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808295
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808398
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808399
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808325
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808292
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808269
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808401
+   Generating output for cell sky130_fd_io__com_cclat
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808368
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808625
+   Generating output for cell sky130_fd_io__com_opath_datoev2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808416
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808417
+   Generating output for cell sky130_fd_io__hvsbt_xor
+   Generating output for cell sky130_fd_io__hvsbt_xorv2
+   Generating output for cell sky130_fd_io__com_ctl_ls_octl
+   Generating output for cell sky130_fd_io__gpiov2_octl
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808354
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808626
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808627
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808628
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808629
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808630
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808631
+   Generating output for cell sky130_fd_io__gpiov2_pdpredrvr_strong_nr2
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808633
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808632
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808634
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808635
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808636
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808637
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808638
+   Generating output for cell sky130_fd_io__gpiov2_pdpredrvr_strong_nr3
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808327
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808328
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808329
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808330
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808304
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808331
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808134
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808332
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808333
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808334
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808343
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808344
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808345
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808347
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808348
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808639
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808640
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808641
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808320
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808321
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808323
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808291
+   Generating output for cell sky130_fd_io__com_pdpredrvr_pbiasv2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_5595914180888
+   Generating output for cell sky130_fd_io__gpiov2_octl_mux
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808642
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808141
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808184
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808643
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808183
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808139
+   Generating output for cell sky130_fd_io__gpiov2_pdpredrvr_strong
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808143
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808364
+   Generating output for cell sky130_fd_io__com_pdpredrvr_strong_slowv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808363
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808314
+   Generating output for cell sky130_fd_pr__via_pol1__example_5595914180854
+   Generating output for cell sky130_fd_io__com_pupredrvr_strong_slowv2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808644
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808281
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808282
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808287
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808283
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808284
+   Generating output for cell sky130_fd_pr__res_generic_po__example_55959141808285
+   Generating output for cell sky130_fd_pr__res_generic_po__example_55959141808286
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808275
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808276
+   Generating output for cell sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a
+   Generating output for cell sky130_fd_io__gpiov2_pupredrvr_strong_nd2
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_55959141808301
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808302
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808303
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808305
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808307
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808308
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808309
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808310
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808311
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808312
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808313
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808315
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808317
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808318
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808319
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808293
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808296
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808297
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808299
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808300
+   Generating output for cell sky130_fd_io__feascom_pupredrvr_nbiasv2
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808144
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_5595914180899
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808142
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808101
+   Generating output for cell sky130_fd_io__gpio_pupredrvr_strongv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808365
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808366
+   Generating output for cell sky130_fd_io__com_pdpredrvr_weakv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808361
+   Generating output for cell sky130_fd_io__feas_com_pupredrvr_weak
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808266
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808267
+   Generating output for cell sky130_fd_io__gpiov2_obpredrvr
+   Generating output for cell sky130_fd_io__gpiov2_octl_dat
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418082
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418083
+   Generating output for cell sky130_fd_io__nfet_con_diff_wo_abt_270v2
+   Generating output for cell sky130_fd_io__gpiov2_pddrvr_strong
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808655
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808654
+   Generating output for cell sky130_fd_io__com_pudrvr_strong_slowv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808656
+   Generating output for cell sky130_fd_io__com_pudrvr_weakv2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_5595914180850
+   Generating output for cell sky130_fd_io__gpio_pddrvr_weakv2
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418085
+   Generating output for cell sky130_fd_io__pfet_con_diff_wo_abt_270v2
+   Generating output for cell sky130_fd_io__gpio_pudrvr_strongv2
+   Generating output for cell sky130_fd_io__gpio_pddrvr_strong_slowv2
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180852
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180853
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180855
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180856
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180832
+   Generating output for cell sky130_fd_pr__via_pol1_centered__example_559591418080
+   Generating output for cell sky130_fd_io__gpio_odrvr_subv2
+   Generating output for cell sky130_fd_io__gpio_odrvrv2
+   Generating output for cell sky130_fd_io__gpio_opathv2
+   Generating output for cell sky130_fd_io__top_gpiov2
+   Generating output for cell sky130_ef_io__gpiov2_pad
+   Generating output for cell sky130_ef_io__gpiov2_pad_wrapped
+   Generating output for cell sky130_ef_io__lvc_vccdx_overlay
+   Generating output for cell sky130_fd_io__overlay_vssd_lvc
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808683
+   Generating output for cell sky130_fd_io__gnd2gnd_strap
+   Generating output for cell sky130_fd_io__gnd2gnd_tap
+   Generating output for cell sky130_fd_io__gnd2gnd_diff
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808684
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808685
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808686
+   Generating output for cell sky130_fd_io__gnd2gnd_sub_dnwl
+   Generating output for cell sky130_fd_io__gnd2gnd_120x2_lv_isosub
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808687
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808691
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808690
+   Generating output for cell sky130_fd_pr__dftpl1s2__example_55959141808702
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808705
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808682
+   Generating output for cell sky130_fd_pr__dftpl1s2__example_55959141808694
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808693
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808681
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808688
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808696
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808697
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808698
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808699
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808695
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808704
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808703
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808701
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808692
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808689
+   Generating output for cell sky130_fd_io__top_ground_lvc_wpad
+   Generating output for cell sky130_ef_io__vssd_lvc_clamped_pad
+   Generating output for cell sky130_ef_io__hvc_vssio_overlay
+   Generating output for cell sky130_fd_io__overlay_vssio_hvc
+   Generating output for cell sky130_ef_io__vssio_hvc_clamped_pad
+   Generating output for cell sky130_fd_io__overlay_vdda_hvc
+   Generating output for cell sky130_fd_io__hvc_clampv2
+   Generating output for cell sky130_fd_io__top_power_hvc_wpadv2
+   Generating output for cell sky130_ef_io__vdda_hvc_clamped_pad
+   Generating output for cell sky130_fd_io__overlay_vccd_lvc
+   Generating output for cell sky130_fd_io__top_power_lvc_wpad
+   Generating output for cell sky130_ef_io__vccd_lvc_clamped_pad
+   Generating output for cell sky130_ef_io__disconnect_vdda_slice_5um
+   Generating output for cell sky130_ef_io__hvc_vddio_overlay
+   Generating output for cell sky130_fd_io__overlay_vddio_hvc
+   Generating output for cell sky130_ef_io__vddio_hvc_clamped_pad
+   Generating output for cell sky130_ef_io__lvc_vccdy_overlay
+   Generating output for cell sky130_ef_io__vssd_lvc_clamped3_pad
+   Generating output for cell sky130_ef_io__vccd_lvc_clamped3_pad
+   Generating output for cell chip_io
+   Generating output for cell user_project_wrapper
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_11$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_12$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_360_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w1_120_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_15$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_29$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_28$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m2_w0_740_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m2_w1_260_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_13$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_14$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_16$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w7_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w7_000_sli_dli_da_p$1".
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_dec$1".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_740_sactive_dli$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_740_sli_dactive$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w1_120_sli_dli$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m22_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m22_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m7_w1_680_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m7_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m18_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m18_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m3_w1_680_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m3_w1_680_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_dec_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_20$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_and2_dec$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_17$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_and3_dec$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w2_880_sli_dli$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pnand2$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_23$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_22$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_21$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_19$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w0_550_sli_dli$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_7$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_15$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m40_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m40_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_3$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m12_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m12_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m4_w1_260_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m4_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_16$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_740_sactive_dactive$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m24_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m24_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m8_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m8_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m3_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m3_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m39_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m39_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m13_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m13_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m5_w1_680_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m5_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m2_w1_260_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m2_w2_000_sli_dli_da_p$1".
+Reading "sky130_fd_bd_sram__openram_dff$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_2$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_1$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_wordline_driver$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_hierarchical_predecode3x8$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_hierarchical_predecode2x4$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_column_mux_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_precharge_1$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_27$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_26$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_25$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_24$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_column_mux$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pand2$1".
+Reading "sky130_fd_bd_sram__openram_write_driver$1".
+Reading "sky130_fd_bd_sram__openram_sense_amp$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_precharge_0$1".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row$1".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col$1".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy$1".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica$1".
+Reading "sky130_fd_bd_sram__openram_dp_cell$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_3$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_10$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pnand2_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_dff_buf_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_18$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_17$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_19$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_4$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pnand3$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_14$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_13$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_12$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_11$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_20$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_9$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_8$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_7$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_6$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_and2_dec_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_wordline_driver_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_hierarchical_decoder$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_column_mux_array_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_precharge_array_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_column_mux_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_write_mask_and_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_write_driver_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_sense_amp_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_precharge_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_9$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_8$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_row_cap_array_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_row_cap_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_col_cap_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_col_cap_array_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_dummy_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_replica_column_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_replica_column$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_bitcell_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_dff_buf_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pand3$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_1$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_33$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pnand2_1$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pand2_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_dff_buf_array_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_5$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_delay_chain$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pand3_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_2$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_6$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_34$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinvbuf$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_port_address_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_port_address$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_port_data_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_port_data$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_replica_bitcell_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_wmask_dff$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_cr_3$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_row_addr_dff$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_control_logic_rw$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_col_addr_dff$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_cr_5$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_40$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_39$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_control_logic_r$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_cr_4$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_data_dff$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_bank$1".
+Reading "sky130_fd_sc_hd__decap_6$1".
+Reading "sky130_fd_sc_hd__fill_2$1".
+Reading "sky130_fd_sc_hd__fill_4$1".
+Reading "sky130_fd_sc_hd__decap_6$2".
+Reading "sky130_fd_sc_hd__fill_4$2".
+Reading "sky130_fd_sc_hd__fill_2$2".
+Reading "sky130_fd_sc_hd__decap_6_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__fill_2_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__fill_4_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__nand2_2$1".
+Reading "sky130_fd_sc_hd__o21ai_2$1".
+Reading "sky130_fd_sc_hd__nor2b_2$1".
+Reading "sky130_fd_sc_hd__or2_2$3".
+Reading "sky130_fd_sc_hd__dlxtn_1$1".
+Reading "sky130_fd_sc_hd__nor2_2$1".
+Reading "sky130_fd_sc_hd__and2_2$1".
+Reading "sky130_fd_sc_hd__mux4_1$2".
+Reading "M1M2_PR_M$3".
+Reading "sky130_fd_sc_hd__decap_3$3".
+Reading "sky130_fd_sc_hd__decap_4$3".
+Reading "sky130_fd_sc_hd__dfxtp_2$3".
+Reading "BlockRAM_1KB_VIA3$1".
+Reading "BlockRAM_1KB_VIA2$1".
+Reading "BlockRAM_1KB_VIA1$1".
+Reading "BlockRAM_1KB_VIA0$1".
+Reading "M3M4_PR$3".
+Reading "sky130_fd_sc_hd__diode_2$3".
+Reading "M2M3_PR$3".
+Reading "sky130_fd_sc_hd__conb_1$2".
+Reading "sky130_fd_sc_hd__decap_6$3".
+Reading "M1M2_PR$3".
+Reading "L1M1_PR$3".
+Reading "sky130_fd_sc_hd__fill_1$3".
+Reading "sky130_fd_sc_hd__fill_4$3".
+Reading "sky130_fd_sc_hd__fill_8$1".
+Reading "sky130_fd_sc_hd__fill_2$3".
+Reading "sky130_fd_sc_hd__decap_8$3".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1$3".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8$1".
+Reading "sky130_fd_sc_hd__mux2_1$3".
+Reading "sky130_fd_sc_hd__inv_2$3".
+Reading "sky130_fd_sc_hd__clkbuf_1_N_term_RAM_IO_gds".
+Reading "M3M4_PR_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1_N_term_RAM_IO_gds".
+Reading "N_term_RAM_IO_VIA4".
+Reading "N_term_RAM_IO_VIA5".
+Reading "N_term_RAM_IO_VIA6".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_N_term_RAM_IO_gds".
+Reading "M1M2_PR_M_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_4_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_2_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_1_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__buf_8_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_8_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__decap_8_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_RAM_IO_gds".
+Reading "L1M1_PR_N_term_RAM_IO_gds".
+Reading "M2M3_PR_N_term_RAM_IO_gds".
+Reading "N_term_RAM_IO_VIA1".
+Reading "N_term_RAM_IO_VIA2".
+Reading "N_term_RAM_IO_VIA3".
+Reading "N_term_RAM_IO_VIA0".
+Reading "M1M2_PR_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_N_term_DSP_gds".
+Reading "M1M2_PR_M_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__buf_2_N_term_DSP_gds".
+Reading "N_term_DSP_VIA6".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_N_term_DSP_gds".
+Reading "N_term_DSP_VIA4".
+Reading "N_term_DSP_VIA5".
+Reading "sky130_fd_sc_hd__fill_4_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__decap_8_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__fill_8_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__fill_2_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__fill_1_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__buf_8_N_term_DSP_gds".
+Reading "N_term_DSP_VIA0".
+Reading "N_term_DSP_VIA1".
+Reading "N_term_DSP_VIA2".
+Reading "N_term_DSP_VIA3".
+Reading "M2M3_PR_N_term_DSP_gds".
+Reading "M1M2_PR_N_term_DSP_gds".
+Reading "L1M1_PR_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_N_term_single2_gds".
+Reading "M1M2_PR_M_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__buf_2_N_term_single2_gds".
+Reading "N_term_single2_VIA6".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_N_term_single2_gds".
+Reading "N_term_single2_VIA4".
+Reading "N_term_single2_VIA5".
+Reading "sky130_fd_sc_hd__fill_4_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__decap_8_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__fill_8_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__fill_2_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__fill_1_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__buf_8_N_term_single2_gds".
+Reading "N_term_single2_VIA0".
+Reading "N_term_single2_VIA1".
+Reading "N_term_single2_VIA2".
+Reading "N_term_single2_VIA3".
+Reading "M2M3_PR_N_term_single2_gds".
+Reading "M1M2_PR_N_term_single2_gds".
+Reading "L1M1_PR_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_N_term_single_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_N_term_single_gds".
+Reading "sky130_fd_sc_hd__buf_2_N_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_4_N_term_single_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_N_term_single_gds".
+Reading "N_term_single_VIA4".
+Reading "N_term_single_VIA5".
+Reading "N_term_single_VIA6".
+Reading "sky130_fd_sc_hd__decap_8_N_term_single_gds".
+Reading "M1M2_PR_M_N_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_8_N_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_2_N_term_single_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_1_N_term_single_gds".
+Reading "sky130_fd_sc_hd__buf_8_N_term_single_gds".
+Reading "N_term_single_VIA1".
+Reading "N_term_single_VIA2".
+Reading "N_term_single_VIA3".
+Reading "N_term_single_VIA0".
+Reading "L1M1_PR_N_term_single_gds".
+Reading "M1M2_PR_N_term_single_gds".
+Reading "M2M3_PR_N_term_single_gds".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1$1".
+Reading "sky130_fd_sc_hd__clkbuf_4$1".
+Reading "M1M2_PR_R$1".
+Reading "M2M3_PR_R$1".
+Reading "sky130_ef_sc_hd__fill_12$1".
+Reading "sky130_fd_sc_hd__clkinv_4$1".
+Reading "RegFile_VIA6$1".
+Reading "RegFile_VIA5$1".
+Reading "RegFile_VIA4$1".
+Reading "sky130_ef_sc_hd__fill_8$1".
+Reading "sky130_fd_sc_hd__buf_2$1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1$1".
+Reading "sky130_fd_sc_hd__buf_4$1".
+Reading "sky130_ef_sc_hd__decap_12$1".
+Reading "sky130_fd_sc_hd__decap_8$1".
+Reading "sky130_fd_sc_hd__mux2_4$1".
+Reading "sky130_fd_sc_hd__or3_1$1".
+Reading "sky130_fd_sc_hd__mux4_4$1".
+Reading "sky130_fd_sc_hd__mux2_1$1".
+Reading "sky130_fd_sc_hd__clkbuf_1$1".
+Reading "sky130_fd_sc_hd__buf_12$1".
+Reading "sky130_fd_sc_hd__mux4_1$1".
+Reading "sky130_fd_sc_hd__dlxbp_1$1".
+Reading "M1M2_PR_MR$1".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1$1".
+Reading "sky130_fd_sc_hd__clkinv_8$1".
+Reading "sky130_fd_sc_hd__mux4_2$1".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1$1".
+Reading "sky130_fd_sc_hd__or2_2$1".
+Reading "sky130_fd_sc_hd__clkinv_16$1".
+Reading "sky130_fd_sc_hd__buf_1$1".
+Reading "sky130_fd_sc_hd__decap_3$1".
+Reading "sky130_fd_sc_hd__dfxtp_2$1".
+Reading "sky130_fd_sc_hd__diode_2$1".
+Reading "sky130_fd_sc_hd__inv_2$1".
+Reading "M1M2_PR_M$1".
+Reading "sky130_fd_sc_hd__buf_8$1".
+Reading "sky130_fd_sc_hd__a22o_1$1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1$1".
+Reading "RegFile_VIA3$1".
+Reading "sky130_fd_sc_hd__decap_4$1".
+Reading "sky130_fd_sc_hd__fill_1$1".
+Reading "RegFile_VIA0$1".
+Reading "RegFile_VIA1$1".
+Reading "M3M4_PR$1".
+Reading "RegFile_VIA2$1".
+Reading "M1M2_PR$1".
+Reading "M2M3_PR$1".
+Reading "L1M1_PR$1".
+Reading "sky130_fd_sc_hd__buf_1_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__decap_6_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__buf_8_S_term_single2_gds".
+Reading "S_term_single2_VIA4".
+Reading "S_term_single2_VIA5".
+Reading "S_term_single2_VIA6".
+Reading "sky130_fd_sc_hd__clkinv_4_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__fill_2_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__fill_8_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__fill_4_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__fill_1_S_term_single2_gds".
+Reading "L1M1_PR_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__decap_8_S_term_single2_gds".
+Reading "M1M2_PR_M_S_term_single2_gds".
+Reading "S_term_single2_VIA2".
+Reading "S_term_single2_VIA3".
+Reading "M2M3_PR_S_term_single2_gds".
+Reading "S_term_single2_VIA0".
+Reading "S_term_single2_VIA1".
+Reading "M1M2_PR_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__buf_1_W_IO_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1_W_IO_gds".
+Reading "M1M2_PR_MR_W_IO_gds".
+Reading "sky130_fd_sc_hd__dfxtp_2_W_IO_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_W_IO_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_W_IO_gds".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1_W_IO_gds".
+Reading "sky130_fd_sc_hd__conb_1_W_IO_gds".
+Reading "sky130_fd_sc_hd__inv_2_W_IO_gds".
+Reading "W_IO_VIA6".
+Reading "W_IO_VIA4".
+Reading "W_IO_VIA5".
+Reading "sky130_fd_sc_hd__buf_8_W_IO_gds".
+Reading "sky130_fd_sc_hd__mux4_2_W_IO_gds".
+Reading "sky130_fd_sc_hd__mux2_1_W_IO_gds".
+Reading "sky130_fd_sc_hd__dlxbp_1_W_IO_gds".
+Reading "sky130_fd_sc_hd__decap_6_W_IO_gds".
+Reading "sky130_fd_sc_hd__diode_2_W_IO_gds".
+Reading "sky130_fd_sc_hd__decap_8_W_IO_gds".
+Reading "sky130_fd_sc_hd__decap_4_W_IO_gds".
+Reading "M1M2_PR_M_W_IO_gds".
+Reading "M3M4_PR_W_IO_gds".
+Reading "L1M1_PR_W_IO_gds".
+Reading "sky130_fd_sc_hd__fill_2_W_IO_gds".
+Reading "M1M2_PR_W_IO_gds".
+Reading "W_IO_VIA0".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_W_IO_gds".
+Reading "M2M3_PR_W_IO_gds".
+Reading "sky130_fd_sc_hd__decap_3_W_IO_gds".
+Reading "sky130_fd_sc_hd__fill_1_W_IO_gds".
+Reading "W_IO_VIA1".
+Reading "W_IO_VIA2".
+Reading "W_IO_VIA3".
+Reading "sky130_fd_sc_hd__clkinv_8_RAM_IO_gds".
+Reading "M2M3_PR_R".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_RAM_IO_gds".
+Reading "RAM_IO_VIA4".
+Reading "RAM_IO_VIA5".
+Reading "RAM_IO_VIA6".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__buf_4_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1_RAM_IO_gds".
+Reading "M1M2_PR_R_RAM_IO_gds".
+Reading "L1M1_PR_R_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__conb_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__mux4_2_RAM_IO_gds".
+Reading "M1M2_PR_MR_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__buf_2_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkinv_16_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__diode_2_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__decap_4_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__dlxbp_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__decap_3_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_8_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__buf_8_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__dfxtp_2_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkbuf_4_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__buf_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_4_RAM_IO_gds".
+Reading "M1M2_PR_M_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__mux2_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_2_RAM_IO_gds".
+Reading "RAM_IO_VIA1".
+Reading "L1M1_PR_RAM_IO_gds".
+Reading "RAM_IO_VIA2".
+Reading "M2M3_PR_RAM_IO_gds".
+Reading "RAM_IO_VIA3".
+Reading "sky130_fd_sc_hd__fill_1_RAM_IO_gds".
+Reading "RAM_IO_VIA0".
+Reading "M1M2_PR_RAM_IO_gds".
+Reading "M3M4_PR_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__decap_4_S_term_RAM_IO_gds".
+Reading "M1M2_PR_M_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_S_term_RAM_IO_gds".
+Reading "S_term_RAM_IO_VIA4".
+Reading "S_term_RAM_IO_VIA5".
+Reading "S_term_RAM_IO_VIA6".
+Reading "sky130_fd_sc_hd__decap_6_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__buf_8_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__diode_2_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__decap_8_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_8_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_1_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_4_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_2_S_term_RAM_IO_gds".
+Reading "M2M3_PR_S_term_RAM_IO_gds".
+Reading "L1M1_PR_S_term_RAM_IO_gds".
+Reading "M1M2_PR_S_term_RAM_IO_gds".
+Reading "S_term_RAM_IO_VIA0".
+Reading "S_term_RAM_IO_VIA1".
+Reading "S_term_RAM_IO_VIA2".
+Reading "S_term_RAM_IO_VIA3".
+Reading "sky130_fd_sc_hd__o31a_1$1".
+Reading "sky130_fd_sc_hd__and2b_1$1".
+Reading "sky130_fd_sc_hd__a2bb2oi_1$1".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1$2".
+Reading "sky130_fd_sc_hd__clkbuf_4$2".
+Reading "sky130_fd_sc_hd__xor2_1$1".
+Reading "sky130_fd_sc_hd__o22ai_1$1".
+Reading "sky130_fd_sc_hd__a31oi_1$1".
+Reading "sky130_fd_sc_hd__a21oi_1$1".
+Reading "sky130_fd_sc_hd__a22o_1$2".
+Reading "sky130_fd_sc_hd__o221a_2$1".
+Reading "sky130_fd_sc_hd__a22oi_1$1".
+Reading "sky130_fd_sc_hd__mux2_2$1".
+Reading "sky130_fd_sc_hd__o21ai_1$1".
+Reading "sky130_fd_sc_hd__buf_12$2".
+Reading "sky130_fd_sc_hd__a221o_1$1".
+Reading "sky130_fd_sc_hd__o2bb2a_1$1".
+Reading "sky130_fd_sc_hd__a32o_1$1".
+Reading "sky130_fd_sc_hd__a31o_2$1".
+Reading "sky130_fd_sc_hd__and4_1$1".
+Reading "sky130_fd_sc_hd__or3_1$2".
+Reading "sky130_fd_sc_hd__o32a_1$1".
+Reading "DSP_VIA5$1".
+Reading "DSP_VIA4$1".
+Reading "DSP_VIA6$1".
+Reading "sky130_fd_sc_hd__conb_1$1".
+Reading "M1M2_PR_MR$2".
+Reading "sky130_fd_sc_hd__o21a_1$1".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1$2".
+Reading "sky130_fd_sc_hd__buf_2$2".
+Reading "sky130_fd_sc_hd__decap_3$2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1$2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1$2".
+Reading "sky130_fd_sc_hd__nand2_1$1".
+Reading "sky130_fd_sc_hd__mux2_4$2".
+Reading "sky130_fd_sc_hd__dfxtp_2$2".
+Reading "sky130_fd_sc_hd__a2bb2o_1$1".
+Reading "sky130_fd_sc_hd__a21o_1$1".
+Reading "sky130_fd_sc_hd__a21bo_2$1".
+Reading "sky130_fd_sc_hd__and2_1$1".
+Reading "sky130_fd_sc_hd__o21ba_2$1".
+Reading "sky130_fd_sc_hd__o22a_1$1".
+Reading "sky130_fd_sc_hd__or4_1$1".
+Reading "sky130_fd_sc_hd__xnor2_1$1".
+Reading "sky130_fd_sc_hd__or2b_1$1".
+Reading "sky130_fd_sc_hd__nor2_1$1".
+Reading "sky130_fd_sc_hd__or2_2$2".
+Reading "sky130_fd_sc_hd__inv_2$2".
+Reading "sky130_fd_sc_hd__mux2_1$2".
+Reading "sky130_fd_sc_hd__buf_1$2".
+Reading "L1M1_PR_R$1".
+Reading "sky130_fd_sc_hd__clkinv_4$2".
+Reading "sky130_fd_sc_hd__mux4_2$2".
+Reading "M1M2_PR_R$2".
+Reading "sky130_fd_sc_hd__decap_4$2".
+Reading "sky130_fd_sc_hd__buf_8$2".
+Reading "sky130_ef_sc_hd__fill_12$2".
+Reading "sky130_fd_sc_hd__dlxbp_1$2".
+Reading "sky130_fd_sc_hd__clkbuf_1$2".
+Reading "M1M2_PR_M$2".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1$2".
+Reading "sky130_ef_sc_hd__fill_8$2".
+Reading "sky130_ef_sc_hd__decap_12$2".
+Reading "sky130_fd_sc_hd__diode_2$2".
+Reading "sky130_fd_sc_hd__decap_8$2".
+Reading "M3M4_PR$2".
+Reading "DSP_VIA0$1".
+Reading "DSP_VIA2$1".
+Reading "DSP_VIA3$1".
+Reading "M2M3_PR$2".
+Reading "M1M2_PR$2".
+Reading "DSP_VIA1$1".
+Reading "L1M1_PR$2".
+Reading "sky130_fd_sc_hd__fill_1$2".
+Reading "sky130_fd_sc_hd__buf_1_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__decap_6_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__buf_8_S_term_DSP_gds".
+Reading "S_term_DSP_VIA4".
+Reading "S_term_DSP_VIA5".
+Reading "S_term_DSP_VIA6".
+Reading "sky130_fd_sc_hd__clkinv_4_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__fill_2_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__fill_8_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__fill_4_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__fill_1_S_term_DSP_gds".
+Reading "L1M1_PR_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__decap_8_S_term_DSP_gds".
+Reading "M1M2_PR_M_S_term_DSP_gds".
+Reading "S_term_DSP_VIA2".
+Reading "S_term_DSP_VIA3".
+Reading "M2M3_PR_S_term_DSP_gds".
+Reading "S_term_DSP_VIA0".
+Reading "S_term_DSP_VIA1".
+Reading "M1M2_PR_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__clkinv_16_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_LUT4AB_gds".
+Reading "L1M1_PR_R_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__buf_2_LUT4AB_gds".
+Reading "LUT4AB_VIA4".
+Reading "LUT4AB_VIA5".
+Reading "LUT4AB_VIA6".
+Reading "sky130_fd_sc_hd__clkinv_8_LUT4AB_gds".
+Reading "M1M2_PR_R_LUT4AB_gds".
+Reading "M1M2_PR_MR_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__decap_4_LUT4AB_gds".
+Reading "sky130_ef_sc_hd__fill_12_LUT4AB_gds".
+Reading "sky130_ef_sc_hd__decap_12_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__conb_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__mux2_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__mux2_4_LUT4AB_gds".
+Reading "sky130_ef_sc_hd__fill_8_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__inv_2_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__nor2_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__mux4_2_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__decap_3_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__o22a_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__buf_8_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__dfxtp_2_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__dlxbp_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__mux2_2_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__decap_8_LUT4AB_gds".
+Reading "M3M4_PR_LUT4AB_gds".
+Reading "M1M2_PR_M_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__fill_1_LUT4AB_gds".
+Reading "M2M3_PR_LUT4AB_gds".
+Reading "M1M2_PR_LUT4AB_gds".
+Reading "LUT4AB_VIA1".
+Reading "LUT4AB_VIA2".
+Reading "LUT4AB_VIA0".
+Reading "sky130_fd_sc_hd__diode_2_LUT4AB_gds".
+Reading "L1M1_PR_LUT4AB_gds".
+Reading "LUT4AB_VIA3".
+Reading "sky130_fd_sc_hd__conb_1_S_term_single_gds".
+Reading "M1M2_PR_M_S_term_single_gds".
+Reading "sky130_fd_sc_hd__buf_1_S_term_single_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_S_term_single_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_S_term_single_gds".
+Reading "sky130_fd_sc_hd__decap_6_S_term_single_gds".
+Reading "sky130_fd_sc_hd__buf_8_S_term_single_gds".
+Reading "S_term_single_VIA4".
+Reading "S_term_single_VIA5".
+Reading "S_term_single_VIA6".
+Reading "S_term_single_VIA0".
+Reading "sky130_fd_sc_hd__fill_4_S_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_2_S_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_1_S_term_single_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_8_S_term_single_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_S_term_single_gds".
+Reading "sky130_fd_sc_hd__decap_8_S_term_single_gds".
+Reading "M2M3_PR_S_term_single_gds".
+Reading "M1M2_PR_S_term_single_gds".
+Reading "S_term_single_VIA1".
+Reading "S_term_single_VIA2".
+Reading "S_term_single_VIA3".
+Reading "L1M1_PR_S_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_4".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "BlockRAM_1KB".
+Reading "N_term_RAM_IO".
+Reading "eFPGA_top_VIA7".
+Reading "eFPGA_top_VIA23".
+Reading "eFPGA_top_VIA24".
+Reading "eFPGA_top_VIA25".
+Reading "eFPGA_top_VIA6".
+Reading "eFPGA_top_VIA8".
+Reading "eFPGA_top_VIA19".
+Reading "N_term_DSP".
+Reading "eFPGA_top_VIA11".
+Reading "N_term_single2".
+Reading "N_term_single".
+Reading "eFPGA_top_VIA22".
+Reading "eFPGA_top_VIA36".
+Reading "eFPGA_top_VIA20".
+Reading "eFPGA_top_VIA21".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__buf_16".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_2".
+Reading "RegFile".
+Reading "S_term_single2".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__a2bb2oi_2".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__dlxbp_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "L1M1_PR_R".
+Reading "W_IO".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "eFPGA_top_VIA35".
+Reading "sky130_fd_sc_hd__clkdlybuf4s15_1".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "M1M2_PR_R".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "M1M2_PR_MR".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "eFPGA_top_VIA29".
+Reading "eFPGA_top_VIA30".
+Reading "sky130_fd_sc_hd__clkdlybuf4s18_2".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "RAM_IO".
+Reading "S_term_RAM_IO".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "M1M2_PR_M".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "DSP".
+Reading "S_term_DSP".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "eFPGA_top_VIA10".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "LUT4AB".
+Reading "S_term_single".
+Reading "sky130_fd_sc_hd__bufbuf_8".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "eFPGA_top_VIA9".
+Reading "eFPGA_top_VIA34".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "eFPGA_top_VIA37".
+Reading "eFPGA_top_VIA38".
+Reading "eFPGA_top_VIA39".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__bufbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "eFPGA_top_VIA18".
+Reading "eFPGA_top_VIA4".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "eFPGA_top_VIA32".
+Reading "eFPGA_top_VIA31".
+Reading "eFPGA_top_VIA5".
+Reading "eFPGA_top_VIA15".
+Reading "eFPGA_top_VIA33".
+Reading "eFPGA_top_VIA16".
+Reading "eFPGA_top_VIA17".
+Reading "eFPGA_top_VIA14".
+Reading "eFPGA_top_VIA1".
+Reading "eFPGA_top_VIA3".
+Reading "eFPGA_top_VIA12".
+Reading "eFPGA_top_VIA2".
+Reading "eFPGA_top_VIA13".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__clkinv_16".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "eFPGA_top_VIA0".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "M2M3_PR".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "M3M4_PR".
+Reading "eFPGA_top_VIA27".
+Reading "L1M1_PR".
+Reading "eFPGA_top_VIA28".
+Reading "sky130_ef_sc_hd__fill_12".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "M1M2_PR".
+Reading "sky130_ef_sc_hd__fill_8".
+Reading "eFPGA_top_VIA26".
+Reading "eFPGA_top".
+Reading "user_project_wrapper".
+   Generating output for cell caravel
+Make ship completed.
diff --git a/signoff/build/set_user_id.out b/signoff/build/set_user_id.out
new file mode 100644
index 0000000..82a76cf
--- /dev/null
+++ b/signoff/build/set_user_id.out
@@ -0,0 +1,8 @@
+Setting project user ID to: 00020005
+Step 1:  Modify GDS of the user_id_programming subcell
+Done!
+Step 2:  Add user project ID parameter to verilog.
+Done!
+Step 3:  Add user project ID text to top level layout.
+Done!
+Set user ID completed.
diff --git a/signoff/fill_generated b/signoff/fill_generated
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/signoff/fill_generated
diff --git a/signoff/kdrc_results_fom.xml b/signoff/kdrc_results_fom.xml
new file mode 100644
index 0000000..af54c87
--- /dev/null
+++ b/signoff/kdrc_results_fom.xml
@@ -0,0 +1,654 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/mnt/shuttles/shuttle/sak/klayout/tech/sky130A/fom_density.drc'</generator>
+ <top-cell>caravel_00020005</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>cfom.pd.1d</name>
+   <description>0.33 min fom pattern density</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>caravel_00020005</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (560,2870;560,3570;1260,3570;1260,2870)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (630,2730;630,3430;1330,3430;1330,2730)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (630,2800;630,3500;1330,3500;1330,2800)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (630,2870;630,3570;1330,3570;1330,2870)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (630,2940;630,3640;1330,3640;1330,2940)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (630,3010;630,3710;1330,3710;1330,3010)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (630,3080;630,3780;1330,3780;1330,3080)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (630,3150;630,3850;1330,3850;1330,3150)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (700,2730;700,3430;1400,3430;1400,2730)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (700,2800;700,3500;1400,3500;1400,2800)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (700,2870;700,3570;1400,3570;1400,2870)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (700,2940;700,3640;1400,3640;1400,2940)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (700,3010;700,3710;1400,3710;1400,3010)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (700,3080;700,3780;1400,3780;1400,3080)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (700,3150;700,3850;1400,3850;1400,3150)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (770,2660;770,3360;1470,3360;1470,2660)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (770,2730;770,3430;1470,3430;1470,2730)</value>
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+   <multiplicity>1</multiplicity>
+   <image/>
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+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
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+  <item>
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+   <category>'cfom.pd.1d'</category>
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+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
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+  <item>
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+   <category>'cfom.pd.1d'</category>
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+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
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+  <item>
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+   <category>'cfom.pd.1d'</category>
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+   <category>'cfom.pd.1d'</category>
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+   <image/>
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+   <category>'cfom.pd.1d'</category>
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+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
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+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
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+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
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+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
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+   <tags/>
+   <category>'cfom.pd.1d'</category>
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+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
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+   <category>'cfom.pd.1d'</category>
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+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
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+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
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+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
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+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
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+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
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+   <category>'cfom.pd.1d'</category>
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+   <category>'cfom.pd.1d'</category>
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+   <image/>
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+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
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+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
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+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
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+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
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+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
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+   <multiplicity>1</multiplicity>
+   <image/>
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+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
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+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
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+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (2310,4060;2310,4760;3010,4760;3010,4060)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cfom.pd.1d'</category>
+   <cell>caravel_00020005</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>polygon: (2310,4130;2310,4830;3010,4830;3010,4130)</value>
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+ </items>
+</report-database>
diff --git a/signoff/kdrc_results_fom.xml.summary b/signoff/kdrc_results_fom.xml.summary
new file mode 100644
index 0000000..2e9704f
--- /dev/null
+++ b/signoff/kdrc_results_fom.xml.summary
@@ -0,0 +1,2 @@
+      57 0.33 min fom pattern density
+      57 total error(s) among 1 error type(s), 1 non-zero type(s)
diff --git a/signoff/kdrc_results_met.xml b/signoff/kdrc_results_met.xml
new file mode 100644
index 0000000..347f0be
--- /dev/null
+++ b/signoff/kdrc_results_met.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/mnt/shuttles/shuttle/sak/klayout/tech/sky130A/met_density.lydrc'</generator>
+ <top-cell>caravel_00020005</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>caravel_00020005</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/signoff/kdrc_results_met.xml.summary b/signoff/kdrc_results_met.xml.summary
new file mode 100644
index 0000000..8d461a0
--- /dev/null
+++ b/signoff/kdrc_results_met.xml.summary
@@ -0,0 +1 @@
+       0 total error(s) among 0 error type(s), 0 non-zero type(s)
diff --git a/signoff/klayout_drc_fom.log b/signoff/klayout_drc_fom.log
new file mode 100644
index 0000000..d6b9c76
--- /dev/null
+++ b/signoff/klayout_drc_fom.log
@@ -0,0 +1,116 @@
+fom_density.drc:: sourcing design file=./gds/caravel_00020005.gds topcell=caravel_00020005 ...
+done.
+flattening chip boundary...
+done.
+step size = 70.0
+llx=5.965 lly=6.0 urx=3594.035 ury=5194.0
+x_cnt = 51
+y_cnt = 74
+dbu = 0.001
+bbox_area = 18614907.16
+calculating subtile areas (= 3774)...
+tiles per step = 10
+calculating window step densities (= 2730)...
+{{ CHECK }} 0/2730
+{{ CHECK }} 65/2730
+{{ CHECK }} 130/2730
+{{ CHECK }} 195/2730
+{{ CHECK }} 260/2730
+{{ CHECK }} 325/2730
+{{ CHECK }} 390/2730
+{{ CHECK }} 455/2730
+{{ CHECK }} 520/2730
+fom density below 0.33 : 561/2730 is 0.3298 for tile ((560,2870;1260,3570)), area = 490000
+{{ CHECK }} 585/2730
+fom density below 0.33 : 624/2730 is 0.3274 for tile ((630,2730;1330,3430)), area = 490000
+fom density below 0.33 : 625/2730 is 0.3263 for tile ((630,2800;1330,3500)), area = 490000
+fom density below 0.33 : 626/2730 is 0.3225 for tile ((630,2870;1330,3570)), area = 490000
+fom density below 0.33 : 627/2730 is 0.3234 for tile ((630,2940;1330,3640)), area = 490000
+fom density below 0.33 : 628/2730 is 0.3262 for tile ((630,3010;1330,3710)), area = 490000
+fom density below 0.33 : 629/2730 is 0.3291 for tile ((630,3080;1330,3780)), area = 490000
+fom density below 0.33 : 630/2730 is 0.3300 for tile ((630,3150;1330,3850)), area = 490000
+{{ CHECK }} 650/2730
+fom density below 0.33 : 689/2730 is 0.3255 for tile ((700,2730;1400,3430)), area = 490000
+fom density below 0.33 : 690/2730 is 0.3242 for tile ((700,2800;1400,3500)), area = 490000
+fom density below 0.33 : 691/2730 is 0.3205 for tile ((700,2870;1400,3570)), area = 490000
+fom density below 0.33 : 692/2730 is 0.3214 for tile ((700,2940;1400,3640)), area = 490000
+fom density below 0.33 : 693/2730 is 0.3246 for tile ((700,3010;1400,3710)), area = 490000
+fom density below 0.33 : 694/2730 is 0.3281 for tile ((700,3080;1400,3780)), area = 490000
+fom density below 0.33 : 695/2730 is 0.3289 for tile ((700,3150;1400,3850)), area = 490000
+{{ CHECK }} 715/2730
+fom density below 0.33 : 753/2730 is 0.3296 for tile ((770,2660;1470,3360)), area = 490000
+fom density below 0.33 : 754/2730 is 0.3243 for tile ((770,2730;1470,3430)), area = 490000
+fom density below 0.33 : 755/2730 is 0.3228 for tile ((770,2800;1470,3500)), area = 490000
+fom density below 0.33 : 756/2730 is 0.3194 for tile ((770,2870;1470,3570)), area = 490000
+fom density below 0.33 : 757/2730 is 0.3203 for tile ((770,2940;1470,3640)), area = 490000
+fom density below 0.33 : 758/2730 is 0.3231 for tile ((770,3010;1470,3710)), area = 490000
+fom density below 0.33 : 759/2730 is 0.3268 for tile ((770,3080;1470,3780)), area = 490000
+fom density below 0.33 : 760/2730 is 0.3275 for tile ((770,3150;1470,3850)), area = 490000
+{{ CHECK }} 780/2730
+fom density below 0.33 : 819/2730 is 0.3298 for tile ((840,2730;1540,3430)), area = 490000
+fom density below 0.33 : 820/2730 is 0.3290 for tile ((840,2800;1540,3500)), area = 490000
+fom density below 0.33 : 821/2730 is 0.3253 for tile ((840,2870;1540,3570)), area = 490000
+fom density below 0.33 : 822/2730 is 0.3258 for tile ((840,2940;1540,3640)), area = 490000
+fom density below 0.33 : 823/2730 is 0.3282 for tile ((840,3010;1540,3710)), area = 490000
+{{ CHECK }} 845/2730
+fom density below 0.33 : 886/2730 is 0.3271 for tile ((910,2870;1610,3570)), area = 490000
+fom density below 0.33 : 887/2730 is 0.3275 for tile ((910,2940;1610,3640)), area = 490000
+fom density below 0.33 : 888/2730 is 0.3293 for tile ((910,3010;1610,3710)), area = 490000
+{{ CHECK }} 910/2730
+fom density below 0.33 : 951/2730 is 0.3285 for tile ((980,2870;1680,3570)), area = 490000
+fom density below 0.33 : 952/2730 is 0.3289 for tile ((980,2940;1680,3640)), area = 490000
+{{ CHECK }} 975/2730
+{{ CHECK }} 1040/2730
+{{ CHECK }} 1105/2730
+{{ CHECK }} 1170/2730
+{{ CHECK }} 1235/2730
+{{ CHECK }} 1300/2730
+{{ CHECK }} 1365/2730
+{{ CHECK }} 1430/2730
+{{ CHECK }} 1495/2730
+{{ CHECK }} 1560/2730
+{{ CHECK }} 1625/2730
+{{ CHECK }} 1690/2730
+{{ CHECK }} 1755/2730
+{{ CHECK }} 1820/2730
+{{ CHECK }} 1885/2730
+{{ CHECK }} 1950/2730
+{{ CHECK }} 2015/2730
+{{ CHECK }} 2080/2730
+fom density below 0.33 : 2102/2730 is 0.3300 for tile ((2240,1540;2940,2240)), area = 490000
+fom density below 0.33 : 2103/2730 is 0.3289 for tile ((2240,1610;2940,2310)), area = 490000
+fom density below 0.33 : 2108/2730 is 0.3275 for tile ((2240,1960;2940,2660)), area = 490000
+fom density below 0.33 : 2109/2730 is 0.3279 for tile ((2240,2030;2940,2730)), area = 490000
+fom density below 0.33 : 2126/2730 is 0.3276 for tile ((2240,3220;2940,3920)), area = 490000
+fom density below 0.33 : 2127/2730 is 0.3277 for tile ((2240,3290;2940,3990)), area = 490000
+fom density below 0.33 : 2132/2730 is 0.3290 for tile ((2240,3640;2940,4340)), area = 490000
+fom density below 0.33 : 2133/2730 is 0.3293 for tile ((2240,3710;2940,4410)), area = 490000
+fom density below 0.33 : 2138/2730 is 0.3275 for tile ((2240,4060;2940,4760)), area = 490000
+fom density below 0.33 : 2139/2730 is 0.3296 for tile ((2240,4130;2940,4830)), area = 490000
+{{ CHECK }} 2145/2730
+fom density below 0.33 : 2167/2730 is 0.3273 for tile ((2310,1540;3010,2240)), area = 490000
+fom density below 0.33 : 2168/2730 is 0.3258 for tile ((2310,1610;3010,2310)), area = 490000
+fom density below 0.33 : 2173/2730 is 0.3254 for tile ((2310,1960;3010,2660)), area = 490000
+fom density below 0.33 : 2174/2730 is 0.3251 for tile ((2310,2030;3010,2730)), area = 490000
+fom density below 0.33 : 2179/2730 is 0.3280 for tile ((2310,2380;3010,3080)), area = 490000
+fom density below 0.33 : 2180/2730 is 0.3278 for tile ((2310,2450;3010,3150)), area = 490000
+fom density below 0.33 : 2185/2730 is 0.3285 for tile ((2310,2800;3010,3500)), area = 490000
+fom density below 0.33 : 2186/2730 is 0.3270 for tile ((2310,2870;3010,3570)), area = 490000
+fom density below 0.33 : 2191/2730 is 0.3253 for tile ((2310,3220;3010,3920)), area = 490000
+fom density below 0.33 : 2192/2730 is 0.3248 for tile ((2310,3290;3010,3990)), area = 490000
+fom density below 0.33 : 2197/2730 is 0.3265 for tile ((2310,3640;3010,4340)), area = 490000
+fom density below 0.33 : 2198/2730 is 0.3261 for tile ((2310,3710;3010,4410)), area = 490000
+fom density below 0.33 : 2203/2730 is 0.3256 for tile ((2310,4060;3010,4760)), area = 490000
+fom density below 0.33 : 2204/2730 is 0.3264 for tile ((2310,4130;3010,4830)), area = 490000
+{{ CHECK }} 2210/2730
+{{ CHECK }} 2275/2730
+{{ CHECK }} 2340/2730
+{{ CHECK }} 2405/2730
+{{ CHECK }} 2470/2730
+{{ CHECK }} 2535/2730
+{{ CHECK }} 2600/2730
+{{ CHECK }} 2665/2730
+minimum fom density  = 0.3194
+maximum fom density  = 0.4958
+cfom.pd.1d violations = 57
+finish received: success = true
diff --git a/signoff/klayout_drc_met.log b/signoff/klayout_drc_met.log
new file mode 100644
index 0000000..7b984f6
--- /dev/null
+++ b/signoff/klayout_drc_met.log
@@ -0,0 +1,6 @@
+li1_ca_density is 0.498195197686893
+m1_ca_density is 0.5727492015579667
+m2_ca_density is 0.6262573537669555
+m3_ca_density is 0.5959006790415609
+m4_ca_density is 0.5327295391910261
+m5_ca_density is 0.5294507162849029
diff --git a/signoff/klayout_drc_version b/signoff/klayout_drc_version
new file mode 100644
index 0000000..2256b57
--- /dev/null
+++ b/signoff/klayout_drc_version
@@ -0,0 +1 @@
+KLayout 0.27.3
diff --git a/signoff/make_final b/signoff/make_final
new file mode 100644
index 0000000..51f204f
--- /dev/null
+++ b/signoff/make_final
@@ -0,0 +1 @@
+da2760b402772b4f392c4032d658f6b014321874  ./gds/caravel_00020005.gds
diff --git a/signoff/make_ship b/signoff/make_ship
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/signoff/make_ship
diff --git a/signoff/tapeout.log b/signoff/tapeout.log
new file mode 100644
index 0000000..31fe116
--- /dev/null
+++ b/signoff/tapeout.log
@@ -0,0 +1,36623 @@
+2759580    4 drwx------   2 root     root         4096 Dec  9 16:05 /root/.ssh
+2759586    4 -rw-------   1 root     root          401 Dec  9 16:05 /root/.ssh/id_rsa.pub
+2759587    4 -rw-------   1 root     root         2757 Dec  9 16:05 /root/.ssh/known_hosts
+2759583    4 -rw-------   1 root     root          401 Dec  9 16:05 /root/.ssh/authorized_keys
+2759584    4 -rw-------   1 root     root          218 Dec  9 16:05 /root/.ssh/config
+2759585    4 -rw-------   1 root     root         1679 Dec  9 16:05 /root/.ssh/id_rsa
+Welcome to GitLab, @jeffdi!
+-------------------------------------------------------------------------------------------
+-------------------------------------------------------------------------------------------
+Beginning tapeout for mpw-two, slot-005 eFPGA_v3_caravel
+
+Thu Dec  9 16:05:06 UTC 2021
+-------------------------------------------------------------------------------------------
+-------------------------------------------------------------------------------------------
+Everything up-to-date
+ok-------------------------------------------------------------------------------------------
+{{ STEP 1 }}  project ID: 00020005, project type: digital, shuttle-repo: https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-two/slot-005.git
+-------------------------------------------------------------------------------------------
+All files are uncompressed!
+USER_ID is set to 00020005
+All files are uncompressed!
+cd /mnt/shuttles/shuttle/mpw-two/caravel && \
+make uncompress
+make[1]: Entering directory `/mnt/shuttles/shuttle/mpw-two/caravel'
+All files are uncompressed!
+make[1]: Leaving directory `/mnt/shuttles/shuttle/mpw-two/caravel'
+make -f /mnt/shuttles/shuttle/mpw-two/caravel/Makefile __set_user_id
+make[1]: Entering directory `/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel'
+mkdir -p ./signoff/build
+# Update info.yaml
+# sed -r "s/^(\s*project_id\s*:\s*).*/\100020005/" -i info.yaml
+cp /mnt/shuttles/shuttle/mpw-two/caravel/gds/user_id_programming.gds ./gds/user_id_programming.gds
+cp /mnt/shuttles/shuttle/mpw-two/caravel/mag/user_id_programming.mag ./mag/user_id_programming.mag
+cp /mnt/shuttles/shuttle/mpw-two/caravel/mag/user_id_textblock.mag ./mag/user_id_textblock.mag
+cp /mnt/shuttles/shuttle/mpw-two/caravel/verilog/rtl/caravel.v ./verilog/rtl/caravel.v
+python3 /mnt/shuttles/shuttle/mpw-two/caravel/scripts/set_user_id.py 00020005 /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel 2>&1 | tee ./signoff/build/set_user_id.out
+Setting project user ID to: 00020005
+Step 1:  Modify GDS of the user_id_programming subcell
+Done!
+Step 2:  Add user project ID parameter to verilog.
+Done!
+Step 3:  Add user project ID text to top level layout.
+Done!
+make[1]: Leaving directory `/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel'
+Set user ID completed.
+All files are uncompressed!
+cd /mnt/shuttles/shuttle/mpw-two/caravel && \
+make uncompress
+make[1]: Entering directory `/mnt/shuttles/shuttle/mpw-two/caravel'
+All files are uncompressed!
+make[1]: Leaving directory `/mnt/shuttles/shuttle/mpw-two/caravel'
+make -f /mnt/shuttles/shuttle/mpw-two/caravel/Makefile __gpio_defaults
+make[1]: Entering directory `/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel'
+mkdir -p ./signoff/build
+mkdir -p ./verilog/gl
+python3 /mnt/shuttles/shuttle/mpw-two/caravel/scripts/gen_gpio_defaults.py /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel 2>&1 | tee ./signoff/build/gpio_defaults.out
+Step 1:  Create new cells for new GPIO default vectors.
+Creating new layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag
+Creating new gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Step 2:  Modify top-level layouts to use the specified defaults.
+Done.
+make[1]: Leaving directory `/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel'
+GPIO defaults completed.
+fatal: ambiguous argument 'develop': unknown revision or path not in the working tree.
+Use '--' to separate paths from revisions, like this:
+'git <command> [<revision>...] -- [<file>...]'
+All files are uncompressed!
+cd /mnt/shuttles/shuttle/mpw-two/caravel && \
+make uncompress
+make[1]: Entering directory `/mnt/shuttles/shuttle/mpw-two/caravel'
+All files are uncompressed!
+make[1]: Leaving directory `/mnt/shuttles/shuttle/mpw-two/caravel'
+Running make ship in the foreground...
+make -f /mnt/shuttles/shuttle/mpw-two/caravel/Makefile __ship
+make[1]: Entering directory `/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel'
+###############################################
+Generating Caravel GDS (sources are in the 'gds' directory)
+#@cd /mnt/shuttles/shuttle/mpw-two/caravel/mag && PDKPATH=/mnt/shuttles/shuttle/mpw-two/pdks/sky130A MAGTYPE=mag magic -noc -dnull -rcfile /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.tech/magic/sky130A.magicrc /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/mag2gds_caravel.tcl 2>&1 | tee /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/signoff/build/make_ship.out
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/mag2gds_caravel.tcl" from command line.
+Scaled magic input cell user_id_textblock geometry by factor of 2
+caravel: 10000 rects
+caravel: 20000 rects
+caravel: 30000 rects
+caravel: 40000 rects
+caravel: 50000 rects
+caravel: 60000 rects
+Processing timestamp mismatches: user_project_wrapper, user_id_programming.
+Warning:  Parent cell lists instance of "caravel_motto" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/caravel_motto.mag.
+The cell exists in the search paths at ../mag/caravel_motto.mag.
+The discovered version will be used.
+Scaled magic input cell caravel_motto geometry by factor of 2
+Warning:  Parent cell lists instance of "font_22" at bad file path ../mag/font_22.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_22.mag.
+The discovered version will be used.
+Scaled magic input cell font_22 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_73" at bad file path ../mag/font_73.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_73.mag.
+The discovered version will be used.
+Scaled magic input cell font_73 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_43" at bad file path ../mag/font_43.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_43.mag.
+The discovered version will be used.
+Scaled magic input cell font_43 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_49" at bad file path ../mag/font_49.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_49.mag.
+The discovered version will be used.
+Scaled magic input cell font_49 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_65" at bad file path ../mag/font_65.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_65.mag.
+The discovered version will be used.
+Scaled magic input cell font_65 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_68" at bad file path ../mag/font_68.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_68.mag.
+The discovered version will be used.
+Scaled magic input cell font_68 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_54" at bad file path ../mag/font_54.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_54.mag.
+The discovered version will be used.
+Scaled magic input cell font_54 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_67" at bad file path ../mag/font_67.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_67.mag.
+The discovered version will be used.
+Scaled magic input cell font_67 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_6E" at bad file path ../mag/font_6E.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_6E.mag.
+The discovered version will be used.
+Scaled magic input cell font_6E geometry by factor of 24
+Warning:  Parent cell lists instance of "font_69" at bad file path ../mag/font_69.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_69.mag.
+The discovered version will be used.
+Scaled magic input cell font_69 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_6C" at bad file path ../mag/font_6C.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_6C.mag.
+The discovered version will be used.
+Scaled magic input cell font_6C geometry by factor of 24
+Warning:  Parent cell lists instance of "font_61" at bad file path ../mag/font_61.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_61.mag.
+The discovered version will be used.
+Scaled magic input cell font_61 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_53" at bad file path ../mag/font_53.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_53.mag.
+The discovered version will be used.
+Scaled magic input cell font_53 geometry by factor of 24
+Warning:  Parent cell lists instance of "caravel_logo" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/caravel_logo.mag.
+The cell exists in the search paths at ../mag/caravel_logo.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "open_source" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/open_source.mag.
+The cell exists in the search paths at hexdigits/open_source.mag.
+The discovered version will be used.
+Scaled magic input cell open_source geometry by factor of 2
+Warning:  Parent cell lists instance of "xres_buf" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/xres_buf.mag.
+The cell exists in the search paths at ../mag/xres_buf.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__lsbufhv2lv_1" at bad file path ../mag/sky130_fd_sc_hvl__lsbufhv2lv_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__lsbufhv2lv_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__decap_8" at bad file path ../mag/sky130_fd_sc_hvl__decap_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__decap_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__diode_2" at bad file path ../mag/sky130_fd_sc_hvl__diode_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__diode_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__fill_2" at bad file path ../mag/sky130_fd_sc_hvl__fill_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__fill_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__fill_1" at bad file path ../mag/sky130_fd_sc_hvl__fill_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__fill_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__decap_4" at bad file path ../mag/sky130_fd_sc_hvl__decap_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__decap_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "alpha_0" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/hexdigits/alpha_0.mag.
+The cell exists in the search paths at hexdigits/alpha_0.mag.
+The discovered version will be used.
+Scaled magic input cell alpha_0 geometry by factor of 2
+Warning:  Parent cell lists instance of "alpha_2" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/hexdigits/alpha_2.mag.
+The cell exists in the search paths at hexdigits/alpha_2.mag.
+The discovered version will be used.
+Scaled magic input cell alpha_2 geometry by factor of 72
+Warning:  Parent cell lists instance of "alpha_5" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/hexdigits/alpha_5.mag.
+The cell exists in the search paths at hexdigits/alpha_5.mag.
+The discovered version will be used.
+Scaled magic input cell alpha_5 geometry by factor of 72
+Warning:  Parent cell lists instance of "copyright_block" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/copyright_block.mag.
+The cell exists in the search paths at ../mag/copyright_block.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "font_62" at bad file path ../mag/font_62.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_62.mag.
+The discovered version will be used.
+Scaled magic input cell font_62 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_66" at bad file path ../mag/font_66.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_66.mag.
+The discovered version will be used.
+Scaled magic input cell font_66 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_29" at bad file path ../mag/font_29.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_29.mag.
+The discovered version will be used.
+Scaled magic input cell font_29 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_20" at bad file path ../mag/font_20.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_20.mag.
+The discovered version will be used.
+Scaled magic input cell font_20 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_28" at bad file path ../mag/font_28.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_28.mag.
+The discovered version will be used.
+Scaled magic input cell font_28 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_33" at bad file path ../mag/font_33.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_33.mag.
+The discovered version will be used.
+Scaled magic input cell font_33 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_56" at bad file path ../mag/font_56.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_56.mag.
+The discovered version will be used.
+Scaled magic input cell font_56 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_76" at bad file path ../mag/font_76.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_76.mag.
+The discovered version will be used.
+Scaled magic input cell font_76 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_72" at bad file path ../mag/font_72.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_72.mag.
+The discovered version will be used.
+Scaled magic input cell font_72 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_2D" at bad file path ../mag/font_2D.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_2D.mag.
+The discovered version will be used.
+Scaled magic input cell font_2D geometry by factor of 24
+Warning:  Parent cell lists instance of "font_4B" at bad file path ../mag/font_4B.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_4B.mag.
+The discovered version will be used.
+Scaled magic input cell font_4B geometry by factor of 24
+Warning:  Parent cell lists instance of "font_44" at bad file path ../mag/font_44.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_44.mag.
+The discovered version will be used.
+Scaled magic input cell font_44 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_50" at bad file path ../mag/font_50.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_50.mag.
+The discovered version will be used.
+Scaled magic input cell font_50 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_70" at bad file path ../mag/font_70.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_70.mag.
+The discovered version will be used.
+Scaled magic input cell font_70 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_6F" at bad file path ../mag/font_6F.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_6F.mag.
+The discovered version will be used.
+Scaled magic input cell font_6F geometry by factor of 24
+Warning:  Parent cell lists instance of "font_74" at bad file path ../mag/font_74.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_74.mag.
+The discovered version will be used.
+Scaled magic input cell font_74 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_57" at bad file path ../mag/font_57.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_57.mag.
+The discovered version will be used.
+Scaled magic input cell font_57 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_6B" at bad file path ../mag/font_6B.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_6B.mag.
+The discovered version will be used.
+Scaled magic input cell font_6B geometry by factor of 24
+Warning:  Parent cell lists instance of "font_79" at bad file path ../mag/font_79.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_79.mag.
+The discovered version will be used.
+Scaled magic input cell font_79 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_47" at bad file path ../mag/font_47.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_47.mag.
+The discovered version will be used.
+Scaled magic input cell font_47 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_31" at bad file path ../mag/font_31.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_31.mag.
+The discovered version will be used.
+Scaled magic input cell font_31 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_32" at bad file path ../mag/font_32.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_32.mag.
+The discovered version will be used.
+Scaled magic input cell font_32 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_30" at bad file path ../mag/font_30.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_30.mag.
+The discovered version will be used.
+Scaled magic input cell font_30 geometry by factor of 24
+Warning:  Parent cell lists instance of "font_6D" at bad file path ../mag/font_6D.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_6D.mag.
+The discovered version will be used.
+Scaled magic input cell font_6D geometry by factor of 24
+Warning:  Parent cell lists instance of "font_4E" at bad file path ../mag/font_4E.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_4E.mag.
+The discovered version will be used.
+Scaled magic input cell font_4E geometry by factor of 24
+Warning:  Parent cell lists instance of "caravel_clocking" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/caravel_clocking.mag.
+The cell exists in the search paths at ../mag/caravel_clocking.mag.
+The discovered version will be used.
+caravel_clocking: 10000 rects
+caravel_clocking: 20000 rects
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_1" at bad file path ../mag/sky130_fd_sc_hd__clkbuf_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor2_1" at bad file path ../mag/sky130_fd_sc_hd__nor2_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__inv_4" at bad file path ../mag/sky130_fd_sc_hd__inv_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__diode_2" at bad file path ../mag/sky130_fd_sc_hd__diode_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__diode_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__buf_2" at bad file path ../mag/sky130_fd_sc_hd__buf_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkdlybuf4s25_1" at bad file path ../mag/sky130_fd_sc_hd__clkdlybuf4s25_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkdlybuf4s25_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__mux2_1" at bad file path ../mag/sky130_fd_sc_hd__mux2_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__mux2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_2" at bad file path ../mag/sky130_fd_sc_hd__clkbuf_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__buf_1" at bad file path ../mag/sky130_fd_sc_hd__buf_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__mux2_2" at bad file path ../mag/sky130_fd_sc_hd__mux2_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__mux2_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__xor2_1" at bad file path ../mag/sky130_fd_sc_hd__xor2_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__xor2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand2_1" at bad file path ../mag/sky130_fd_sc_hd__nand2_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfstp_1" at bad file path ../mag/sky130_fd_sc_hd__dfstp_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfstp_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfrtp_1" at bad file path ../mag/sky130_fd_sc_hd__dfrtp_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfrtp_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfrtn_1" at bad file path ../mag/sky130_fd_sc_hd__dfrtn_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfrtn_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand3_1" at bad file path ../mag/sky130_fd_sc_hd__nand3_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand3_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_16" at bad file path ../mag/sky130_fd_sc_hd__clkbuf_16.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_16.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o21bai_1" at bad file path ../mag/sky130_fd_sc_hd__o21bai_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21bai_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__inv_2" at bad file path ../mag/sky130_fd_sc_hd__inv_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor3b_2" at bad file path ../mag/sky130_fd_sc_hd__nor3b_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor3b_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfrtp_4" at bad file path ../mag/sky130_fd_sc_hd__dfrtp_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfrtp_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a21bo_1" at bad file path ../mag/sky130_fd_sc_hd__a21bo_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21bo_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__buf_12" at bad file path ../mag/sky130_fd_sc_hd__buf_12.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_12.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__xnor2_1" at bad file path ../mag/sky130_fd_sc_hd__xnor2_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__xnor2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand3b_1" at bad file path ../mag/sky130_fd_sc_hd__nand3b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand3b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkinv_4" at bad file path ../mag/sky130_fd_sc_hd__clkinv_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinv_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfxtp_1" at bad file path ../mag/sky130_fd_sc_hd__dfxtp_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfxtp_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o21ai_1" at bad file path ../mag/sky130_fd_sc_hd__o21ai_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21ai_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfstp_4" at bad file path ../mag/sky130_fd_sc_hd__dfstp_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfstp_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2bb2ai_2" at bad file path ../mag/sky130_fd_sc_hd__o2bb2ai_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2bb2ai_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a21o_1" at bad file path ../mag/sky130_fd_sc_hd__a21o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o21a_1" at bad file path ../mag/sky130_fd_sc_hd__o21a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkinv_2" at bad file path ../mag/sky130_fd_sc_hd__clkinv_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinv_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand2_2" at bad file path ../mag/sky130_fd_sc_hd__nand2_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand2_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o211a_1" at bad file path ../mag/sky130_fd_sc_hd__o211a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o211a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor3_1" at bad file path ../mag/sky130_fd_sc_hd__nor3_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor3_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and2_1" at bad file path ../mag/sky130_fd_sc_hd__and2_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfrtp_2" at bad file path ../mag/sky130_fd_sc_hd__dfrtp_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfrtp_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o211ai_4" at bad file path ../mag/sky130_fd_sc_hd__o211ai_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o211ai_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or2b_1" at bad file path ../mag/sky130_fd_sc_hd__or2b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or2b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_4" at bad file path ../mag/sky130_fd_sc_hd__clkbuf_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor3b_1" at bad file path ../mag/sky130_fd_sc_hd__nor3b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor3b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dlygate4sd1_1" at bad file path ../mag/sky130_fd_sc_hd__dlygate4sd1_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dlygate4sd1_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfstp_2" at bad file path ../mag/sky130_fd_sc_hd__dfstp_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfstp_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dlymetal6s2s_1" at bad file path ../mag/sky130_fd_sc_hd__dlymetal6s2s_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dlymetal6s2s_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "housekeeping" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/housekeeping.mag.
+The cell exists in the search paths at ../mag/housekeeping.mag.
+The discovered version will be used.
+housekeeping: 10000 rects
+housekeeping: 20000 rects
+housekeeping: 30000 rects
+housekeeping: 40000 rects
+housekeeping: 50000 rects
+housekeeping: 60000 rects
+housekeeping: 70000 rects
+housekeeping: 80000 rects
+housekeeping: 90000 rects
+housekeeping: 100000 rects
+housekeeping: 110000 rects
+housekeeping: 120000 rects
+housekeeping: 130000 rects
+housekeeping: 140000 rects
+housekeeping: 150000 rects
+housekeeping: 160000 rects
+housekeeping: 170000 rects
+housekeeping: 180000 rects
+housekeeping: 190000 rects
+housekeeping: 200000 rects
+housekeeping: 210000 rects
+housekeeping: 220000 rects
+housekeeping: 230000 rects
+housekeeping: 240000 rects
+housekeeping: 250000 rects
+housekeeping: 260000 rects
+housekeeping: 270000 rects
+housekeeping: 280000 rects
+housekeeping: 290000 rects
+housekeeping: 300000 rects
+housekeeping: 310000 rects
+housekeeping: 320000 rects
+housekeeping: 330000 rects
+housekeeping: 340000 rects
+housekeeping: 350000 rects
+housekeeping: 360000 rects
+housekeeping: 370000 rects
+housekeeping: 380000 rects
+housekeeping: 390000 rects
+housekeeping: 400000 rects
+housekeeping: 410000 rects
+housekeeping: 420000 rects
+housekeeping: 430000 rects
+housekeeping: 440000 rects
+housekeeping: 450000 rects
+housekeeping: 460000 rects
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__buf_4" at bad file path ../mag/sky130_fd_sc_hd__buf_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__buf_6" at bad file path ../mag/sky130_fd_sc_hd__buf_6.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_6.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__ebufn_8" at bad file path ../mag/sky130_fd_sc_hd__ebufn_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__ebufn_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkinv_8" at bad file path ../mag/sky130_fd_sc_hd__clkinv_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinv_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__inv_6" at bad file path ../mag/sky130_fd_sc_hd__inv_6.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_6.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a221o_1" at bad file path ../mag/sky130_fd_sc_hd__a221o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a221o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4bb_1" at bad file path ../mag/sky130_fd_sc_hd__or4bb_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4bb_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or2_1" at bad file path ../mag/sky130_fd_sc_hd__or2_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4b_1" at bad file path ../mag/sky130_fd_sc_hd__or4b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a32o_2" at bad file path ../mag/sky130_fd_sc_hd__a32o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a32o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o21ai_2" at bad file path ../mag/sky130_fd_sc_hd__o21ai_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21ai_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4_2" at bad file path ../mag/sky130_fd_sc_hd__or4_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4_1" at bad file path ../mag/sky130_fd_sc_hd__or4_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand4_1" at bad file path ../mag/sky130_fd_sc_hd__nand4_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand4bb_1" at bad file path ../mag/sky130_fd_sc_hd__nand4bb_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4bb_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o22a_2" at bad file path ../mag/sky130_fd_sc_hd__o22a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o22a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a22o_1" at bad file path ../mag/sky130_fd_sc_hd__a22o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a22o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or3_1" at bad file path ../mag/sky130_fd_sc_hd__or3_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or3_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o22a_1" at bad file path ../mag/sky130_fd_sc_hd__o22a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o22a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2bb2a_1" at bad file path ../mag/sky130_fd_sc_hd__o2bb2a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2bb2a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__inv_8" at bad file path ../mag/sky130_fd_sc_hd__inv_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or3_2" at bad file path ../mag/sky130_fd_sc_hd__or3_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or3_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or3_4" at bad file path ../mag/sky130_fd_sc_hd__or3_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or3_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__mux2_8" at bad file path ../mag/sky130_fd_sc_hd__mux2_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__mux2_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__buf_8" at bad file path ../mag/sky130_fd_sc_hd__buf_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a22oi_4" at bad file path ../mag/sky130_fd_sc_hd__a22oi_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a22oi_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or3b_1" at bad file path ../mag/sky130_fd_sc_hd__or3b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or3b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a2bb2o_1" at bad file path ../mag/sky130_fd_sc_hd__a2bb2o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a2bb2o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and3_1" at bad file path ../mag/sky130_fd_sc_hd__and3_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and3_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a211o_1" at bad file path ../mag/sky130_fd_sc_hd__a211o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a211o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a21oi_1" at bad file path ../mag/sky130_fd_sc_hd__a21oi_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21oi_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or2_4" at bad file path ../mag/sky130_fd_sc_hd__or2_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or2_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4bb_4" at bad file path ../mag/sky130_fd_sc_hd__or4bb_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4bb_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand2_4" at bad file path ../mag/sky130_fd_sc_hd__nand2_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand2_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o22ai_1" at bad file path ../mag/sky130_fd_sc_hd__o22ai_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o22ai_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o32a_1" at bad file path ../mag/sky130_fd_sc_hd__o32a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o32a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or2_2" at bad file path ../mag/sky130_fd_sc_hd__or2_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or2_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a21bo_2" at bad file path ../mag/sky130_fd_sc_hd__a21bo_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21bo_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__inv_12" at bad file path ../mag/sky130_fd_sc_hd__inv_12.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_12.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o31ai_4" at bad file path ../mag/sky130_fd_sc_hd__o31ai_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o31ai_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or2b_2" at bad file path ../mag/sky130_fd_sc_hd__or2b_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or2b_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkinvlp_2" at bad file path ../mag/sky130_fd_sc_hd__clkinvlp_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinvlp_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o32a_2" at bad file path ../mag/sky130_fd_sc_hd__o32a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o32a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a311o_1" at bad file path ../mag/sky130_fd_sc_hd__a311o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a311o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and4b_1" at bad file path ../mag/sky130_fd_sc_hd__and4b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o221a_1" at bad file path ../mag/sky130_fd_sc_hd__o221a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o221a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor3_4" at bad file path ../mag/sky130_fd_sc_hd__nor3_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor3_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4_4" at bad file path ../mag/sky130_fd_sc_hd__or4_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4b_2" at bad file path ../mag/sky130_fd_sc_hd__or4b_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4b_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor2_4" at bad file path ../mag/sky130_fd_sc_hd__nor2_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor2_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a21o_2" at bad file path ../mag/sky130_fd_sc_hd__a21o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a31o_1" at bad file path ../mag/sky130_fd_sc_hd__a31o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a31o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor4_1" at bad file path ../mag/sky130_fd_sc_hd__nor4_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor4_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a32o_1" at bad file path ../mag/sky130_fd_sc_hd__a32o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a32o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__ebufn_2" at bad file path ../mag/sky130_fd_sc_hd__ebufn_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__ebufn_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand2_8" at bad file path ../mag/sky130_fd_sc_hd__nand2_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand2_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor2_2" at bad file path ../mag/sky130_fd_sc_hd__nor2_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor2_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or3b_2" at bad file path ../mag/sky130_fd_sc_hd__or3b_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or3b_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_8" at bad file path ../mag/sky130_fd_sc_hd__clkbuf_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a22oi_1" at bad file path ../mag/sky130_fd_sc_hd__a22oi_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a22oi_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o221a_2" at bad file path ../mag/sky130_fd_sc_hd__o221a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o221a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__mux2_4" at bad file path ../mag/sky130_fd_sc_hd__mux2_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__mux2_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o211a_2" at bad file path ../mag/sky130_fd_sc_hd__o211a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o211a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a41o_1" at bad file path ../mag/sky130_fd_sc_hd__a41o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a41o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o22ai_4" at bad file path ../mag/sky130_fd_sc_hd__o22ai_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o22ai_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a41o_2" at bad file path ../mag/sky130_fd_sc_hd__a41o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a41o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a311oi_1" at bad file path ../mag/sky130_fd_sc_hd__a311oi_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a311oi_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o21ba_1" at bad file path ../mag/sky130_fd_sc_hd__o21ba_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21ba_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2111ai_1" at bad file path ../mag/sky130_fd_sc_hd__o2111ai_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2111ai_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o311a_1" at bad file path ../mag/sky130_fd_sc_hd__o311a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o311a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a211o_4" at bad file path ../mag/sky130_fd_sc_hd__a211o_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a211o_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o221ai_1" at bad file path ../mag/sky130_fd_sc_hd__o221ai_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o221ai_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and3_2" at bad file path ../mag/sky130_fd_sc_hd__and3_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and3_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o31a_1" at bad file path ../mag/sky130_fd_sc_hd__o31a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o31a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o22ai_2" at bad file path ../mag/sky130_fd_sc_hd__o22ai_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o22ai_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o22a_4" at bad file path ../mag/sky130_fd_sc_hd__o22a_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o22a_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o211ai_1" at bad file path ../mag/sky130_fd_sc_hd__o211ai_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o211ai_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o221ai_2" at bad file path ../mag/sky130_fd_sc_hd__o221ai_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o221ai_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2111ai_2" at bad file path ../mag/sky130_fd_sc_hd__o2111ai_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2111ai_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand3_4" at bad file path ../mag/sky130_fd_sc_hd__nand3_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand3_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2111ai_4" at bad file path ../mag/sky130_fd_sc_hd__o2111ai_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2111ai_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and4_1" at bad file path ../mag/sky130_fd_sc_hd__and4_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2111a_1" at bad file path ../mag/sky130_fd_sc_hd__o2111a_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2111a_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o221ai_4" at bad file path ../mag/sky130_fd_sc_hd__o221ai_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o221ai_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor4_2" at bad file path ../mag/sky130_fd_sc_hd__nor4_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor4_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a2111o_2" at bad file path ../mag/sky130_fd_sc_hd__a2111o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a2111o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and3_4" at bad file path ../mag/sky130_fd_sc_hd__and3_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and3_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and4bb_1" at bad file path ../mag/sky130_fd_sc_hd__and4bb_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4bb_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o211ai_2" at bad file path ../mag/sky130_fd_sc_hd__o211ai_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o211ai_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and4_2" at bad file path ../mag/sky130_fd_sc_hd__and4_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2111a_2" at bad file path ../mag/sky130_fd_sc_hd__o2111a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2111a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand4_4" at bad file path ../mag/sky130_fd_sc_hd__nand4_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand4b_4" at bad file path ../mag/sky130_fd_sc_hd__nand4b_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4b_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a311oi_2" at bad file path ../mag/sky130_fd_sc_hd__a311oi_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a311oi_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a2111o_1" at bad file path ../mag/sky130_fd_sc_hd__a2111o_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a2111o_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor3_2" at bad file path ../mag/sky130_fd_sc_hd__nor3_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor3_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nand4_2" at bad file path ../mag/sky130_fd_sc_hd__nand4_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o2bb2a_2" at bad file path ../mag/sky130_fd_sc_hd__o2bb2a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2bb2a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or4b_4" at bad file path ../mag/sky130_fd_sc_hd__or4b_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4b_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and3b_1" at bad file path ../mag/sky130_fd_sc_hd__and3b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and3b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a22o_2" at bad file path ../mag/sky130_fd_sc_hd__a22o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a22o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o221a_4" at bad file path ../mag/sky130_fd_sc_hd__o221a_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o221a_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__or3b_4" at bad file path ../mag/sky130_fd_sc_hd__or3b_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or3b_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o21ai_4" at bad file path ../mag/sky130_fd_sc_hd__o21ai_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21ai_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__nor2_8" at bad file path ../mag/sky130_fd_sc_hd__nor2_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor2_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and2b_1" at bad file path ../mag/sky130_fd_sc_hd__and2b_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2b_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o311a_2" at bad file path ../mag/sky130_fd_sc_hd__o311a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o311a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a31oi_1" at bad file path ../mag/sky130_fd_sc_hd__a31oi_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a31oi_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a221o_2" at bad file path ../mag/sky130_fd_sc_hd__a221o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a221o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "digital_pll" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/digital_pll.mag.
+The cell exists in the search paths at ../mag/digital_pll.mag.
+The discovered version will be used.
+digital_pll: 10000 rects
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvp_2" at bad file path ../mag/sky130_fd_sc_hd__einvp_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkinv_1" at bad file path ../mag/sky130_fd_sc_hd__clkinv_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinv_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvn_8" at bad file path ../mag/sky130_fd_sc_hd__einvn_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvn_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvn_4" at bad file path ../mag/sky130_fd_sc_hd__einvn_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvn_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o21a_2" at bad file path ../mag/sky130_fd_sc_hd__o21a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and2_2" at bad file path ../mag/sky130_fd_sc_hd__and2_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o31a_2" at bad file path ../mag/sky130_fd_sc_hd__o31a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o31a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__o41a_2" at bad file path ../mag/sky130_fd_sc_hd__o41a_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o41a_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a31o_2" at bad file path ../mag/sky130_fd_sc_hd__a31o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a31o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvp_1" at bad file path ../mag/sky130_fd_sc_hd__einvp_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a2bb2o_2" at bad file path ../mag/sky130_fd_sc_hd__a2bb2o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a2bb2o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a311o_2" at bad file path ../mag/sky130_fd_sc_hd__a311o_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a311o_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a21oi_2" at bad file path ../mag/sky130_fd_sc_hd__a21oi_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21oi_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__a22oi_2" at bad file path ../mag/sky130_fd_sc_hd__a22oi_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a22oi_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gpio_control_block" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_control_block.mag.
+The cell exists in the search paths at ../mag/gpio_control_block.mag.
+The discovered version will be used.
+gpio_control_block: 10000 rects
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfbbn_1" at bad file path ../mag/sky130_fd_sc_hd__dfbbn_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfbbn_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__ebufn_1" at bad file path ../mag/sky130_fd_sc_hd__ebufn_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__ebufn_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gpio_defaults_block_1803" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_1803.mag.
+The cell exists in the search paths at ../mag/gpio_defaults_block_1803.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "mgmt_protect" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/mgmt_protect.mag.
+The cell exists in the search paths at ../mag/mgmt_protect.mag.
+The discovered version will be used.
+mgmt_protect: 10000 rects
+mgmt_protect: 20000 rects
+mgmt_protect: 30000 rects
+mgmt_protect: 40000 rects
+mgmt_protect: 50000 rects
+mgmt_protect: 60000 rects
+mgmt_protect: 70000 rects
+mgmt_protect: 80000 rects
+mgmt_protect: 90000 rects
+mgmt_protect: 100000 rects
+mgmt_protect: 110000 rects
+mgmt_protect: 120000 rects
+mgmt_protect: 130000 rects
+mgmt_protect: 140000 rects
+mgmt_protect: 150000 rects
+mgmt_protect: 160000 rects
+mgmt_protect: 170000 rects
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvp_4" at bad file path ../mag/sky130_fd_sc_hd__einvp_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvp_8" at bad file path ../mag/sky130_fd_sc_hd__einvp_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and2_4" at bad file path ../mag/sky130_fd_sc_hd__and2_4.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__conb_1" at bad file path ../mag/sky130_fd_sc_hvl__conb_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__conb_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "spare_logic_block" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/spare_logic_block.mag.
+The cell exists in the search paths at ../mag/spare_logic_block.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfbbp_1" at bad file path ../mag/sky130_fd_sc_hd__dfbbp_1.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfbbp_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gpio_defaults_block_0403" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block_0403.mag.
+The cell exists in the search paths at ../mag/gpio_defaults_block_0403.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gpio_defaults_block" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/gpio_defaults_block.mag.
+The cell exists in the search paths at ../mag/gpio_defaults_block.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "chip_io" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/chip_io.mag.
+The cell exists in the search paths at ../mag/chip_io.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__corner_pad" at bad file path ../mag/sky130_ef_io__corner_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__corner_pad.mag.
+The discovered version will be used.
+sky130_fd_io__corner_bus_overlay: 10000 rects
+Warning:  Parent cell lists instance of "sky130_ef_io__com_bus_slice_20um" at bad file path ../mag/sky130_ef_io__com_bus_slice_20um.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__com_bus_slice_20um.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__com_bus_slice_10um" at bad file path ../mag/sky130_ef_io__com_bus_slice_10um.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__com_bus_slice_10um.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__com_bus_slice_5um" at bad file path ../mag/sky130_ef_io__com_bus_slice_5um.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__com_bus_slice_5um.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__com_bus_slice_1um" at bad file path ../mag/sky130_ef_io__com_bus_slice_1um.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__com_bus_slice_1um.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um" at bad file path ../mag/sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__vssa_hvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vssa_hvc_clamped_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vssa_hvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__top_ground_hvc_wpad: 10000 rects
+sky130_fd_io__top_ground_hvc_wpad: 20000 rects
+sky130_fd_io__top_ground_hvc_wpad: 30000 rects
+sky130_fd_io__top_ground_hvc_wpad: 40000 rects
+sky130_fd_io__top_ground_hvc_wpad: 50000 rects
+sky130_fd_io__top_ground_hvc_wpad: 60000 rects
+sky130_fd_io__top_ground_hvc_wpad: 70000 rects
+sky130_fd_io__top_ground_hvc_wpad: 80000 rects
+sky130_fd_io__top_ground_hvc_wpad: 90000 rects
+sky130_fd_io__top_ground_hvc_wpad: 100000 rects
+sky130_fd_io__top_ground_hvc_wpad: 110000 rects
+sky130_fd_io__top_ground_hvc_wpad: 120000 rects
+sky130_fd_io__top_ground_hvc_wpad: 130000 rects
+sky130_fd_io__top_ground_hvc_wpad: 140000 rects
+sky130_fd_io__top_ground_hvc_wpad: 150000 rects
+sky130_fd_io__top_ground_hvc_wpad: 160000 rects
+sky130_fd_io__top_ground_hvc_wpad: 170000 rects
+sky130_fd_io__top_ground_hvc_wpad: 180000 rects
+sky130_fd_io__top_ground_hvc_wpad: 190000 rects
+sky130_fd_io__top_ground_hvc_wpad: 200000 rects
+sky130_fd_io__top_ground_hvc_wpad: 210000 rects
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_5595914180851 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808336 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808666 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808678 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808679 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_5595914180839 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808660 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808663 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s__example_55959141808671 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s2__example_55959141808672 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808662 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808661 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s__example_55959141808675 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s2__example_55959141808676 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_559591418084 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__gendlring__example_559591418081 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__genrivetdlring__example_559591418082 geometry by factor of 2
+Warning:  Parent cell lists instance of "sky130_fd_io__top_xres4v2" at bad file path ../mag/sky130_fd_io__top_xres4v2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_fd_io__top_xres4v2.mag.
+The discovered version will be used.
+sky130_fd_io__top_xres4v2: 10000 rects
+sky130_fd_io__top_xres4v2: 20000 rects
+sky130_fd_io__top_xres4v2: 30000 rects
+sky130_fd_io__top_xres4v2: 40000 rects
+sky130_fd_io__top_xres4v2: 50000 rects
+sky130_fd_io__top_xres4v2: 60000 rects
+sky130_fd_io__top_xres4v2: 70000 rects
+sky130_fd_io__top_xres4v2: 80000 rects
+sky130_fd_io__top_xres4v2: 90000 rects
+sky130_fd_io__top_xres4v2: 100000 rects
+sky130_fd_io__top_xres4v2: 110000 rects
+sky130_fd_io__top_xres4v2: 120000 rects
+sky130_fd_io__top_xres4v2: 130000 rects
+sky130_fd_io__top_xres4v2: 140000 rects
+sky130_fd_io__top_xres4v2: 150000 rects
+sky130_fd_io__top_xres4v2: 160000 rects
+sky130_fd_io__top_xres4v2: 170000 rects
+sky130_fd_io__top_xres4v2: 180000 rects
+sky130_fd_io__top_xres4v2: 190000 rects
+sky130_fd_io__top_xres4v2: 200000 rects
+sky130_fd_io__top_xres4v2: 210000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808717 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808719 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180890 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808243 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808765 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_5595914180833 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808264 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180858 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180819 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808147 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808148 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808149 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808150 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808151 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808152 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808153 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808154 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808155 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808156 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808157 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808158 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808274 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808400 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808128 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808372 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808326 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808290 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808127 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180897 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808551 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808552 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808350 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808260 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808402 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808724 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808259 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808261 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808553 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808725 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808554 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808726 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808727 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808728 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_5595914180848 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180849 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808370 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808137 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_559591418086 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_559591418083 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808385 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_559591418088 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808316 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808612 geometry by factor of 2
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 10000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 20000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 30000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 40000 rects
+Scaled magic input cell sky130_fd_pr__hvdftpm1s2__example_55959141808659 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808202 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_5595914180811 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_5595914180812 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418084 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418086 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1_centered__example_559591418081 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m2m3__example_55959141808714 geometry by factor of 2
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 10000 rects
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 20000 rects
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 30000 rects
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 40000 rects
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808187 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808700 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808559 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808338 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808337 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808729 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808730 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808731 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808732 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808733 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808734 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808735 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808736 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808737 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808738 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808739 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808740 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808273 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808741 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808742 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808743 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808744 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808324 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808745 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808746 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808747 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808748 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808749 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808270 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808750 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808751 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808752 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180857 geometry by factor of 2
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 10000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 20000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 30000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 40000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 50000 rects
+Scaled magic input cell sky130_fd_pr__hvdftpl1s__example_55959141808646 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpm1s2__example_55959141808649 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808378 geometry by factor of 2
+sky130_fd_io__xres4v2_in_buf: 10000 rects
+sky130_fd_io__xres4v2_in_buf: 20000 rects
+sky130_fd_io__xres4v2_in_buf: 30000 rects
+sky130_fd_io__xres4v2_in_buf: 40000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180827 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808233 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808237 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180829 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808242 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_5595914180835 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808782 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808452 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808449 geometry by factor of 2
+Warning:  Parent cell lists instance of "sky130_ef_io__gpiov2_pad_wrapped" at bad file path ../mag/sky130_ef_io__gpiov2_pad_wrapped.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__gpiov2_pad_wrapped.mag.
+The discovered version will be used.
+sky130_fd_io__top_gpiov2: 10000 rects
+sky130_fd_io__top_gpiov2: 20000 rects
+sky130_fd_io__top_gpiov2: 30000 rects
+sky130_fd_io__top_gpiov2: 40000 rects
+sky130_fd_io__top_gpiov2: 50000 rects
+sky130_fd_io__top_gpiov2: 60000 rects
+sky130_fd_io__top_gpiov2: 70000 rects
+sky130_fd_io__top_gpiov2: 80000 rects
+sky130_fd_io__top_gpiov2: 90000 rects
+sky130_fd_io__gpiov2_amux: 10000 rects
+sky130_fd_io__gpiov2_amux: 20000 rects
+sky130_fd_io__gpiov2_amux: 30000 rects
+sky130_fd_io__amux_switch_1v2b: 10000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808251 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfm1sd2__example_55959141808561 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808563 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180868 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180869 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180875 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808122 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808123 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180884 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808100 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180815 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180823 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808106 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808510 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808504 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808581 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808418 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808140 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808278 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808462 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_5595914180894 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808200 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfm1sd__example_55959141808258 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808476 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808115 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180816 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808178 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808488 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808306 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808517 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808518 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180811 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808190 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808191 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180812 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808280 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808425 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808102 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808434 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808440 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180878 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808394 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808298 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808373 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808272 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808271 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808374 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808194 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808294 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808322 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808395 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808396 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808397 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808295 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808398 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808399 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808325 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808292 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808269 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808401 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808368 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808625 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808633 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808320 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808321 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808323 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808291 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808143 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_5595914180854 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808275 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808276 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808293 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808296 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808297 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808299 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808300 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808266 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808267 geometry by factor of 2
+sky130_fd_io__gpio_odrvr_subv2: 10000 rects
+sky130_fd_io__gpio_odrvr_subv2: 20000 rects
+sky130_fd_io__gpio_odrvr_subv2: 30000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270v2: 10000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270v2: 20000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270v2: 30000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418082 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418083 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808655 geometry by factor of 2
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 10000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 20000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 30000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 40000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418085 geometry by factor of 2
+sky130_fd_io__gpio_pddrvr_strong_slowv2: 10000 rects
+sky130_fd_io__gpio_pddrvr_strong_slowv2: 20000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180832 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1_centered__example_559591418080 geometry by factor of 2
+Warning:  Parent cell lists instance of "sky130_ef_io__vssd_lvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vssd_lvc_clamped_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vssd_lvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__top_ground_lvc_wpad: 10000 rects
+sky130_fd_io__top_ground_lvc_wpad: 20000 rects
+sky130_fd_io__top_ground_lvc_wpad: 30000 rects
+sky130_fd_io__top_ground_lvc_wpad: 40000 rects
+sky130_fd_io__top_ground_lvc_wpad: 50000 rects
+sky130_fd_io__top_ground_lvc_wpad: 60000 rects
+sky130_fd_io__top_ground_lvc_wpad: 70000 rects
+sky130_fd_io__top_ground_lvc_wpad: 80000 rects
+sky130_fd_io__top_ground_lvc_wpad: 90000 rects
+sky130_fd_io__top_ground_lvc_wpad: 100000 rects
+sky130_fd_io__top_ground_lvc_wpad: 110000 rects
+sky130_fd_io__top_ground_lvc_wpad: 120000 rects
+sky130_fd_io__top_ground_lvc_wpad: 130000 rects
+sky130_fd_io__top_ground_lvc_wpad: 140000 rects
+sky130_fd_io__top_ground_lvc_wpad: 150000 rects
+sky130_fd_io__top_ground_lvc_wpad: 160000 rects
+sky130_fd_io__top_ground_lvc_wpad: 170000 rects
+sky130_fd_io__top_ground_lvc_wpad: 180000 rects
+sky130_fd_io__top_ground_lvc_wpad: 190000 rects
+sky130_fd_io__top_ground_lvc_wpad: 200000 rects
+sky130_fd_io__top_ground_lvc_wpad: 210000 rects
+sky130_fd_io__top_ground_lvc_wpad: 220000 rects
+Scaled magic input cell sky130_fd_io__gnd2gnd_tap geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808683 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__gnd2gnd_diff geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808684 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808685 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808686 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dftpl1s2__example_55959141808702 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808682 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dftpl1s2__example_55959141808694 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808681 geometry by factor of 2
+Warning:  Parent cell lists instance of "sky130_ef_io__vssio_hvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vssio_hvc_clamped_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vssio_hvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__overlay_vssio_hvc: 10000 rects
+Warning:  Parent cell lists instance of "sky130_ef_io__vdda_hvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vdda_hvc_clamped_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vdda_hvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__hvc_clampv2: 10000 rects
+sky130_fd_io__hvc_clampv2: 20000 rects
+sky130_fd_io__hvc_clampv2: 30000 rects
+sky130_fd_io__hvc_clampv2: 40000 rects
+sky130_fd_io__hvc_clampv2: 50000 rects
+sky130_fd_io__hvc_clampv2: 60000 rects
+sky130_fd_io__hvc_clampv2: 70000 rects
+sky130_fd_io__hvc_clampv2: 80000 rects
+sky130_fd_io__hvc_clampv2: 90000 rects
+sky130_fd_io__hvc_clampv2: 100000 rects
+sky130_fd_io__hvc_clampv2: 110000 rects
+sky130_fd_io__hvc_clampv2: 120000 rects
+sky130_fd_io__hvc_clampv2: 130000 rects
+sky130_fd_io__hvc_clampv2: 140000 rects
+sky130_fd_io__hvc_clampv2: 150000 rects
+sky130_fd_io__hvc_clampv2: 160000 rects
+sky130_fd_io__hvc_clampv2: 170000 rects
+sky130_fd_io__hvc_clampv2: 180000 rects
+sky130_fd_io__hvc_clampv2: 190000 rects
+sky130_fd_io__hvc_clampv2: 200000 rects
+sky130_fd_io__hvc_clampv2: 210000 rects
+sky130_fd_io__hvc_clampv2: 220000 rects
+sky130_fd_io__hvc_clampv2: 230000 rects
+sky130_fd_io__hvc_clampv2: 240000 rects
+sky130_fd_io__hvc_clampv2: 250000 rects
+sky130_fd_io__hvc_clampv2: 260000 rects
+sky130_fd_io__hvc_clampv2: 270000 rects
+sky130_fd_io__hvc_clampv2: 280000 rects
+Warning:  Parent cell lists instance of "sky130_ef_io__vccd_lvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vccd_lvc_clamped_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vccd_lvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__top_power_lvc_wpad: 10000 rects
+sky130_fd_io__top_power_lvc_wpad: 20000 rects
+sky130_fd_io__top_power_lvc_wpad: 30000 rects
+sky130_fd_io__top_power_lvc_wpad: 40000 rects
+sky130_fd_io__top_power_lvc_wpad: 50000 rects
+sky130_fd_io__top_power_lvc_wpad: 60000 rects
+sky130_fd_io__top_power_lvc_wpad: 70000 rects
+sky130_fd_io__top_power_lvc_wpad: 80000 rects
+sky130_fd_io__top_power_lvc_wpad: 90000 rects
+sky130_fd_io__top_power_lvc_wpad: 100000 rects
+sky130_fd_io__top_power_lvc_wpad: 110000 rects
+sky130_fd_io__top_power_lvc_wpad: 120000 rects
+sky130_fd_io__top_power_lvc_wpad: 130000 rects
+sky130_fd_io__top_power_lvc_wpad: 140000 rects
+sky130_fd_io__top_power_lvc_wpad: 150000 rects
+sky130_fd_io__top_power_lvc_wpad: 160000 rects
+sky130_fd_io__top_power_lvc_wpad: 170000 rects
+sky130_fd_io__top_power_lvc_wpad: 180000 rects
+sky130_fd_io__top_power_lvc_wpad: 190000 rects
+sky130_fd_io__top_power_lvc_wpad: 200000 rects
+sky130_fd_io__top_power_lvc_wpad: 210000 rects
+sky130_fd_io__top_power_lvc_wpad: 220000 rects
+sky130_fd_io__top_power_lvc_wpad: 230000 rects
+Warning:  Parent cell lists instance of "sky130_ef_io__disconnect_vdda_slice_5um" at bad file path ../mag/sky130_ef_io__disconnect_vdda_slice_5um.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__disconnect_vdda_slice_5um.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__vddio_hvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vddio_hvc_clamped_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vddio_hvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__overlay_vddio_hvc: 10000 rects
+Warning:  Parent cell lists instance of "sky130_ef_io__vssd_lvc_clamped3_pad" at bad file path ../mag/sky130_ef_io__vssd_lvc_clamped3_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vssd_lvc_clamped3_pad.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_ef_io__vccd_lvc_clamped3_pad" at bad file path ../mag/sky130_ef_io__vccd_lvc_clamped3_pad.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vccd_lvc_clamped3_pad.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "caravel_power_routing" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/caravel_power_routing.mag.
+The cell exists in the search paths at ../mag/caravel_power_routing.mag.
+The discovered version will be used.
+Processing timestamp mismatches: caravel_power_routing, sky130_ef_io__vccd_lvc_clamped3_pad, sky130_ef_io__vssd_lvc_clamped3_pad, sky130_ef_io__vddio_hvc_clamped_pad, sky130_ef_io__disconnect_vdda_slice_5um, sky130_ef_io__vccd_lvc_clamped_pad, sky130_ef_io__vdda_hvc_clamped_pad, sky130_ef_io__vssio_hvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped_pad, sky130_ef_io__gpiov2_pad_wrapped, sky130_fd_io__top_xres4v2, sky130_ef_io__vssa_hvc_clamped_pad, sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um, sky130_ef_io__com_bus_slice_1um, sky130_ef_io__com_bus_slice_5um, sky130_ef_io__com_bus_slice_10um, sky130_ef_io__com_bus_slice_20um, sky130_ef_io__corner_pad, gpio_defaults_block, sky130_fd_sc_hd__decap_3, sky130_fd_sc_hd__fill_1, sky130_fd_sc_hd__decap_4, sky130_fd_sc_hd__tapvpwrvgnd_1, sky130_fd_sc_hd__decap_12, sky130_fd_sc_hd__conb_1, sky130_fd_sc_hd__fill_2, sky130_fd_sc_hd__decap_6, gpio_defaults_block_0403, sky130_fd_sc_hd__dfbbp_1, spare_logic_block, sky130_fd_sc_hd__inv_2, sky130_fd_sc_hd__nand2_2, sky130_fd_sc_hd__inv_8, sky130_fd_sc_hd__decap_8, sky130_fd_sc_hd__nor2_2, sky130_fd_sc_hd__mux2_2, gpio_defaults_block_1800, sky130_fd_sc_hvl__conb_1, sky130_fd_sc_hvl__lsbufhv2lv_1, sky130_fd_sc_hvl__fill_1, sky130_fd_sc_hvl__fill_2, sky130_fd_sc_hd__and2_4, sky130_fd_sc_hd__einvp_8, sky130_fd_sc_hd__einvp_4, sky130_fd_sc_hd__clkbuf_4, sky130_fd_sc_hd__diode_2, sky130_fd_sc_hd__buf_2, sky130_fd_sc_hd__clkbuf_1, sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__and2_1, sky130_fd_sc_hd__nand2_1, sky130_fd_sc_hd__inv_6, sky130_fd_sc_hd__nand2_4, sky130_fd_sc_hd__clkinv_8, sky130_fd_sc_hd__nand2_8, sky130_fd_sc_hd__einvp_2, sky130_fd_sc_hd__clkbuf_2, sky130_fd_sc_hd__buf_6, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__clkbuf_16, sky130_fd_sc_hd__buf_12, sky130_fd_sc_hd__clkinv_4, sky130_fd_sc_hd__and2b_1, sky130_fd_sc_hd__clkinv_2, sky130_fd_sc_hd__inv_4, sky130_fd_sc_hd__inv_12, sky130_fd_sc_hd__dlymetal6s2s_1, gpio_defaults_block_1803, sky130_fd_sc_hd__ebufn_1, sky130_fd_sc_hd__dfbbn_1, gpio_control_block, sky130_fd_sc_hd__or2_1, sky130_fd_sc_hd__or2b_1, sky130_fd_sc_hd__dfrtp_1, sky130_fd_sc_hd__buf_1, sky130_fd_sc_hd__clkdlybuf4s25_1, sky130_fd_sc_hd__mux2_1, sky130_fd_sc_hd__a22oi_2, sky130_fd_sc_hd__a21oi_2, sky130_fd_sc_hd__a311o_2, sky130_fd_sc_hd__a2bb2o_2, sky130_fd_sc_hd__einvp_1, sky130_fd_sc_hd__a31o_2, sky130_fd_sc_hd__o41a_2, sky130_fd_sc_hd__o31a_2, sky130_fd_sc_hd__and2_2, sky130_fd_sc_hd__o21a_2, sky130_fd_sc_hd__einvn_4, sky130_fd_sc_hd__einvn_8, sky130_fd_sc_hd__clkinv_1, digital_pll, sky130_fd_sc_hd__o311a_2, sky130_fd_sc_hd__or2_2, sky130_fd_sc_hd__or3_2, sky130_fd_sc_hd__or4_2, sky130_fd_sc_hd__and3_2, sky130_fd_sc_hd__o21ai_2, sky130_fd_sc_hd__o32a_2, sky130_fd_sc_hd__a32o_2, sky130_fd_sc_hd__a22o_2, sky130_fd_sc_hd__o2bb2a_2, sky130_fd_sc_hd__o211a_2, sky130_fd_sc_hd__a221o_2, sky130_fd_sc_hd__o22a_2, sky130_fd_sc_hd__dfrtp_2, sky130_fd_sc_hd__o221ai_2, sky130_fd_sc_hd__o22ai_2, sky130_fd_sc_hd__o221a_2, sky130_fd_sc_hd__a21bo_2, sky130_fd_sc_hd__a21o_2, sky130_fd_sc_hd__and4_2, sky130_fd_sc_hd__o2111ai_2, sky130_fd_sc_hd__o2bb2ai_2, sky130_fd_sc_hd__a31oi_1, sky130_fd_sc_hd__nor2_8, sky130_fd_sc_hd__o21ai_4, sky130_fd_sc_hd__or3b_4, sky130_fd_sc_hd__o221a_4, sky130_fd_sc_hd__and3b_1, sky130_fd_sc_hd__or4b_4, sky130_fd_sc_hd__nand4_2, sky130_fd_sc_hd__nor3_2, sky130_fd_sc_hd__a2111o_1, sky130_fd_sc_hd__a311oi_2, sky130_fd_sc_hd__nand4b_4, sky130_fd_sc_hd__nand4_4, sky130_fd_sc_hd__o2111a_2, sky130_fd_sc_hd__o211ai_2, sky130_fd_sc_hd__and4bb_1, sky130_fd_sc_hd__and3_4, sky130_fd_sc_hd__a2111o_2, sky130_fd_sc_hd__nor4_2, sky130_fd_sc_hd__o221ai_4, sky130_fd_sc_hd__o2111a_1, sky130_fd_sc_hd__and4_1, sky130_fd_sc_hd__o2111ai_4, sky130_fd_sc_hd__nand3_4, sky130_fd_sc_hd__o211ai_1, sky130_fd_sc_hd__o22a_4, sky130_fd_sc_hd__o31a_1, sky130_fd_sc_hd__o221ai_1, sky130_fd_sc_hd__a211o_4, sky130_fd_sc_hd__o311a_1, sky130_fd_sc_hd__o2111ai_1, sky130_fd_sc_hd__o21ba_1, sky130_fd_sc_hd__a311oi_1, sky130_fd_sc_hd__a41o_2, sky130_fd_sc_hd__o22ai_4, sky130_fd_sc_hd__a41o_1, sky130_fd_sc_hd__mux2_4, sky130_fd_sc_hd__a22oi_1, sky130_fd_sc_hd__clkbuf_8, sky130_fd_sc_hd__or3b_2, sky130_fd_sc_hd__ebufn_2, sky130_fd_sc_hd__a32o_1, sky130_fd_sc_hd__nor4_1, sky130_fd_sc_hd__a31o_1, sky130_fd_sc_hd__nor2_4, sky130_fd_sc_hd__or4b_2, sky130_fd_sc_hd__or4_4, sky130_fd_sc_hd__nor3_4, sky130_fd_sc_hd__o221a_1, sky130_fd_sc_hd__and4b_1, sky130_fd_sc_hd__a311o_1, sky130_fd_sc_hd__clkinvlp_2, sky130_fd_sc_hd__or2b_2, sky130_fd_sc_hd__o31ai_4, sky130_fd_sc_hd__o32a_1, sky130_fd_sc_hd__o22ai_1, sky130_fd_sc_hd__or4bb_4, sky130_fd_sc_hd__or2_4, sky130_fd_sc_hd__a21oi_1, sky130_fd_sc_hd__a211o_1, sky130_fd_sc_hd__and3_1, sky130_fd_sc_hd__a2bb2o_1, sky130_fd_sc_hd__or3b_1, sky130_fd_sc_hd__a22oi_4, sky130_fd_sc_hd__mux2_8, sky130_fd_sc_hd__or3_4, sky130_fd_sc_hd__o2bb2a_1, sky130_fd_sc_hd__o22a_1, sky130_fd_sc_hd__or3_1, sky130_fd_sc_hd__a22o_1, sky130_fd_sc_hd__nand4bb_1, sky130_fd_sc_hd__nand4_1, sky130_fd_sc_hd__or4_1, sky130_fd_sc_hd__or4b_1, sky130_fd_sc_hd__or4bb_1, sky130_fd_sc_hd__a221o_1, sky130_fd_sc_hd__ebufn_8, housekeeping, sky130_fd_sc_hd__dfstp_1, sky130_fd_sc_hd__dfrtp_4, sky130_fd_sc_hd__dfxtp_1, sky130_fd_sc_hd__o21a_1, sky130_fd_sc_hd__nor2_1, sky130_fd_sc_hd__a21bo_1, sky130_fd_sc_hd__nor3_1, sky130_fd_sc_hd__o21ai_1, sky130_fd_sc_hd__nand3b_1, sky130_fd_sc_hd__o21bai_1, sky130_fd_sc_hd__a21o_1, sky130_fd_sc_hd__o211ai_4, sky130_fd_sc_hd__o211a_1, sky130_fd_sc_hd__dfrtn_1, sky130_fd_sc_hd__dfstp_2, sky130_fd_sc_hd__dfstp_4, sky130_fd_sc_hd__dlygate4sd1_1, sky130_fd_sc_hd__nor3b_1, sky130_fd_sc_hd__xnor2_1, sky130_fd_sc_hd__nor3b_2, sky130_fd_sc_hd__nand3_1, sky130_fd_sc_hd__xor2_1, caravel_clocking, alpha_5, alpha_2, sky130_fd_sc_hvl__decap_4, sky130_fd_sc_hvl__diode_2, sky130_fd_sc_hvl__decap_8, xres_buf, open_source, caravel_logo.
+   Generating output for cell caravel_logo
+   Generating output for cell open_source
+   Generating output for cell sky130_fd_sc_hvl__decap_8
+   Generating output for cell sky130_fd_sc_hvl__diode_2
+   Generating output for cell sky130_fd_sc_hvl__decap_4
+   Generating output for cell sky130_fd_sc_hvl__fill_2
+   Generating output for cell sky130_fd_sc_hvl__fill_1
+   Generating output for cell sky130_fd_sc_hvl__lsbufhv2lv_1
+   Generating output for cell xres_buf
+   Generating output for cell font_22
+   Generating output for cell font_73
+   Generating output for cell font_43
+   Generating output for cell font_49
+   Generating output for cell font_65
+   Generating output for cell font_68
+   Generating output for cell font_54
+   Generating output for cell font_67
+   Generating output for cell font_6E
+   Generating output for cell font_69
+   Generating output for cell font_6C
+   Generating output for cell font_61
+   Generating output for cell font_53
+   Generating output for cell caravel_motto
+   Generating output for cell alpha_2
+   Generating output for cell alpha_5
+   Generating output for cell alpha_0
+   Generating output for cell user_id_textblock
+   Generating output for cell font_62
+   Generating output for cell font_66
+   Generating output for cell font_29
+   Generating output for cell font_20
+   Generating output for cell font_28
+   Generating output for cell font_33
+   Generating output for cell font_56
+   Generating output for cell font_76
+   Generating output for cell font_72
+   Generating output for cell font_2D
+   Generating output for cell font_4B
+   Generating output for cell font_44
+   Generating output for cell font_50
+   Generating output for cell font_70
+   Generating output for cell font_6F
+   Generating output for cell font_74
+   Generating output for cell font_57
+   Generating output for cell font_6B
+   Generating output for cell font_79
+   Generating output for cell font_47
+   Generating output for cell font_31
+   Generating output for cell font_32
+   Generating output for cell font_30
+   Generating output for cell font_6D
+   Generating output for cell font_4E
+   Generating output for cell copyright_block
+   Generating output for cell sky130_fd_sc_hd__xor2_1
+   Generating output for cell sky130_fd_sc_hd__nand3_1
+   Generating output for cell sky130_fd_sc_hd__nor3b_2
+   Generating output for cell sky130_fd_sc_hd__xnor2_1
+   Generating output for cell sky130_fd_sc_hd__nor3b_1
+   Generating output for cell sky130_fd_sc_hd__dlygate4sd1_1
+   Generating output for cell sky130_fd_sc_hd__dfstp_4
+   Generating output for cell sky130_fd_sc_hd__dfstp_2
+   Generating output for cell sky130_fd_sc_hd__dfrtn_1
+   Generating output for cell sky130_fd_sc_hd__o211a_1
+   Generating output for cell sky130_fd_sc_hd__o211ai_4
+   Generating output for cell sky130_fd_sc_hd__a21o_1
+   Generating output for cell sky130_fd_sc_hd__o21bai_1
+   Generating output for cell sky130_fd_sc_hd__nand3b_1
+   Generating output for cell sky130_fd_sc_hd__o21ai_1
+   Generating output for cell sky130_fd_sc_hd__nor3_1
+   Generating output for cell sky130_fd_sc_hd__a21bo_1
+   Generating output for cell sky130_fd_sc_hd__nor2_1
+   Generating output for cell sky130_fd_sc_hd__o21a_1
+   Generating output for cell sky130_fd_sc_hd__dfxtp_1
+   Generating output for cell sky130_fd_sc_hd__dfrtp_4
+   Generating output for cell sky130_fd_sc_hd__dfstp_1
+   Generating output for cell sky130_fd_sc_hd__o2bb2ai_2
+   Generating output for cell sky130_fd_sc_hd__dfrtp_2
+   Generating output for cell sky130_fd_sc_hd__mux2_1
+   Generating output for cell sky130_fd_sc_hd__clkdlybuf4s25_1
+   Generating output for cell sky130_fd_sc_hd__buf_1
+   Generating output for cell sky130_fd_sc_hd__dfrtp_1
+   Generating output for cell sky130_fd_sc_hd__or2b_1
+   Generating output for cell sky130_fd_sc_hd__dlymetal6s2s_1
+   Generating output for cell sky130_fd_sc_hd__inv_4
+   Generating output for cell sky130_fd_sc_hd__clkinv_2
+   Generating output for cell sky130_fd_sc_hd__clkinv_4
+   Generating output for cell sky130_fd_sc_hd__buf_12
+   Generating output for cell sky130_fd_sc_hd__clkbuf_16
+   Generating output for cell sky130_fd_sc_hd__clkbuf_2
+   Generating output for cell sky130_fd_sc_hd__nand2_1
+   Generating output for cell sky130_fd_sc_hd__and2_1
+   Generating output for cell sky130_fd_sc_hd__clkbuf_1
+   Generating output for cell sky130_fd_sc_hd__buf_2
+   Generating output for cell sky130_fd_sc_hd__diode_2
+   Generating output for cell sky130_fd_sc_hd__clkbuf_4
+   Generating output for cell sky130_fd_sc_hd__mux2_2
+   Generating output for cell sky130_fd_sc_hd__decap_8
+   Generating output for cell sky130_fd_sc_hd__nand2_2
+   Generating output for cell sky130_fd_sc_hd__inv_2
+   Generating output for cell sky130_fd_sc_hd__decap_6
+   Generating output for cell sky130_fd_sc_hd__fill_2
+   Generating output for cell sky130_fd_sc_hd__conb_1
+   Generating output for cell sky130_fd_sc_hd__decap_12
+   Generating output for cell sky130_fd_sc_hd__tapvpwrvgnd_1
+   Generating output for cell sky130_fd_sc_hd__decap_4
+   Generating output for cell sky130_fd_sc_hd__fill_1
+   Generating output for cell sky130_fd_sc_hd__decap_3
+   Generating output for cell caravel_clocking
+   Generating output for cell sky130_fd_sc_hd__ebufn_8
+   Generating output for cell sky130_fd_sc_hd__a221o_1
+   Generating output for cell sky130_fd_sc_hd__or4bb_1
+   Generating output for cell sky130_fd_sc_hd__or4b_1
+   Generating output for cell sky130_fd_sc_hd__or4_1
+   Generating output for cell sky130_fd_sc_hd__nand4_1
+   Generating output for cell sky130_fd_sc_hd__nand4bb_1
+   Generating output for cell sky130_fd_sc_hd__a22o_1
+   Generating output for cell sky130_fd_sc_hd__or3_1
+   Generating output for cell sky130_fd_sc_hd__o22a_1
+   Generating output for cell sky130_fd_sc_hd__o2bb2a_1
+   Generating output for cell sky130_fd_sc_hd__or3_4
+   Generating output for cell sky130_fd_sc_hd__mux2_8
+   Generating output for cell sky130_fd_sc_hd__a22oi_4
+   Generating output for cell sky130_fd_sc_hd__or3b_1
+   Generating output for cell sky130_fd_sc_hd__a2bb2o_1
+   Generating output for cell sky130_fd_sc_hd__and3_1
+   Generating output for cell sky130_fd_sc_hd__a211o_1
+   Generating output for cell sky130_fd_sc_hd__a21oi_1
+   Generating output for cell sky130_fd_sc_hd__or2_4
+   Generating output for cell sky130_fd_sc_hd__or4bb_4
+   Generating output for cell sky130_fd_sc_hd__o22ai_1
+   Generating output for cell sky130_fd_sc_hd__o32a_1
+   Generating output for cell sky130_fd_sc_hd__o31ai_4
+   Generating output for cell sky130_fd_sc_hd__or2b_2
+   Generating output for cell sky130_fd_sc_hd__clkinvlp_2
+   Generating output for cell sky130_fd_sc_hd__a311o_1
+   Generating output for cell sky130_fd_sc_hd__and4b_1
+   Generating output for cell sky130_fd_sc_hd__o221a_1
+   Generating output for cell sky130_fd_sc_hd__nor3_4
+   Generating output for cell sky130_fd_sc_hd__or4_4
+   Generating output for cell sky130_fd_sc_hd__or4b_2
+   Generating output for cell sky130_fd_sc_hd__nor2_4
+   Generating output for cell sky130_fd_sc_hd__a31o_1
+   Generating output for cell sky130_fd_sc_hd__nor4_1
+   Generating output for cell sky130_fd_sc_hd__a32o_1
+   Generating output for cell sky130_fd_sc_hd__ebufn_2
+   Generating output for cell sky130_fd_sc_hd__or3b_2
+   Generating output for cell sky130_fd_sc_hd__clkbuf_8
+   Generating output for cell sky130_fd_sc_hd__a22oi_1
+   Generating output for cell sky130_fd_sc_hd__mux2_4
+   Generating output for cell sky130_fd_sc_hd__a41o_1
+   Generating output for cell sky130_fd_sc_hd__o22ai_4
+   Generating output for cell sky130_fd_sc_hd__a41o_2
+   Generating output for cell sky130_fd_sc_hd__a311oi_1
+   Generating output for cell sky130_fd_sc_hd__o21ba_1
+   Generating output for cell sky130_fd_sc_hd__o2111ai_1
+   Generating output for cell sky130_fd_sc_hd__o311a_1
+   Generating output for cell sky130_fd_sc_hd__a211o_4
+   Generating output for cell sky130_fd_sc_hd__o221ai_1
+   Generating output for cell sky130_fd_sc_hd__o31a_1
+   Generating output for cell sky130_fd_sc_hd__o22a_4
+   Generating output for cell sky130_fd_sc_hd__o211ai_1
+   Generating output for cell sky130_fd_sc_hd__nand3_4
+   Generating output for cell sky130_fd_sc_hd__o2111ai_4
+   Generating output for cell sky130_fd_sc_hd__and4_1
+   Generating output for cell sky130_fd_sc_hd__o2111a_1
+   Generating output for cell sky130_fd_sc_hd__o221ai_4
+   Generating output for cell sky130_fd_sc_hd__nor4_2
+   Generating output for cell sky130_fd_sc_hd__a2111o_2
+   Generating output for cell sky130_fd_sc_hd__and3_4
+   Generating output for cell sky130_fd_sc_hd__and4bb_1
+   Generating output for cell sky130_fd_sc_hd__o211ai_2
+   Generating output for cell sky130_fd_sc_hd__o2111a_2
+   Generating output for cell sky130_fd_sc_hd__nand4_4
+   Generating output for cell sky130_fd_sc_hd__nand4b_4
+   Generating output for cell sky130_fd_sc_hd__a311oi_2
+   Generating output for cell sky130_fd_sc_hd__a2111o_1
+   Generating output for cell sky130_fd_sc_hd__nor3_2
+   Generating output for cell sky130_fd_sc_hd__nand4_2
+   Generating output for cell sky130_fd_sc_hd__or4b_4
+   Generating output for cell sky130_fd_sc_hd__and3b_1
+   Generating output for cell sky130_fd_sc_hd__o221a_4
+   Generating output for cell sky130_fd_sc_hd__or3b_4
+   Generating output for cell sky130_fd_sc_hd__o21ai_4
+   Generating output for cell sky130_fd_sc_hd__nor2_8
+   Generating output for cell sky130_fd_sc_hd__a31oi_1
+   Generating output for cell sky130_fd_sc_hd__o2111ai_2
+   Generating output for cell sky130_fd_sc_hd__and4_2
+   Generating output for cell sky130_fd_sc_hd__a21o_2
+   Generating output for cell sky130_fd_sc_hd__a21bo_2
+   Generating output for cell sky130_fd_sc_hd__o221a_2
+   Generating output for cell sky130_fd_sc_hd__o22ai_2
+   Generating output for cell sky130_fd_sc_hd__o221ai_2
+   Generating output for cell sky130_fd_sc_hd__o22a_2
+   Generating output for cell sky130_fd_sc_hd__a221o_2
+   Generating output for cell sky130_fd_sc_hd__o211a_2
+   Generating output for cell sky130_fd_sc_hd__o2bb2a_2
+   Generating output for cell sky130_fd_sc_hd__a22o_2
+   Generating output for cell sky130_fd_sc_hd__a32o_2
+   Generating output for cell sky130_fd_sc_hd__o32a_2
+   Generating output for cell sky130_fd_sc_hd__o21ai_2
+   Generating output for cell sky130_fd_sc_hd__and3_2
+   Generating output for cell sky130_fd_sc_hd__or4_2
+   Generating output for cell sky130_fd_sc_hd__or3_2
+   Generating output for cell sky130_fd_sc_hd__or2_2
+   Generating output for cell sky130_fd_sc_hd__o311a_2
+   Generating output for cell sky130_fd_sc_hd__or2_1
+   Generating output for cell sky130_fd_sc_hd__inv_12
+   Generating output for cell sky130_fd_sc_hd__and2b_1
+   Generating output for cell sky130_fd_sc_hd__buf_8
+   Generating output for cell sky130_fd_sc_hd__buf_6
+   Generating output for cell sky130_fd_sc_hd__nand2_8
+   Generating output for cell sky130_fd_sc_hd__clkinv_8
+   Generating output for cell sky130_fd_sc_hd__nand2_4
+   Generating output for cell sky130_fd_sc_hd__inv_6
+   Generating output for cell sky130_fd_sc_hd__buf_4
+   Generating output for cell sky130_fd_sc_hd__nor2_2
+   Generating output for cell sky130_fd_sc_hd__inv_8
+   Generating output for cell housekeeping
+   Generating output for cell sky130_fd_sc_hd__clkinv_1
+   Generating output for cell sky130_fd_sc_hd__einvn_8
+   Generating output for cell sky130_fd_sc_hd__einvn_4
+   Generating output for cell sky130_fd_sc_hd__o21a_2
+   Generating output for cell sky130_fd_sc_hd__and2_2
+   Generating output for cell sky130_fd_sc_hd__o31a_2
+   Generating output for cell sky130_fd_sc_hd__o41a_2
+   Generating output for cell sky130_fd_sc_hd__a31o_2
+   Generating output for cell sky130_fd_sc_hd__einvp_1
+   Generating output for cell sky130_fd_sc_hd__a2bb2o_2
+   Generating output for cell sky130_fd_sc_hd__a311o_2
+   Generating output for cell sky130_fd_sc_hd__a21oi_2
+   Generating output for cell sky130_fd_sc_hd__a22oi_2
+   Generating output for cell sky130_fd_sc_hd__einvp_2
+   Generating output for cell digital_pll
+   Generating output for cell sky130_fd_sc_hd__dfbbn_1
+   Generating output for cell sky130_fd_sc_hd__ebufn_1
+   Generating output for cell gpio_logic_high
+   Generating output for cell gpio_control_block
+   Generating output for cell gpio_defaults_block_1803
+   Generating output for cell simple_por
+Reading "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "sky130_fd_sc_hvl__schmittbuf_1".
+Reading "sky130_fd_sc_hvl__buf_8".
+Reading "sky130_fd_sc_hvl__fill_4".
+Reading "sky130_fd_sc_hvl__inv_8".
+Reading "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "simple_por".
+   Generating output for cell user_id_programming
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "user_id_programming".
+   Generating output for cell mgmt_core_wrapper
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__ebufn_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__inv_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "DFFRAM".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__a41oi_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__o41ai_1".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__o2111a_4".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__nor2b_2".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__a32oi_2".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__nor2b_4".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__o311ai_1".
+Reading "sky130_fd_sc_hd__a41oi_2".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__clkinv_16".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__o311ai_4".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__a221oi_2".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__a32oi_1".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__o311ai_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__o41ai_4".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_4".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__a2bb2oi_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__o32ai_4".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+Reading "sky130_fd_sc_hd__inv_16".
+Reading "sky130_fd_sc_hd__o41ai_2".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "mgmt_core".
+Reading "mgmt_core_wrapper".
+   Generating output for cell gpio_defaults_block_1800
+   Generating output for cell sky130_fd_sc_hd__dfbbp_1
+   Generating output for cell spare_logic_block
+   Generating output for cell sky130_fd_sc_hd__einvp_4
+   Generating output for cell sky130_fd_sc_hd__einvp_8
+   Generating output for cell sky130_fd_sc_hd__and2_4
+   Generating output for cell sky130_fd_sc_hvl__conb_1
+   Generating output for cell mgmt_protect_hv
+   Generating output for cell mprj_logic_high
+   Generating output for cell mprj2_logic_high
+   Generating output for cell mgmt_protect
+   Generating output for cell gpio_defaults_block_0403
+   Generating output for cell gpio_defaults_block
+   Generating output for cell gpio_control_power_routing_right
+   Generating output for cell gpio_control_power_routing_top
+   Generating output for cell gpio_control_power_routing
+   Generating output for cell caravel_power_routing
+   Generating output for cell sky130_fd_io__corner_bus_overlay
+   Generating output for cell sky130_ef_io__corner_pad
+   Generating output for cell sky130_ef_io__com_bus_slice_20um
+   Generating output for cell sky130_ef_io__com_bus_slice_10um
+   Generating output for cell sky130_ef_io__com_bus_slice_5um
+   Generating output for cell sky130_ef_io__com_bus_slice_1um
+   Generating output for cell sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um
+   Generating output for cell sky130_ef_io__hvc_vdda_overlay
+   Generating output for cell sky130_fd_io__com_bus_slice
+   Generating output for cell sky130_fd_io__com_bus_hookup
+   Generating output for cell sky130_fd_io__overlay_vssa_hvc
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_5595914180851
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808664
+   Generating output for cell sky130_fd_io__sio_clamp_pcap_4x5
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808680
+   Generating output for cell sky130_fd_io__esd_rcclamp_nfetcap
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808336
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808666
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808665
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808678
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808679
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808677
+   Generating output for cell sky130_fd_pr__via_pol1__example_5595914180839
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808667
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808660
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808663
+   Generating output for cell sky130_fd_pr__hvdftpl1s__example_55959141808671
+   Generating output for cell sky130_fd_pr__hvdftpl1s2__example_55959141808672
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808673
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808668
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808670
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808662
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808661
+   Generating output for cell sky130_fd_pr__hvdftpl1s__example_55959141808675
+   Generating output for cell sky130_fd_pr__hvdftpl1s2__example_55959141808676
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808674
+   Generating output for cell sky130_fd_pr__via_l1m1__example_559591418084
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808669
+   Generating output for cell sky130_fd_pr__gendlring__example_559591418081
+   Generating output for cell sky130_fd_pr__genrivetdlring__example_559591418082
+   Generating output for cell sky130_fd_pr__padplhp__example_559591418080
+   Generating output for cell sky130_fd_io__pad_esd
+   Generating output for cell sky130_fd_io__com_busses_esd
+   Generating output for cell sky130_fd_io__top_ground_hvc_wpad
+   Generating output for cell sky130_ef_io__vssa_hvc_clamped_pad
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808717
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808716
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808719
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808718
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808720
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180890
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808721
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808243
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808722
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808723
+   Generating output for cell sky130_fd_io__xres_inv_hysv2
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180838
+   Generating output for cell sky130_fd_io__tk_tie_r_out_esd
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808765
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808764
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808767
+   Generating output for cell sky130_fd_io__res250_sub_small
+   Generating output for cell sky130_fd_io__res250only_small
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808289
+   Generating output for cell sky130_fd_pr__via_pol1__example_5595914180833
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808715
+   Generating output for cell sky130_fd_pr__res_bent_po__example_5595914180862
+   Generating output for cell sky130_fd_pr__res_bent_po__example_5595914180863
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_55959141808288
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180859
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180864
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808264
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180858
+   Generating output for cell sky130_fd_io__com_res_weak_v2
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180819
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808555
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808147
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808148
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808149
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808150
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808151
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808152
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808153
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808154
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808155
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808156
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808157
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808158
+   Generating output for cell sky130_fd_io__signal_5_sym_hv_local_5term
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808274
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808400
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808128
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808372
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808326
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808290
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808127
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180897
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808551
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808552
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808350
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808260
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808402
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808724
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808259
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808261
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808553
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808725
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808554
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808726
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808727
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808728
+   Generating output for cell sky130_fd_io__gpio_buf_localesdv2
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_5595914180848
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180849
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808766
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808370
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808369
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808137
+   Generating output for cell sky130_fd_pr__dfl1sd__example_559591418086
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808371
+   Generating output for cell sky130_fd_pr__via_pol1__example_559591418083
+   Generating output for cell sky130_fd_io__hvsbt_inv_x1
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808385
+   Generating output for cell sky130_fd_pr__dfl1sd__example_559591418088
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808615
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808316
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808616
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808612
+   Generating output for cell sky130_fd_io__hvsbt_inv_x4
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808422
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808421
+   Generating output for cell sky130_fd_io__hvsbt_inv_x2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808657
+   Generating output for cell sky130_fd_pr__hvdftpm1s2__example_55959141808659
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808658
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808202
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_5595914180811
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_5595914180812
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418084
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418086
+   Generating output for cell sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2
+   Generating output for cell sky130_fd_io__tk_em2o_cdns_55959141808653
+   Generating output for cell sky130_fd_io__tk_em2s_cdns_55959141808652
+   Generating output for cell sky130_fd_pr__via_pol1_centered__example_559591418081
+   Generating output for cell sky130_fd_io__gpio_pudrvr_strong_axres4v2
+   Generating output for cell sky130_fd_pr__via_m2m3__example_55959141808714
+   Generating output for cell sky130_fd_io__xres_p_em1c_cdns_55959141808753
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808187
+   Generating output for cell sky130_fd_pr__res_generic_nd__example_55959141808754
+   Generating output for cell sky130_fd_pr__res_generic_nd__example_55959141808755
+   Generating output for cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756
+   Generating output for cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757
+   Generating output for cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758
+   Generating output for cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759
+   Generating output for cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760
+   Generating output for cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808700
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808559
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808762
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808338
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808337
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808763
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808729
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808730
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808731
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808732
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808733
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808734
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808735
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808736
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808737
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808738
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808739
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808740
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808273
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808741
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808742
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808743
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808744
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808324
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808745
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808746
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808747
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808748
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808749
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808270
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808750
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808751
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808752
+   Generating output for cell sky130_fd_io__xres2v2_rcfilter_lpfv2
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_5595914180860
+   Generating output for cell sky130_fd_pr__res_bent_po__example_5595914180861
+   Generating output for cell sky130_fd_io__com_res_weak_bentbigres
+   Generating output for cell sky130_fd_io__com_res_weak
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180857
+   Generating output for cell sky130_fd_pr__hvdftpl1s__example_55959141808646
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808645
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808647
+   Generating output for cell sky130_fd_pr__hvdftpm1s2__example_55959141808649
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808648
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808650
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808651
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808378
+   Generating output for cell sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2
+   Generating output for cell sky130_fd_io__gpio_pddrvr_strong_xres4v2
+   Generating output for cell sky130_fd_io__top_gpio_pad
+   Generating output for cell sky130_fd_io__com_busses
+   Generating output for cell sky130_fd_io__tap_1
+   Generating output for cell sky130_fd_io__inv_1
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808768
+   Generating output for cell sky130_fd_pr__res_bent_nd__example_55959141808769
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_559591418085
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_559591418087
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_559591418089
+   Generating output for cell sky130_fd_io__hvsbt_nand2
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180827
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808770
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808233
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808771
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808237
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180829
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808772
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808773
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808242
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808774
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808775
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808776
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_5595914180835
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808777
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808778
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808779
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808780
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808782
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808781
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808452
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808783
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808449
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808784
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808785
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808786
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808787
+   Generating output for cell sky130_fd_io__xres4v2_in_buf
+   Generating output for cell sky130_fd_io__top_xres4v2
+   Generating output for cell sky130_fd_io__com_bus_slice_m4
+   Generating output for cell sky130_fd_io__overlay_gpiov2_m4
+   Generating output for cell sky130_fd_io__overlay_gpiov2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808558
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808251
+   Generating output for cell sky130_fd_pr__dfm1sd2__example_55959141808561
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808560
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808563
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808562
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808564
+   Generating output for cell sky130_fd_io__amux_switch_1v2b
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180868
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180869
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808565
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180875
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808566
+   Generating output for cell sky130_fd_io__gpiov2_amx_pucsd_inv
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808567
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808122
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808123
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808477
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808568
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180884
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808569
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808100
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180815
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808570
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr_lshv2hv2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808571
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808441
+   Generating output for cell sky130_fd_io__gpiov2_amx_inv4
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr_lshv2hv
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180823
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808572
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808573
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808106
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808574
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808510
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808575
+   Generating output for cell sky130_fd_io__amx_inv1
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808576
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808504
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808577
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808578
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808579
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808581
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808418
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808580
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808140
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808496
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808497
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808278
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808462
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808582
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808583
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808498
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr_ls
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr
+   Generating output for cell sky130_fd_io__xor2_1
+   Generating output for cell sky130_fd_io__nand2_1
+   Generating output for cell sky130_fd_io__nor2_1
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808419
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808420
+   Generating output for cell sky130_fd_io__hvsbt_nor
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_5595914180894
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808584
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808455
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808445
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808447
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808248
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808200
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808457
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808450
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808451
+   Generating output for cell sky130_fd_io__gpiov2_amux_nand5
+   Generating output for cell sky130_fd_pr__dfm1sd__example_55959141808258
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808585
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808446
+   Generating output for cell sky130_fd_io__gpiov2_amux_nand4
+   Generating output for cell sky130_fd_io__gpiov2_amux_decoder
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808586
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808587
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808476
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808588
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808475
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808115
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808589
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_lshv2hv2
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_lshv2hv
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808460
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808590
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180816
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808463
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808464
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808465
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808466
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808467
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808468
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_ls
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_inv_1
+   Generating output for cell sky130_fd_io__gpiov2_amux_ls
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_logic
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808178
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808591
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808488
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808592
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808306
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808593
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808594
+   Generating output for cell sky130_fd_io__res75only_small
+   Generating output for cell sky130_fd_io__gpiov2_amux
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808608
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808517
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808533
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808230
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808529
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808518
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808609
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808604
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808610
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180811
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808549
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808190
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808548
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808611
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808191
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808189
+   Generating output for cell sky130_fd_io__gpiov2_in_buf
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808481
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808537
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808600
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808528
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808550
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808607
+   Generating output for cell sky130_fd_io__gpiov2_ipath_hvls
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808601
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_5595914180825
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808602
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808603
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808527
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808535
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808540
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808598
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808605
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808596
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808606
+   Generating output for cell sky130_fd_io__gpiov2_vcchib_in_buf
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180812
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808597
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808599
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808546
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808547
+   Generating output for cell sky130_fd_io__gpiov2_ipath_lvls
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808595
+   Generating output for cell sky130_fd_io__gpiov2_inbuf_lvinv_x1
+   Generating output for cell sky130_fd_io__gpiov2_ibuf_se
+   Generating output for cell sky130_fd_io__gpiov2_buf_localesd
+   Generating output for cell sky130_fd_io__hvsbt_nand2v2
+   Generating output for cell sky130_fd_io__gpiov2_ictl_logic
+   Generating output for cell sky130_fd_io__gpiov2_ipath
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808613
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808614
+   Generating output for cell sky130_fd_io__hvsbt_inv_x8v2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808423
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808280
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808425
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808424
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808426
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808379
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808380
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808382
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808383
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808427
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808428
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808429
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808430
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808102
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808431
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808432
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808434
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808433
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808435
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808440
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180878
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808394
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808298
+   Generating output for cell sky130_fd_io__com_ctl_ls
+   Generating output for cell sky130_fd_io__hvsbt_inv_x8
+   Generating output for cell sky130_fd_io__com_ctl_hldv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808617
+   Generating output for cell sky130_fd_io__com_ctl_ls_en_1_v2
+   Generating output for cell sky130_fd_io__com_ctl_ls_v2
+   Generating output for cell sky130_fd_io__tk_em2o_cdns_55959141808439
+   Generating output for cell sky130_fd_io__tk_em2s_cdns_55959141808438
+   Generating output for cell sky130_fd_io__com_ctl_ls_1v2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_5595914180813
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_5595914180822
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808618
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808619
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808620
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808621
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808622
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808623
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808116
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808624
+   Generating output for cell sky130_fd_io__com_ctl_lsv2
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_5595914180880
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_5595914180879
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180882
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180881
+   Generating output for cell sky130_fd_io__gpiov2_ctl_lsbank
+   Generating output for cell sky130_fd_io__gpiov2_ctl
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808375
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808376
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808377
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808381
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808384
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808386
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808387
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808388
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808389
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808390
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808391
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808392
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808393
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808373
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808272
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808271
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808374
+   Generating output for cell sky130_fd_io__gpio_dat_ls_1v2
+   Generating output for cell sky130_fd_io__gpio_dat_lsv2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808360
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808403
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808362
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808404
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808405
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808406
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808194
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808346
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808407
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808408
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808409
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808410
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808294
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808322
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808395
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808396
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808397
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808295
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808398
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808399
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808325
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808292
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808269
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808401
+   Generating output for cell sky130_fd_io__com_cclat
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808368
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808625
+   Generating output for cell sky130_fd_io__com_opath_datoev2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808416
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808417
+   Generating output for cell sky130_fd_io__hvsbt_xor
+   Generating output for cell sky130_fd_io__hvsbt_xorv2
+   Generating output for cell sky130_fd_io__com_ctl_ls_octl
+   Generating output for cell sky130_fd_io__gpiov2_octl
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808354
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808626
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808627
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808628
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808629
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808630
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808631
+   Generating output for cell sky130_fd_io__gpiov2_pdpredrvr_strong_nr2
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808633
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808632
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808634
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808635
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808636
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808637
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808638
+   Generating output for cell sky130_fd_io__gpiov2_pdpredrvr_strong_nr3
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808327
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808328
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808329
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808330
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808304
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808331
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808134
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808332
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808333
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808334
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808343
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808344
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808345
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808347
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808348
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808639
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808640
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808641
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808320
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808321
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808323
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808291
+   Generating output for cell sky130_fd_io__com_pdpredrvr_pbiasv2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_5595914180888
+   Generating output for cell sky130_fd_io__gpiov2_octl_mux
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808642
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808141
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808184
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808643
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808183
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808139
+   Generating output for cell sky130_fd_io__gpiov2_pdpredrvr_strong
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808143
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808364
+   Generating output for cell sky130_fd_io__com_pdpredrvr_strong_slowv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808363
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808314
+   Generating output for cell sky130_fd_pr__via_pol1__example_5595914180854
+   Generating output for cell sky130_fd_io__com_pupredrvr_strong_slowv2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808644
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808281
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808282
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808287
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808283
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808284
+   Generating output for cell sky130_fd_pr__res_generic_po__example_55959141808285
+   Generating output for cell sky130_fd_pr__res_generic_po__example_55959141808286
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808275
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808276
+   Generating output for cell sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a
+   Generating output for cell sky130_fd_io__gpiov2_pupredrvr_strong_nd2
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_55959141808301
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808302
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808303
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808305
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808307
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808308
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808309
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808310
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808311
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808312
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808313
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808315
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808317
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808318
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808319
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808293
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808296
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808297
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808299
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808300
+   Generating output for cell sky130_fd_io__feascom_pupredrvr_nbiasv2
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808144
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_5595914180899
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808142
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808101
+   Generating output for cell sky130_fd_io__gpio_pupredrvr_strongv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808365
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808366
+   Generating output for cell sky130_fd_io__com_pdpredrvr_weakv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808361
+   Generating output for cell sky130_fd_io__feas_com_pupredrvr_weak
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808266
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808267
+   Generating output for cell sky130_fd_io__gpiov2_obpredrvr
+   Generating output for cell sky130_fd_io__gpiov2_octl_dat
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418082
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418083
+   Generating output for cell sky130_fd_io__nfet_con_diff_wo_abt_270v2
+   Generating output for cell sky130_fd_io__gpiov2_pddrvr_strong
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808655
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808654
+   Generating output for cell sky130_fd_io__com_pudrvr_strong_slowv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808656
+   Generating output for cell sky130_fd_io__com_pudrvr_weakv2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_5595914180850
+   Generating output for cell sky130_fd_io__gpio_pddrvr_weakv2
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418085
+   Generating output for cell sky130_fd_io__pfet_con_diff_wo_abt_270v2
+   Generating output for cell sky130_fd_io__gpio_pudrvr_strongv2
+   Generating output for cell sky130_fd_io__gpio_pddrvr_strong_slowv2
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180852
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180853
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180855
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180856
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180832
+   Generating output for cell sky130_fd_pr__via_pol1_centered__example_559591418080
+   Generating output for cell sky130_fd_io__gpio_odrvr_subv2
+   Generating output for cell sky130_fd_io__gpio_odrvrv2
+   Generating output for cell sky130_fd_io__gpio_opathv2
+   Generating output for cell sky130_fd_io__top_gpiov2
+   Generating output for cell sky130_ef_io__gpiov2_pad
+   Generating output for cell sky130_ef_io__gpiov2_pad_wrapped
+   Generating output for cell sky130_ef_io__lvc_vccdx_overlay
+   Generating output for cell sky130_fd_io__overlay_vssd_lvc
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808683
+   Generating output for cell sky130_fd_io__gnd2gnd_strap
+   Generating output for cell sky130_fd_io__gnd2gnd_tap
+   Generating output for cell sky130_fd_io__gnd2gnd_diff
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808684
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808685
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808686
+   Generating output for cell sky130_fd_io__gnd2gnd_sub_dnwl
+   Generating output for cell sky130_fd_io__gnd2gnd_120x2_lv_isosub
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808687
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808691
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808690
+   Generating output for cell sky130_fd_pr__dftpl1s2__example_55959141808702
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808705
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808682
+   Generating output for cell sky130_fd_pr__dftpl1s2__example_55959141808694
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808693
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808681
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808688
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808696
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808697
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808698
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808699
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808695
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808704
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808703
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808701
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808692
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808689
+   Generating output for cell sky130_fd_io__top_ground_lvc_wpad
+   Generating output for cell sky130_ef_io__vssd_lvc_clamped_pad
+   Generating output for cell sky130_ef_io__hvc_vssio_overlay
+   Generating output for cell sky130_fd_io__overlay_vssio_hvc
+   Generating output for cell sky130_ef_io__vssio_hvc_clamped_pad
+   Generating output for cell sky130_fd_io__overlay_vdda_hvc
+   Generating output for cell sky130_fd_io__hvc_clampv2
+   Generating output for cell sky130_fd_io__top_power_hvc_wpadv2
+   Generating output for cell sky130_ef_io__vdda_hvc_clamped_pad
+   Generating output for cell sky130_fd_io__overlay_vccd_lvc
+   Generating output for cell sky130_fd_io__top_power_lvc_wpad
+   Generating output for cell sky130_ef_io__vccd_lvc_clamped_pad
+   Generating output for cell sky130_ef_io__disconnect_vdda_slice_5um
+   Generating output for cell sky130_ef_io__hvc_vddio_overlay
+   Generating output for cell sky130_fd_io__overlay_vddio_hvc
+   Generating output for cell sky130_ef_io__vddio_hvc_clamped_pad
+   Generating output for cell sky130_ef_io__lvc_vccdy_overlay
+   Generating output for cell sky130_ef_io__vssd_lvc_clamped3_pad
+   Generating output for cell sky130_ef_io__vccd_lvc_clamped3_pad
+   Generating output for cell chip_io
+   Generating output for cell user_project_wrapper
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_11$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_12$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_360_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w1_120_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_15$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_29$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_28$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m2_w0_740_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m2_w1_260_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_13$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_14$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_16$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w7_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w7_000_sli_dli_da_p$1".
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_dec$1".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_740_sactive_dli$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_740_sli_dactive$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w1_120_sli_dli$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m22_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m22_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m7_w1_680_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m7_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m18_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m18_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m3_w1_680_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m3_w1_680_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_dec_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_20$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_and2_dec$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_17$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_and3_dec$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w2_880_sli_dli$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pnand2$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_23$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_22$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_21$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_19$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w0_550_sli_dli$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_7$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_15$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m40_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m40_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_3$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m12_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m12_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m4_w1_260_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m4_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_16$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_740_sactive_dactive$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m24_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m24_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m8_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m8_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m3_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m3_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m39_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m39_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m13_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m13_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m5_w1_680_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m5_w2_000_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m2_w1_260_sli_dli_da_p$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m2_w2_000_sli_dli_da_p$1".
+Reading "sky130_fd_bd_sram__openram_dff$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_2$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_1$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_wordline_driver$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_hierarchical_predecode3x8$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_hierarchical_predecode2x4$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_column_mux_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_precharge_1$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_27$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_26$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_25$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_24$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_column_mux$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pand2$1".
+Reading "sky130_fd_bd_sram__openram_write_driver$1".
+Reading "sky130_fd_bd_sram__openram_sense_amp$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_precharge_0$1".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row$1".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col$1".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy$1".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica$1".
+Reading "sky130_fd_bd_sram__openram_dp_cell$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_3$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_10$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pnand2_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_dff_buf_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_18$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_17$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_19$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_4$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pnand3$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_14$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_13$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_12$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_11$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_20$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_9$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_8$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_7$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_6$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinv_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_and2_dec_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_wordline_driver_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_hierarchical_decoder$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_column_mux_array_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_precharge_array_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_column_mux_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_write_mask_and_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_write_driver_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_sense_amp_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_precharge_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_9$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_8$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_row_cap_array_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_row_cap_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_col_cap_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_col_cap_array_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_dummy_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_replica_column_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_replica_column$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_bitcell_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_dff_buf_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pand3$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_1$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_33$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pnand2_1$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pand2_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_dff_buf_array_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_5$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_delay_chain$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pand3_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_2$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_6$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_34$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_pinvbuf$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_port_address_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_port_address$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_port_data_0$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_port_data$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_replica_bitcell_array$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_wmask_dff$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_cr_3$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_row_addr_dff$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_control_logic_rw$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_col_addr_dff$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_cr_5$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_40$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_contact_39$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_control_logic_r$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_cr_4$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_data_dff$1".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8_bank$1".
+Reading "sky130_fd_sc_hd__decap_6$1".
+Reading "sky130_fd_sc_hd__fill_2$1".
+Reading "sky130_fd_sc_hd__fill_4$1".
+Reading "sky130_fd_sc_hd__decap_6$2".
+Reading "sky130_fd_sc_hd__fill_4$2".
+Reading "sky130_fd_sc_hd__fill_2$2".
+Reading "sky130_fd_sc_hd__decap_6_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__fill_2_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__fill_4_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__nand2_2$1".
+Reading "sky130_fd_sc_hd__o21ai_2$1".
+Reading "sky130_fd_sc_hd__nor2b_2$1".
+Reading "sky130_fd_sc_hd__or2_2$3".
+Reading "sky130_fd_sc_hd__dlxtn_1$1".
+Reading "sky130_fd_sc_hd__nor2_2$1".
+Reading "sky130_fd_sc_hd__and2_2$1".
+Reading "sky130_fd_sc_hd__mux4_1$2".
+Reading "M1M2_PR_M$3".
+Reading "sky130_fd_sc_hd__decap_3$3".
+Reading "sky130_fd_sc_hd__decap_4$3".
+Reading "sky130_fd_sc_hd__dfxtp_2$3".
+Reading "BlockRAM_1KB_VIA3$1".
+Reading "BlockRAM_1KB_VIA2$1".
+Reading "BlockRAM_1KB_VIA1$1".
+Reading "BlockRAM_1KB_VIA0$1".
+Reading "M3M4_PR$3".
+Reading "sky130_fd_sc_hd__diode_2$3".
+Reading "M2M3_PR$3".
+Reading "sky130_fd_sc_hd__conb_1$2".
+Reading "sky130_fd_sc_hd__decap_6$3".
+Reading "M1M2_PR$3".
+Reading "L1M1_PR$3".
+Reading "sky130_fd_sc_hd__fill_1$3".
+Reading "sky130_fd_sc_hd__fill_4$3".
+Reading "sky130_fd_sc_hd__fill_8$1".
+Reading "sky130_fd_sc_hd__fill_2$3".
+Reading "sky130_fd_sc_hd__decap_8$3".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1$3".
+Reading "sky130_sram_1kbyte_1rw1r_32x256_8$1".
+Reading "sky130_fd_sc_hd__mux2_1$3".
+Reading "sky130_fd_sc_hd__inv_2$3".
+Reading "sky130_fd_sc_hd__clkbuf_1_N_term_RAM_IO_gds".
+Reading "M3M4_PR_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1_N_term_RAM_IO_gds".
+Reading "N_term_RAM_IO_VIA4".
+Reading "N_term_RAM_IO_VIA5".
+Reading "N_term_RAM_IO_VIA6".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_N_term_RAM_IO_gds".
+Reading "M1M2_PR_M_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_4_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_2_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_1_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__buf_8_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_8_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__decap_8_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_RAM_IO_gds".
+Reading "L1M1_PR_N_term_RAM_IO_gds".
+Reading "M2M3_PR_N_term_RAM_IO_gds".
+Reading "N_term_RAM_IO_VIA1".
+Reading "N_term_RAM_IO_VIA2".
+Reading "N_term_RAM_IO_VIA3".
+Reading "N_term_RAM_IO_VIA0".
+Reading "M1M2_PR_N_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_N_term_DSP_gds".
+Reading "M1M2_PR_M_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__buf_2_N_term_DSP_gds".
+Reading "N_term_DSP_VIA6".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_N_term_DSP_gds".
+Reading "N_term_DSP_VIA4".
+Reading "N_term_DSP_VIA5".
+Reading "sky130_fd_sc_hd__fill_4_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__decap_8_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__fill_8_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__fill_2_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__fill_1_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__buf_8_N_term_DSP_gds".
+Reading "N_term_DSP_VIA0".
+Reading "N_term_DSP_VIA1".
+Reading "N_term_DSP_VIA2".
+Reading "N_term_DSP_VIA3".
+Reading "M2M3_PR_N_term_DSP_gds".
+Reading "M1M2_PR_N_term_DSP_gds".
+Reading "L1M1_PR_N_term_DSP_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_N_term_single2_gds".
+Reading "M1M2_PR_M_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__buf_2_N_term_single2_gds".
+Reading "N_term_single2_VIA6".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_N_term_single2_gds".
+Reading "N_term_single2_VIA4".
+Reading "N_term_single2_VIA5".
+Reading "sky130_fd_sc_hd__fill_4_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__decap_8_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__fill_8_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__fill_2_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__fill_1_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__buf_8_N_term_single2_gds".
+Reading "N_term_single2_VIA0".
+Reading "N_term_single2_VIA1".
+Reading "N_term_single2_VIA2".
+Reading "N_term_single2_VIA3".
+Reading "M2M3_PR_N_term_single2_gds".
+Reading "M1M2_PR_N_term_single2_gds".
+Reading "L1M1_PR_N_term_single2_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_N_term_single_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_N_term_single_gds".
+Reading "sky130_fd_sc_hd__buf_2_N_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_4_N_term_single_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_N_term_single_gds".
+Reading "N_term_single_VIA4".
+Reading "N_term_single_VIA5".
+Reading "N_term_single_VIA6".
+Reading "sky130_fd_sc_hd__decap_8_N_term_single_gds".
+Reading "M1M2_PR_M_N_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_8_N_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_2_N_term_single_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_1_N_term_single_gds".
+Reading "sky130_fd_sc_hd__buf_8_N_term_single_gds".
+Reading "N_term_single_VIA1".
+Reading "N_term_single_VIA2".
+Reading "N_term_single_VIA3".
+Reading "N_term_single_VIA0".
+Reading "L1M1_PR_N_term_single_gds".
+Reading "M1M2_PR_N_term_single_gds".
+Reading "M2M3_PR_N_term_single_gds".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1$1".
+Reading "sky130_fd_sc_hd__clkbuf_4$1".
+Reading "M1M2_PR_R$1".
+Reading "M2M3_PR_R$1".
+Reading "sky130_ef_sc_hd__fill_12$1".
+Reading "sky130_fd_sc_hd__clkinv_4$1".
+Reading "RegFile_VIA6$1".
+Reading "RegFile_VIA5$1".
+Reading "RegFile_VIA4$1".
+Reading "sky130_ef_sc_hd__fill_8$1".
+Reading "sky130_fd_sc_hd__buf_2$1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1$1".
+Reading "sky130_fd_sc_hd__buf_4$1".
+Reading "sky130_ef_sc_hd__decap_12$1".
+Reading "sky130_fd_sc_hd__decap_8$1".
+Reading "sky130_fd_sc_hd__mux2_4$1".
+Reading "sky130_fd_sc_hd__or3_1$1".
+Reading "sky130_fd_sc_hd__mux4_4$1".
+Reading "sky130_fd_sc_hd__mux2_1$1".
+Reading "sky130_fd_sc_hd__clkbuf_1$1".
+Reading "sky130_fd_sc_hd__buf_12$1".
+Reading "sky130_fd_sc_hd__mux4_1$1".
+Reading "sky130_fd_sc_hd__dlxbp_1$1".
+Reading "M1M2_PR_MR$1".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1$1".
+Reading "sky130_fd_sc_hd__clkinv_8$1".
+Reading "sky130_fd_sc_hd__mux4_2$1".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1$1".
+Reading "sky130_fd_sc_hd__or2_2$1".
+Reading "sky130_fd_sc_hd__clkinv_16$1".
+Reading "sky130_fd_sc_hd__buf_1$1".
+Reading "sky130_fd_sc_hd__decap_3$1".
+Reading "sky130_fd_sc_hd__dfxtp_2$1".
+Reading "sky130_fd_sc_hd__diode_2$1".
+Reading "sky130_fd_sc_hd__inv_2$1".
+Reading "M1M2_PR_M$1".
+Reading "sky130_fd_sc_hd__buf_8$1".
+Reading "sky130_fd_sc_hd__a22o_1$1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1$1".
+Reading "RegFile_VIA3$1".
+Reading "sky130_fd_sc_hd__decap_4$1".
+Reading "sky130_fd_sc_hd__fill_1$1".
+Reading "RegFile_VIA0$1".
+Reading "RegFile_VIA1$1".
+Reading "M3M4_PR$1".
+Reading "RegFile_VIA2$1".
+Reading "M1M2_PR$1".
+Reading "M2M3_PR$1".
+Reading "L1M1_PR$1".
+Reading "sky130_fd_sc_hd__buf_1_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__decap_6_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__buf_8_S_term_single2_gds".
+Reading "S_term_single2_VIA4".
+Reading "S_term_single2_VIA5".
+Reading "S_term_single2_VIA6".
+Reading "sky130_fd_sc_hd__clkinv_4_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__fill_2_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__fill_8_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__fill_4_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__fill_1_S_term_single2_gds".
+Reading "L1M1_PR_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__decap_8_S_term_single2_gds".
+Reading "M1M2_PR_M_S_term_single2_gds".
+Reading "S_term_single2_VIA2".
+Reading "S_term_single2_VIA3".
+Reading "M2M3_PR_S_term_single2_gds".
+Reading "S_term_single2_VIA0".
+Reading "S_term_single2_VIA1".
+Reading "M1M2_PR_S_term_single2_gds".
+Reading "sky130_fd_sc_hd__buf_1_W_IO_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1_W_IO_gds".
+Reading "M1M2_PR_MR_W_IO_gds".
+Reading "sky130_fd_sc_hd__dfxtp_2_W_IO_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_W_IO_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_W_IO_gds".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1_W_IO_gds".
+Reading "sky130_fd_sc_hd__conb_1_W_IO_gds".
+Reading "sky130_fd_sc_hd__inv_2_W_IO_gds".
+Reading "W_IO_VIA6".
+Reading "W_IO_VIA4".
+Reading "W_IO_VIA5".
+Reading "sky130_fd_sc_hd__buf_8_W_IO_gds".
+Reading "sky130_fd_sc_hd__mux4_2_W_IO_gds".
+Reading "sky130_fd_sc_hd__mux2_1_W_IO_gds".
+Reading "sky130_fd_sc_hd__dlxbp_1_W_IO_gds".
+Reading "sky130_fd_sc_hd__decap_6_W_IO_gds".
+Reading "sky130_fd_sc_hd__diode_2_W_IO_gds".
+Reading "sky130_fd_sc_hd__decap_8_W_IO_gds".
+Reading "sky130_fd_sc_hd__decap_4_W_IO_gds".
+Reading "M1M2_PR_M_W_IO_gds".
+Reading "M3M4_PR_W_IO_gds".
+Reading "L1M1_PR_W_IO_gds".
+Reading "sky130_fd_sc_hd__fill_2_W_IO_gds".
+Reading "M1M2_PR_W_IO_gds".
+Reading "W_IO_VIA0".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_W_IO_gds".
+Reading "M2M3_PR_W_IO_gds".
+Reading "sky130_fd_sc_hd__decap_3_W_IO_gds".
+Reading "sky130_fd_sc_hd__fill_1_W_IO_gds".
+Reading "W_IO_VIA1".
+Reading "W_IO_VIA2".
+Reading "W_IO_VIA3".
+Reading "sky130_fd_sc_hd__clkinv_8_RAM_IO_gds".
+Reading "M2M3_PR_R".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_RAM_IO_gds".
+Reading "RAM_IO_VIA4".
+Reading "RAM_IO_VIA5".
+Reading "RAM_IO_VIA6".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__buf_4_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1_RAM_IO_gds".
+Reading "M1M2_PR_R_RAM_IO_gds".
+Reading "L1M1_PR_R_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__conb_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__mux4_2_RAM_IO_gds".
+Reading "M1M2_PR_MR_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__buf_2_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkinv_16_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__diode_2_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__decap_4_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__dlxbp_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__decap_3_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_8_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__buf_8_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__dfxtp_2_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkbuf_4_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__buf_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_4_RAM_IO_gds".
+Reading "M1M2_PR_M_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__mux2_1_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_2_RAM_IO_gds".
+Reading "RAM_IO_VIA1".
+Reading "L1M1_PR_RAM_IO_gds".
+Reading "RAM_IO_VIA2".
+Reading "M2M3_PR_RAM_IO_gds".
+Reading "RAM_IO_VIA3".
+Reading "sky130_fd_sc_hd__fill_1_RAM_IO_gds".
+Reading "RAM_IO_VIA0".
+Reading "M1M2_PR_RAM_IO_gds".
+Reading "M3M4_PR_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__decap_4_S_term_RAM_IO_gds".
+Reading "M1M2_PR_M_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_S_term_RAM_IO_gds".
+Reading "S_term_RAM_IO_VIA4".
+Reading "S_term_RAM_IO_VIA5".
+Reading "S_term_RAM_IO_VIA6".
+Reading "sky130_fd_sc_hd__decap_6_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__buf_8_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__diode_2_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__decap_8_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_8_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_1_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_4_S_term_RAM_IO_gds".
+Reading "sky130_fd_sc_hd__fill_2_S_term_RAM_IO_gds".
+Reading "M2M3_PR_S_term_RAM_IO_gds".
+Reading "L1M1_PR_S_term_RAM_IO_gds".
+Reading "M1M2_PR_S_term_RAM_IO_gds".
+Reading "S_term_RAM_IO_VIA0".
+Reading "S_term_RAM_IO_VIA1".
+Reading "S_term_RAM_IO_VIA2".
+Reading "S_term_RAM_IO_VIA3".
+Reading "sky130_fd_sc_hd__o31a_1$1".
+Reading "sky130_fd_sc_hd__and2b_1$1".
+Reading "sky130_fd_sc_hd__a2bb2oi_1$1".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1$2".
+Reading "sky130_fd_sc_hd__clkbuf_4$2".
+Reading "sky130_fd_sc_hd__xor2_1$1".
+Reading "sky130_fd_sc_hd__o22ai_1$1".
+Reading "sky130_fd_sc_hd__a31oi_1$1".
+Reading "sky130_fd_sc_hd__a21oi_1$1".
+Reading "sky130_fd_sc_hd__a22o_1$2".
+Reading "sky130_fd_sc_hd__o221a_2$1".
+Reading "sky130_fd_sc_hd__a22oi_1$1".
+Reading "sky130_fd_sc_hd__mux2_2$1".
+Reading "sky130_fd_sc_hd__o21ai_1$1".
+Reading "sky130_fd_sc_hd__buf_12$2".
+Reading "sky130_fd_sc_hd__a221o_1$1".
+Reading "sky130_fd_sc_hd__o2bb2a_1$1".
+Reading "sky130_fd_sc_hd__a32o_1$1".
+Reading "sky130_fd_sc_hd__a31o_2$1".
+Reading "sky130_fd_sc_hd__and4_1$1".
+Reading "sky130_fd_sc_hd__or3_1$2".
+Reading "sky130_fd_sc_hd__o32a_1$1".
+Reading "DSP_VIA5$1".
+Reading "DSP_VIA4$1".
+Reading "DSP_VIA6$1".
+Reading "sky130_fd_sc_hd__conb_1$1".
+Reading "M1M2_PR_MR$2".
+Reading "sky130_fd_sc_hd__o21a_1$1".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1$2".
+Reading "sky130_fd_sc_hd__buf_2$2".
+Reading "sky130_fd_sc_hd__decap_3$2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1$2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1$2".
+Reading "sky130_fd_sc_hd__nand2_1$1".
+Reading "sky130_fd_sc_hd__mux2_4$2".
+Reading "sky130_fd_sc_hd__dfxtp_2$2".
+Reading "sky130_fd_sc_hd__a2bb2o_1$1".
+Reading "sky130_fd_sc_hd__a21o_1$1".
+Reading "sky130_fd_sc_hd__a21bo_2$1".
+Reading "sky130_fd_sc_hd__and2_1$1".
+Reading "sky130_fd_sc_hd__o21ba_2$1".
+Reading "sky130_fd_sc_hd__o22a_1$1".
+Reading "sky130_fd_sc_hd__or4_1$1".
+Reading "sky130_fd_sc_hd__xnor2_1$1".
+Reading "sky130_fd_sc_hd__or2b_1$1".
+Reading "sky130_fd_sc_hd__nor2_1$1".
+Reading "sky130_fd_sc_hd__or2_2$2".
+Reading "sky130_fd_sc_hd__inv_2$2".
+Reading "sky130_fd_sc_hd__mux2_1$2".
+Reading "sky130_fd_sc_hd__buf_1$2".
+Reading "L1M1_PR_R$1".
+Reading "sky130_fd_sc_hd__clkinv_4$2".
+Reading "sky130_fd_sc_hd__mux4_2$2".
+Reading "M1M2_PR_R$2".
+Reading "sky130_fd_sc_hd__decap_4$2".
+Reading "sky130_fd_sc_hd__buf_8$2".
+Reading "sky130_ef_sc_hd__fill_12$2".
+Reading "sky130_fd_sc_hd__dlxbp_1$2".
+Reading "sky130_fd_sc_hd__clkbuf_1$2".
+Reading "M1M2_PR_M$2".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1$2".
+Reading "sky130_ef_sc_hd__fill_8$2".
+Reading "sky130_ef_sc_hd__decap_12$2".
+Reading "sky130_fd_sc_hd__diode_2$2".
+Reading "sky130_fd_sc_hd__decap_8$2".
+Reading "M3M4_PR$2".
+Reading "DSP_VIA0$1".
+Reading "DSP_VIA2$1".
+Reading "DSP_VIA3$1".
+Reading "M2M3_PR$2".
+Reading "M1M2_PR$2".
+Reading "DSP_VIA1$1".
+Reading "L1M1_PR$2".
+Reading "sky130_fd_sc_hd__fill_1$2".
+Reading "sky130_fd_sc_hd__buf_1_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__decap_6_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__buf_8_S_term_DSP_gds".
+Reading "S_term_DSP_VIA4".
+Reading "S_term_DSP_VIA5".
+Reading "S_term_DSP_VIA6".
+Reading "sky130_fd_sc_hd__clkinv_4_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__fill_2_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__fill_8_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__fill_4_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__fill_1_S_term_DSP_gds".
+Reading "L1M1_PR_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__decap_8_S_term_DSP_gds".
+Reading "M1M2_PR_M_S_term_DSP_gds".
+Reading "S_term_DSP_VIA2".
+Reading "S_term_DSP_VIA3".
+Reading "M2M3_PR_S_term_DSP_gds".
+Reading "S_term_DSP_VIA0".
+Reading "S_term_DSP_VIA1".
+Reading "M1M2_PR_S_term_DSP_gds".
+Reading "sky130_fd_sc_hd__clkinv_16_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_LUT4AB_gds".
+Reading "L1M1_PR_R_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__buf_2_LUT4AB_gds".
+Reading "LUT4AB_VIA4".
+Reading "LUT4AB_VIA5".
+Reading "LUT4AB_VIA6".
+Reading "sky130_fd_sc_hd__clkinv_8_LUT4AB_gds".
+Reading "M1M2_PR_R_LUT4AB_gds".
+Reading "M1M2_PR_MR_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__decap_4_LUT4AB_gds".
+Reading "sky130_ef_sc_hd__fill_12_LUT4AB_gds".
+Reading "sky130_ef_sc_hd__decap_12_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__conb_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__mux2_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__mux2_4_LUT4AB_gds".
+Reading "sky130_ef_sc_hd__fill_8_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__inv_2_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__nor2_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__mux4_2_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__decap_3_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__o22a_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__buf_8_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__dfxtp_2_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__dlxbp_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__mux2_2_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__decap_8_LUT4AB_gds".
+Reading "M3M4_PR_LUT4AB_gds".
+Reading "M1M2_PR_M_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_LUT4AB_gds".
+Reading "sky130_fd_sc_hd__fill_1_LUT4AB_gds".
+Reading "M2M3_PR_LUT4AB_gds".
+Reading "M1M2_PR_LUT4AB_gds".
+Reading "LUT4AB_VIA1".
+Reading "LUT4AB_VIA2".
+Reading "LUT4AB_VIA0".
+Reading "sky130_fd_sc_hd__diode_2_LUT4AB_gds".
+Reading "L1M1_PR_LUT4AB_gds".
+Reading "LUT4AB_VIA3".
+Reading "sky130_fd_sc_hd__conb_1_S_term_single_gds".
+Reading "M1M2_PR_M_S_term_single_gds".
+Reading "sky130_fd_sc_hd__buf_1_S_term_single_gds".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1_S_term_single_gds".
+Reading "sky130_fd_sc_hd__clkbuf_1_S_term_single_gds".
+Reading "sky130_fd_sc_hd__decap_6_S_term_single_gds".
+Reading "sky130_fd_sc_hd__buf_8_S_term_single_gds".
+Reading "S_term_single_VIA4".
+Reading "S_term_single_VIA5".
+Reading "S_term_single_VIA6".
+Reading "S_term_single_VIA0".
+Reading "sky130_fd_sc_hd__fill_4_S_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_2_S_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_1_S_term_single_gds".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_8_S_term_single_gds".
+Reading "sky130_fd_sc_hd__clkinv_4_S_term_single_gds".
+Reading "sky130_fd_sc_hd__decap_8_S_term_single_gds".
+Reading "M2M3_PR_S_term_single_gds".
+Reading "M1M2_PR_S_term_single_gds".
+Reading "S_term_single_VIA1".
+Reading "S_term_single_VIA2".
+Reading "S_term_single_VIA3".
+Reading "L1M1_PR_S_term_single_gds".
+Reading "sky130_fd_sc_hd__fill_4".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "BlockRAM_1KB".
+Reading "N_term_RAM_IO".
+Reading "eFPGA_top_VIA7".
+Reading "eFPGA_top_VIA23".
+Reading "eFPGA_top_VIA24".
+Reading "eFPGA_top_VIA25".
+Reading "eFPGA_top_VIA6".
+Reading "eFPGA_top_VIA8".
+Reading "eFPGA_top_VIA19".
+Reading "N_term_DSP".
+Reading "eFPGA_top_VIA11".
+Reading "N_term_single2".
+Reading "N_term_single".
+Reading "eFPGA_top_VIA22".
+Reading "eFPGA_top_VIA36".
+Reading "eFPGA_top_VIA20".
+Reading "eFPGA_top_VIA21".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__buf_16".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_2".
+Reading "RegFile".
+Reading "S_term_single2".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__a2bb2oi_2".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__dlxbp_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "L1M1_PR_R".
+Reading "W_IO".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "eFPGA_top_VIA35".
+Reading "sky130_fd_sc_hd__clkdlybuf4s15_1".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "M1M2_PR_R".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "M1M2_PR_MR".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "eFPGA_top_VIA29".
+Reading "eFPGA_top_VIA30".
+Reading "sky130_fd_sc_hd__clkdlybuf4s18_2".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "RAM_IO".
+Reading "S_term_RAM_IO".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "M1M2_PR_M".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "DSP".
+Reading "S_term_DSP".
+Reading "sky130_fd_sc_hd__dlygate4sd2_1".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "eFPGA_top_VIA10".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "LUT4AB".
+Reading "S_term_single".
+Reading "sky130_fd_sc_hd__bufbuf_8".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "eFPGA_top_VIA9".
+Reading "eFPGA_top_VIA34".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "eFPGA_top_VIA37".
+Reading "eFPGA_top_VIA38".
+Reading "eFPGA_top_VIA39".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__bufbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "eFPGA_top_VIA18".
+Reading "eFPGA_top_VIA4".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "eFPGA_top_VIA32".
+Reading "eFPGA_top_VIA31".
+Reading "eFPGA_top_VIA5".
+Reading "eFPGA_top_VIA15".
+Reading "eFPGA_top_VIA33".
+Reading "eFPGA_top_VIA16".
+Reading "eFPGA_top_VIA17".
+Reading "eFPGA_top_VIA14".
+Reading "eFPGA_top_VIA1".
+Reading "eFPGA_top_VIA3".
+Reading "eFPGA_top_VIA12".
+Reading "eFPGA_top_VIA2".
+Reading "eFPGA_top_VIA13".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__clkinv_16".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "eFPGA_top_VIA0".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "M2M3_PR".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "M3M4_PR".
+Reading "eFPGA_top_VIA27".
+Reading "L1M1_PR".
+Reading "eFPGA_top_VIA28".
+Reading "sky130_ef_sc_hd__fill_12".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "M1M2_PR".
+Reading "sky130_ef_sc_hd__fill_8".
+Reading "eFPGA_top_VIA26".
+Reading "eFPGA_top".
+Reading "user_project_wrapper".
+   Generating output for cell caravel
+make[1]: Leaving directory `/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel'
+Make ship completed.
+make_ship complete: /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel;
+-------------------------------------------------------------------------------------------
+{{ STEP 2 }} make ship completed for mpw-two, slot-005 : eFPGA_v3_caravel
+-------------------------------------------------------------------------------------------
+okfatal: ambiguous argument 'develop': unknown revision or path not in the working tree.
+Use '--' to separate paths from revisions, like this:
+'git <command> [<revision>...] -- [<file>...]'
+USER_ID is set to 00020005
+PROJECT is set to caravel
+All files are uncompressed!
+Running generate_fill in the foreground...
+make -f /mnt/shuttles/shuttle/mpw-two/caravel/Makefile __generate_fill
+make[1]: Entering directory `/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel'
+python3 /mnt/shuttles/shuttle/mpw-two/caravel/scripts/generate_fill.py 00020005 caravel /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel -dist 2>&1 | tee ./signoff/build/generate_fill.out
+This script will generate files caravel_00020005_fill_pattern_x_y.gds
+Now generating fill patterns.  This may take. . . quite. . . a while.
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill.tcl" from command line.
+Started: 12/09/2021 16:06:02
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: caravel
+Reading "caravel_logo".
+Reading "open_source".
+Reading "sky130_fd_sc_hvl__decap_8".
+Reading "sky130_fd_sc_hvl__diode_2".
+Reading "sky130_fd_sc_hvl__decap_4".
+Reading "sky130_fd_sc_hvl__fill_2".
+Reading "sky130_fd_sc_hvl__fill_1".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "xres_buf".
+Reading "font_22".
+Reading "font_73".
+Reading "font_43".
+Reading "font_49".
+Reading "font_65".
+Reading "font_68".
+Reading "font_54".
+Reading "font_67".
+Reading "font_6E".
+Reading "font_69".
+Reading "font_6C".
+Reading "font_61".
+Reading "font_53".
+Reading "caravel_motto".
+Reading "alpha_2".
+Reading "alpha_5".
+Reading "alpha_0".
+Reading "user_id_textblock".
+Reading "font_62".
+Reading "font_66".
+Reading "font_29".
+Reading "font_20".
+Reading "font_28".
+Reading "font_33".
+Reading "font_56".
+Reading "font_76".
+Reading "font_72".
+Reading "font_2D".
+Reading "font_4B".
+Reading "font_44".
+Reading "font_50".
+Reading "font_70".
+Reading "font_6F".
+Reading "font_74".
+Reading "font_57".
+Reading "font_6B".
+Reading "font_79".
+Reading "font_47".
+Reading "font_31".
+Reading "font_32".
+Reading "font_30".
+Reading "font_6D".
+Reading "font_4E".
+Reading "copyright_block".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__dfrtn_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "caravel_clocking".
+Reading "sky130_fd_sc_hd__ebufn_8".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__nand4bb_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__clkinvlp_2".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__ebufn_2".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "housekeeping".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__einvn_4".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "digital_pll".
+Reading "sky130_fd_sc_hd__dfbbn_1".
+Reading "sky130_fd_sc_hd__ebufn_1".
+Reading "gpio_logic_high".
+Reading "gpio_control_block".
+Reading "gpio_defaults_block_1803".
+Reading "OE_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "OE_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "OE_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "OE_sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "OE_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "OE_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "OE_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "OE_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "OE_sky130_fd_sc_hvl__schmittbuf_1".
+Reading "OE_sky130_fd_sc_hvl__buf_8".
+Reading "OE_sky130_fd_sc_hvl__fill_4".
+Reading "OE_sky130_fd_sc_hvl__inv_8".
+Reading "OE_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "OE_sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "OE_sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "simple_por".
+Reading "CD_sky130_fd_sc_hd__decap_3".
+Reading "CD_sky130_fd_sc_hd__conb_1".
+Reading "CD_sky130_fd_sc_hd__fill_1".
+Reading "CD_sky130_fd_sc_hd__decap_8".
+Reading "CD_sky130_fd_sc_hd__fill_2".
+Reading "CD_sky130_fd_sc_hd__decap_6".
+Reading "CD_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "CD_sky130_fd_sc_hd__decap_4".
+Reading "CD_sky130_fd_sc_hd__decap_12".
+Reading "user_id_programming".
+Reading "LO_sky130_fd_sc_hd__decap_3".
+Reading "LO_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "LO_sky130_fd_sc_hd__decap_12".
+Reading "LO_sky130_fd_sc_hd__decap_6".
+Reading "LO_sky130_fd_sc_hd__ebufn_2".
+Reading "LO_sky130_fd_sc_hd__decap_4".
+Reading "LO_sky130_fd_sc_hd__diode_2".
+Reading "LO_sky130_fd_sc_hd__fill_1".
+Reading "LO_sky130_fd_sc_hd__fill_2".
+Reading "LO_sky130_fd_sc_hd__dfxtp_1".
+Reading "LO_sky130_fd_sc_hd__decap_8".
+Reading "LO_sky130_fd_sc_hd__mux2_1".
+Reading "LO_sky130_fd_sc_hd__mux4_1".
+Reading "LO_sky130_fd_sc_hd__inv_1".
+Reading "LO_sky130_fd_sc_hd__and2_1".
+Reading "LO_sky130_fd_sc_hd__dlclkp_1".
+Reading "LO_sky130_fd_sc_hd__conb_1".
+Reading "LO_sky130_fd_sc_hd__clkbuf_2".
+Reading "LO_sky130_fd_sc_hd__clkbuf_16".
+Reading "LO_sky130_fd_sc_hd__and3b_4".
+Reading "LO_sky130_fd_sc_hd__and2_2".
+Reading "LO_sky130_fd_sc_hd__nor3b_4".
+Reading "LO_sky130_fd_sc_hd__clkbuf_1".
+Reading "LO_sky130_fd_sc_hd__and4bb_2".
+Reading "LO_sky130_fd_sc_hd__nor4b_2".
+Reading "LO_sky130_fd_sc_hd__and3_4".
+Reading "LO_sky130_fd_sc_hd__and4b_2".
+Reading "LO_sky130_fd_sc_hd__and4_2".
+Reading "LO_sky130_fd_sc_hd__and2b_2".
+Reading "LO_sky130_fd_sc_hd__clkbuf_4".
+Reading "LO_DFFRAM".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+Reading "LO_sky130_fd_sc_hd__buf_2".
+Reading "LO_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "LO_sky130_fd_sc_hd__buf_8".
+Reading "LO_sky130_fd_sc_hd__buf_6".
+Reading "LO_sky130_fd_sc_hd__clkbuf_8".
+Reading "LO_sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "LO_sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "LO_sky130_fd_sc_hd__dfxtp_2".
+Reading "LO_sky130_fd_sc_hd__buf_4".
+Reading "LO_sky130_fd_sc_hd__a221o_1".
+Reading "LO_sky130_fd_sc_hd__a22o_1".
+Reading "LO_sky130_fd_sc_hd__dfxtp_4".
+Reading "LO_sky130_fd_sc_hd__nand3_4".
+Reading "LO_sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "LO_sky130_fd_sc_hd__a2111o_1".
+Reading "LO_sky130_fd_sc_hd__and4_1".
+Reading "LO_sky130_fd_sc_hd__a2111o_2".
+Reading "LO_sky130_fd_sc_hd__o211a_1".
+Reading "LO_sky130_fd_sc_hd__and3_1".
+Reading "LO_sky130_fd_sc_hd__inv_2".
+Reading "LO_sky130_fd_sc_hd__clkinv_2".
+Reading "LO_sky130_fd_sc_hd__a2111oi_1".
+Reading "LO_sky130_fd_sc_hd__buf_12".
+Reading "LO_sky130_fd_sc_hd__and2b_1".
+Reading "LO_sky130_fd_sc_hd__nand3b_1".
+Reading "LO_sky130_fd_sc_hd__a221o_2".
+Reading "LO_sky130_fd_sc_hd__nor3b_1".
+Reading "LO_sky130_fd_sc_hd__nor3_4".
+Reading "LO_sky130_fd_sc_hd__inv_6".
+Reading "LO_sky130_fd_sc_hd__and3b_1".
+Reading "LO_sky130_fd_sc_hd__nor3b_2".
+Reading "LO_sky130_fd_sc_hd__or2_1".
+Reading "LO_sky130_fd_sc_hd__a211oi_1".
+Reading "LO_sky130_fd_sc_hd__nand2_1".
+Reading "LO_sky130_fd_sc_hd__nand3b_4".
+Reading "LO_sky130_fd_sc_hd__inv_8".
+Reading "LO_sky130_fd_sc_hd__nand3_1".
+Reading "LO_sky130_fd_sc_hd__inv_12".
+Reading "LO_sky130_fd_sc_hd__o2111a_1".
+Reading "LO_sky130_fd_sc_hd__a21oi_1".
+Reading "LO_sky130_fd_sc_hd__o21ai_4".
+Reading "LO_sky130_fd_sc_hd__mux2_2".
+Reading "LO_sky130_fd_sc_hd__inv_4".
+Reading "LO_sky130_fd_sc_hd__a21bo_1".
+Reading "LO_sky130_fd_sc_hd__o21a_1".
+Reading "LO_sky130_fd_sc_hd__a211o_2".
+Reading "LO_sky130_fd_sc_hd__or2b_1".
+Reading "LO_sky130_fd_sc_hd__a21oi_4".
+Reading "LO_sky130_fd_sc_hd__o21ai_1".
+Reading "LO_sky130_fd_sc_hd__a21boi_1".
+Reading "LO_sky130_fd_sc_hd__nor3_1".
+Reading "LO_sky130_fd_sc_hd__nor2_2".
+Reading "LO_sky130_fd_sc_hd__a31oi_1".
+Reading "LO_sky130_fd_sc_hd__a21o_1".
+Reading "LO_sky130_fd_sc_hd__o21bai_1".
+Reading "LO_sky130_fd_sc_hd__o211ai_1".
+Reading "LO_sky130_fd_sc_hd__o31ai_1".
+Reading "LO_sky130_fd_sc_hd__nor2_1".
+Reading "LO_sky130_fd_sc_hd__xor2_4".
+Reading "LO_sky130_fd_sc_hd__nand3_2".
+Reading "LO_sky130_fd_sc_hd__o21ba_1".
+Reading "LO_sky130_fd_sc_hd__a41oi_1".
+Reading "LO_sky130_fd_sc_hd__nor3_2".
+Reading "LO_sky130_fd_sc_hd__o41ai_1".
+Reading "LO_sky130_fd_sc_hd__o21bai_2".
+Reading "LO_sky130_fd_sc_hd__xnor2_4".
+Reading "LO_sky130_fd_sc_hd__a41oi_4".
+Reading "LO_sky130_fd_sc_hd__xnor2_2".
+Reading "LO_sky130_fd_sc_hd__or3b_1".
+Reading "LO_sky130_fd_sc_hd__nand2_4".
+Reading "LO_sky130_fd_sc_hd__xnor2_1".
+Reading "LO_sky130_fd_sc_hd__nand2_8".
+Reading "LO_sky130_fd_sc_hd__xor2_1".
+Reading "LO_sky130_fd_sc_hd__nor2b_1".
+Reading "LO_sky130_fd_sc_hd__o21a_2".
+Reading "LO_sky130_fd_sc_hd__o211a_2".
+Reading "LO_sky130_fd_sc_hd__o31a_1".
+Reading "LO_sky130_fd_sc_hd__mux2_4".
+Reading "LO_sky130_fd_sc_hd__mux2_8".
+Reading "LO_sky130_fd_sc_hd__a211o_1".
+Reading "LO_sky130_fd_sc_hd__a311o_1".
+Reading "LO_sky130_fd_sc_hd__a22oi_4".
+Reading "LO_sky130_fd_sc_hd__o2111a_4".
+Reading "LO_sky130_fd_sc_hd__o22a_1".
+Reading "LO_sky130_fd_sc_hd__a31o_1".
+Reading "LO_sky130_fd_sc_hd__nor2b_2".
+Reading "LO_sky130_fd_sc_hd__a22oi_2".
+Reading "LO_sky130_fd_sc_hd__o21bai_4".
+Reading "LO_sky130_fd_sc_hd__o41a_2".
+Reading "LO_sky130_fd_sc_hd__nand2_2".
+Reading "LO_sky130_fd_sc_hd__nor2_8".
+Reading "LO_sky130_fd_sc_hd__a32oi_2".
+Reading "LO_sky130_fd_sc_hd__a221oi_4".
+Reading "LO_sky130_fd_sc_hd__nor2b_4".
+Reading "LO_sky130_fd_sc_hd__or4_1".
+Reading "LO_sky130_fd_sc_hd__a211oi_2".
+Reading "LO_sky130_fd_sc_hd__clkinv_4".
+Reading "LO_sky130_fd_sc_hd__a2bb2oi_1".
+Reading "LO_sky130_fd_sc_hd__a31oi_4".
+Reading "LO_sky130_fd_sc_hd__a21oi_2".
+Reading "LO_sky130_fd_sc_hd__o311ai_1".
+Reading "LO_sky130_fd_sc_hd__a41oi_2".
+Reading "LO_sky130_fd_sc_hd__or3b_4".
+Reading "LO_sky130_fd_sc_hd__clkinv_16".
+Reading "LO_sky130_fd_sc_hd__o211ai_4".
+Reading "LO_sky130_fd_sc_hd__nor2_4".
+Reading "LO_sky130_fd_sc_hd__o21ba_2".
+Reading "LO_sky130_fd_sc_hd__o2111ai_2".
+Reading "LO_sky130_fd_sc_hd__o2111ai_1".
+Reading "LO_sky130_fd_sc_hd__a32o_1".
+Reading "LO_sky130_fd_sc_hd__a311oi_1".
+Reading "LO_sky130_fd_sc_hd__xor2_2".
+Reading "LO_sky130_fd_sc_hd__a2111o_4".
+Reading "LO_sky130_fd_sc_hd__or4_4".
+Reading "LO_sky130_fd_sc_hd__o21ai_2".
+Reading "LO_sky130_fd_sc_hd__a211oi_4".
+Reading "LO_sky130_fd_sc_hd__o311ai_4".
+Reading "LO_sky130_fd_sc_hd__nand3b_2".
+Reading "LO_sky130_fd_sc_hd__a2111oi_4".
+Reading "LO_sky130_fd_sc_hd__or2b_4".
+Reading "LO_sky130_fd_sc_hd__o21a_4".
+Reading "LO_sky130_fd_sc_hd__and4b_4".
+Reading "LO_sky130_fd_sc_hd__o2111ai_4".
+Reading "LO_sky130_fd_sc_hd__or2_2".
+Reading "LO_sky130_fd_sc_hd__a21boi_2".
+Reading "LO_sky130_fd_sc_hd__mux4_2".
+Reading "LO_sky130_fd_sc_hd__a221oi_2".
+Reading "LO_sky130_fd_sc_hd__o22ai_1".
+Reading "LO_sky130_fd_sc_hd__o2bb2ai_1".
+Reading "LO_sky130_fd_sc_hd__and4_4".
+Reading "LO_sky130_fd_sc_hd__a32oi_1".
+Reading "LO_sky130_fd_sc_hd__clkinv_8".
+Reading "LO_sky130_fd_sc_hd__o32ai_1".
+Reading "LO_sky130_fd_sc_hd__a41o_1".
+Reading "LO_sky130_fd_sc_hd__or4_2".
+Reading "LO_sky130_fd_sc_hd__o221ai_1".
+Reading "LO_sky130_fd_sc_hd__o32a_1".
+Reading "LO_sky130_fd_sc_hd__a22o_2".
+Reading "LO_sky130_fd_sc_hd__o41a_1".
+Reading "LO_sky130_fd_sc_hd__a22oi_1".
+Reading "LO_sky130_fd_sc_hd__and3_2".
+Reading "LO_sky130_fd_sc_hd__o221a_2".
+Reading "LO_sky130_fd_sc_hd__o221a_1".
+Reading "LO_sky130_fd_sc_hd__and2_4".
+Reading "LO_sky130_fd_sc_hd__or3_1".
+Reading "LO_sky130_fd_sc_hd__o22ai_2".
+Reading "LO_sky130_fd_sc_hd__a221oi_1".
+Reading "LO_sky130_fd_sc_hd__a221o_4".
+Reading "LO_sky130_fd_sc_hd__o311ai_2".
+Reading "LO_sky130_fd_sc_hd__o31ai_2".
+Reading "LO_sky130_fd_sc_hd__a311oi_2".
+Reading "LO_sky130_fd_sc_hd__a31oi_2".
+Reading "LO_sky130_fd_sc_hd__o311a_2".
+Reading "LO_sky130_fd_sc_hd__o211ai_2".
+Reading "LO_sky130_fd_sc_hd__o41ai_4".
+Reading "LO_sky130_fd_sc_hd__o31a_4".
+Reading "LO_sky130_fd_sc_hd__a311oi_4".
+Reading "LO_sky130_fd_sc_hd__and2b_4".
+Reading "LO_sky130_fd_sc_hd__o2bb2ai_2".
+Reading "LO_sky130_fd_sc_hd__o2bb2ai_4".
+Reading "LO_sky130_fd_sc_hd__o22a_2".
+Reading "LO_sky130_fd_sc_hd__and4b_1".
+Reading "LO_sky130_fd_sc_hd__nand2b_1".
+Reading "LO_sky130_fd_sc_hd__a21boi_4".
+Reading "LO_sky130_fd_sc_hd__o2111a_2".
+Reading "LO_sky130_fd_sc_hd__o31ai_4".
+Reading "LO_sky130_fd_sc_hd__a2bb2oi_2".
+Reading "LO_sky130_fd_sc_hd__a2bb2oi_4".
+Reading "LO_sky130_fd_sc_hd__or3_4".
+Reading "LO_sky130_fd_sc_hd__a22o_4".
+Reading "LO_sky130_fd_sc_hd__a32oi_4".
+Reading "LO_sky130_fd_sc_hd__o311a_1".
+Reading "LO_sky130_fd_sc_hd__a21o_2".
+Reading "LO_sky130_fd_sc_hd__or4b_1".
+Reading "LO_sky130_fd_sc_hd__a2111oi_2".
+Reading "LO_sky130_fd_sc_hd__a21o_4".
+Reading "LO_sky130_fd_sc_hd__a32o_4".
+Reading "LO_sky130_fd_sc_hd__and3b_2".
+Reading "LO_sky130_fd_sc_hd__o32ai_4".
+Reading "LO_sky130_fd_sc_hd__o221ai_2".
+Reading "LO_sky130_fd_sc_hd__a31o_2".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "LO_sky130_fd_bd_sram__openram_dff".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "LO_sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "LO_sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "LO_sky130_fd_bd_sram__openram_sense_amp".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "LO_sky130_fd_bd_sram__openram_write_driver".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "LO_sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "LO_sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "LO_sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "LO_sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "LO_sky130_fd_bd_sram__openram_dp_cell".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8".
+    5000 uses
+Reading "LO_sky130_fd_sc_hd__inv_16".
+Reading "LO_sky130_fd_sc_hd__o41ai_2".
+Reading "LO_sky130_fd_sc_hd__o211a_4".
+Reading "LO_mgmt_core".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+    105000 uses
+    110000 uses
+    115000 uses
+    120000 uses
+    125000 uses
+    130000 uses
+    135000 uses
+    140000 uses
+    145000 uses
+Reading "mgmt_core_wrapper".
+Reading "gpio_defaults_block_1800".
+Reading "sky130_fd_sc_hd__dfbbp_1".
+Reading "spare_logic_block".
+Reading "sky130_fd_sc_hd__einvp_4".
+Reading "sky130_fd_sc_hd__einvp_8".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hvl__conb_1".
+Reading "mgmt_protect_hv".
+Reading "mprj_logic_high".
+Reading "mprj2_logic_high".
+Reading "mgmt_protect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+Reading "gpio_defaults_block_0403".
+Reading "gpio_defaults_block".
+Reading "gpio_control_power_routing_right".
+Reading "gpio_control_power_routing_top".
+Reading "gpio_control_power_routing".
+Reading "caravel_power_routing".
+Reading "sky130_fd_io__corner_bus_overlay".
+Reading "sky130_ef_io__corner_pad".
+Reading "sky130_ef_io__com_bus_slice_20um".
+Reading "sky130_ef_io__com_bus_slice_10um".
+Reading "sky130_ef_io__com_bus_slice_5um".
+Reading "sky130_ef_io__com_bus_slice_1um".
+Reading "sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um".
+Reading "sky130_ef_io__hvc_vdda_overlay".
+Reading "sky130_fd_io__com_bus_slice".
+Reading "sky130_fd_io__com_bus_hookup".
+Reading "sky130_fd_io__overlay_vssa_hvc".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180851".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808664".
+Reading "sky130_fd_io__sio_clamp_pcap_4x5".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808680".
+Reading "sky130_fd_io__esd_rcclamp_nfetcap".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808336".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808666".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808665".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808678".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808679".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808677".
+Reading "sky130_fd_pr__via_pol1__example_5595914180839".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808667".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808660".
+Reading "sky130_fd_pr__dfl1__example_55959141808663".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808671".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808672".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808673".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808668".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808670".
+Reading "sky130_fd_pr__dfl1__example_55959141808662".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808661".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808675".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808676".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808674".
+Reading "sky130_fd_pr__via_l1m1__example_559591418084".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808669".
+Reading "sky130_fd_pr__gendlring__example_559591418081".
+Reading "sky130_fd_pr__genrivetdlring__example_559591418082".
+Reading "sky130_fd_pr__padplhp__example_559591418080".
+Reading "sky130_fd_io__pad_esd".
+Reading "sky130_fd_io__com_busses_esd".
+Reading "sky130_fd_io__top_ground_hvc_wpad".
+Reading "sky130_ef_io__vssa_hvc_clamped_pad".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808717".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808716".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808719".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808718".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808720".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180890".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808721".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808243".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808722".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808723".
+Reading "sky130_fd_io__xres_inv_hysv2".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180838".
+Reading "sky130_fd_io__tk_tie_r_out_esd".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808765".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808764".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808767".
+Reading "sky130_fd_io__res250_sub_small".
+Reading "sky130_fd_io__res250only_small".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808289".
+Reading "sky130_fd_pr__via_pol1__example_5595914180833".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808715".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180862".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180863".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808288".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180859".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180864".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808264".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180858".
+Reading "sky130_fd_io__com_res_weak_v2".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180819".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808555".
+Reading "sky130_fd_pr__via_pol1__example_55959141808147".
+Reading "sky130_fd_pr__tpl1__example_55959141808148".
+Reading "sky130_fd_pr__tpl1__example_55959141808149".
+Reading "sky130_fd_pr__tpl1__example_55959141808150".
+Reading "sky130_fd_pr__tpl1__example_55959141808151".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808152".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808153".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808154".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808155".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808156".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808157".
+Reading "sky130_fd_pr__dfl1__example_55959141808158".
+Reading "sky130_fd_io__signal_5_sym_hv_local_5term".
+Reading "sky130_fd_pr__via_pol1__example_55959141808274".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808400".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808128".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808372".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808326".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808290".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808127".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180897".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808551".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808552".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808350".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808260".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808402".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808724".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808259".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808261".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808553".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808725".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808554".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808726".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808727".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808728".
+Reading "sky130_fd_io__gpio_buf_localesdv2".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180848".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180849".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808766".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808370".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808369".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808137".
+Reading "sky130_fd_pr__dfl1sd__example_559591418086".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808371".
+Reading "sky130_fd_pr__via_pol1__example_559591418083".
+Reading "sky130_fd_io__hvsbt_inv_x1".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808385".
+Reading "sky130_fd_pr__dfl1sd__example_559591418088".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808615".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808316".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808616".
+Reading "sky130_fd_pr__via_pol1__example_55959141808612".
+Reading "sky130_fd_io__hvsbt_inv_x4".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808422".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808421".
+Reading "sky130_fd_io__hvsbt_inv_x2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808657".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808659".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808658".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808202".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180811".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180812".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418084".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418086".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808653".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808652".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418081".
+Reading "sky130_fd_io__gpio_pudrvr_strong_axres4v2".
+Reading "sky130_fd_pr__via_m2m3__example_55959141808714".
+Reading "sky130_fd_io__xres_p_em1c_cdns_55959141808753".
+Reading "sky130_fd_pr__dfl1__example_55959141808187".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808754".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808755".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808700".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808559".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808762".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808338".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808337".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808763".
+Reading "sky130_fd_pr__dfl1__example_55959141808729".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808730".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808731".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808732".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808733".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808734".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808735".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808736".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808737".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808738".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808739".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808740".
+Reading "sky130_fd_pr__via_pol1__example_55959141808273".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808741".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808742".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808743".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808744".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808324".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808745".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808746".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808747".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808748".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808749".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808270".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808750".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808751".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808752".
+Reading "sky130_fd_io__xres2v2_rcfilter_lpfv2".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180860".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180861".
+Reading "sky130_fd_io__com_res_weak_bentbigres".
+Reading "sky130_fd_io__com_res_weak".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180857".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808646".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808645".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808647".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808649".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808648".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808650".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808651".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808378".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_xres4v2".
+Reading "sky130_fd_io__top_gpio_pad".
+Reading "sky130_fd_io__com_busses".
+Reading "sky130_fd_io__tap_1".
+Reading "sky130_fd_io__inv_1".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808768".
+Reading "sky130_fd_pr__res_bent_nd__example_55959141808769".
+Reading "sky130_fd_pr__pfet_01v8__example_559591418085".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418087".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418089".
+Reading "sky130_fd_io__hvsbt_nand2".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180827".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808770".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808233".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808771".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808237".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180829".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808772".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808773".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808242".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808774".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808775".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808776".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180835".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808777".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808778".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808779".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808780".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808782".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808781".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808452".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808783".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808449".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808784".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808785".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808786".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808787".
+Reading "sky130_fd_io__xres4v2_in_buf".
+Reading "sky130_fd_io__top_xres4v2".
+Reading "sky130_fd_io__com_bus_slice_m4".
+Reading "sky130_fd_io__overlay_gpiov2_m4".
+Reading "sky130_fd_io__overlay_gpiov2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808558".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808251".
+Reading "sky130_fd_pr__dfm1sd2__example_55959141808561".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808560".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808563".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808562".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808564".
+Reading "sky130_fd_io__amux_switch_1v2b".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180868".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180869".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808565".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180875".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808566".
+Reading "sky130_fd_io__gpiov2_amx_pucsd_inv".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808567".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808122".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808123".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808477".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808568".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180884".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808569".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808100".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180815".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808570".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808571".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808441".
+Reading "sky130_fd_io__gpiov2_amx_inv4".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180823".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808572".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808573".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808106".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808574".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808510".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808575".
+Reading "sky130_fd_io__amx_inv1".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808576".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808504".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808577".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808578".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808579".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808581".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808418".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808580".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808140".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808496".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808497".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808278".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808462".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808582".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808583".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808498".
+Reading "sky130_fd_io__gpiov2_amux_drvr_ls".
+Reading "sky130_fd_io__gpiov2_amux_drvr".
+Reading "sky130_fd_io__xor2_1".
+Reading "sky130_fd_io__nand2_1".
+Reading "sky130_fd_io__nor2_1".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808419".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808420".
+Reading "sky130_fd_io__hvsbt_nor".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180894".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808584".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808455".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808445".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808447".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808248".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808200".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808457".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808450".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808451".
+Reading "sky130_fd_io__gpiov2_amux_nand5".
+Reading "sky130_fd_pr__dfm1sd__example_55959141808258".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808585".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808446".
+Reading "sky130_fd_io__gpiov2_amux_nand4".
+Reading "sky130_fd_io__gpiov2_amux_decoder".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808586".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808587".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808476".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808588".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808475".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808115".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808589".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv2".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808460".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808590".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180816".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808463".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808464".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808465".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808466".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808467".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808468".
+Reading "sky130_fd_io__gpiov2_amux_ctl_ls".
+Reading "sky130_fd_io__gpiov2_amux_ctl_inv_1".
+Reading "sky130_fd_io__gpiov2_amux_ls".
+Reading "sky130_fd_io__gpiov2_amux_ctl_logic".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808178".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808591".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808488".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808592".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808306".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808593".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808594".
+Reading "sky130_fd_io__res75only_small".
+Reading "sky130_fd_io__gpiov2_amux".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808608".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808517".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808533".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808230".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808529".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808518".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808609".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808604".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808610".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180811".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808549".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808190".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808548".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808611".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808191".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808189".
+Reading "sky130_fd_io__gpiov2_in_buf".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808481".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808537".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808600".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808528".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808550".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808607".
+Reading "sky130_fd_io__gpiov2_ipath_hvls".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808601".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180825".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808602".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808603".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808527".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808535".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808540".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808598".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808605".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808596".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808606".
+Reading "sky130_fd_io__gpiov2_vcchib_in_buf".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180812".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808597".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808599".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808546".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808547".
+Reading "sky130_fd_io__gpiov2_ipath_lvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808595".
+Reading "sky130_fd_io__gpiov2_inbuf_lvinv_x1".
+Reading "sky130_fd_io__gpiov2_ibuf_se".
+Reading "sky130_fd_io__gpiov2_buf_localesd".
+Reading "sky130_fd_io__hvsbt_nand2v2".
+Reading "sky130_fd_io__gpiov2_ictl_logic".
+Reading "sky130_fd_io__gpiov2_ipath".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808613".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808614".
+Reading "sky130_fd_io__hvsbt_inv_x8v2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808423".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808280".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808425".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808424".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808426".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808379".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808380".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808382".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808383".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808427".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808428".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808429".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808430".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808102".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808431".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808432".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808434".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808433".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808435".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808440".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180878".
+Reading "sky130_fd_pr__via_pol1__example_55959141808394".
+Reading "sky130_fd_pr__via_pol1__example_55959141808298".
+Reading "sky130_fd_io__com_ctl_ls".
+Reading "sky130_fd_io__hvsbt_inv_x8".
+Reading "sky130_fd_io__com_ctl_hldv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808617".
+Reading "sky130_fd_io__com_ctl_ls_en_1_v2".
+Reading "sky130_fd_io__com_ctl_ls_v2".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808439".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808438".
+Reading "sky130_fd_io__com_ctl_ls_1v2".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180813".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180822".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808618".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808619".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808620".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808621".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808622".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808623".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808116".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808624".
+Reading "sky130_fd_io__com_ctl_lsv2".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180880".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180879".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180882".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180881".
+Reading "sky130_fd_io__gpiov2_ctl_lsbank".
+Reading "sky130_fd_io__gpiov2_ctl".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808375".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808376".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808377".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808381".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808384".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808386".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808387".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808388".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808389".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808390".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808391".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808392".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808393".
+Reading "sky130_fd_pr__via_pol1__example_55959141808373".
+Reading "sky130_fd_pr__via_pol1__example_55959141808272".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808271".
+Reading "sky130_fd_pr__tpl1__example_55959141808374".
+Reading "sky130_fd_io__gpio_dat_ls_1v2".
+Reading "sky130_fd_io__gpio_dat_lsv2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808360".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808403".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808362".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808404".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808405".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808406".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808194".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808346".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808407".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808408".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808409".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808410".
+Reading "sky130_fd_pr__via_pol1__example_55959141808294".
+Reading "sky130_fd_pr__via_pol1__example_55959141808322".
+Reading "sky130_fd_pr__via_pol1__example_55959141808395".
+Reading "sky130_fd_pr__via_pol1__example_55959141808396".
+Reading "sky130_fd_pr__via_pol1__example_55959141808397".
+Reading "sky130_fd_pr__via_pol1__example_55959141808295".
+Reading "sky130_fd_pr__via_pol1__example_55959141808398".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808399".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808325".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808292".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808269".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808401".
+Reading "sky130_fd_io__com_cclat".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808368".
+Reading "sky130_fd_pr__tpl1__example_55959141808625".
+Reading "sky130_fd_io__com_opath_datoev2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808416".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808417".
+Reading "sky130_fd_io__hvsbt_xor".
+Reading "sky130_fd_io__hvsbt_xorv2".
+Reading "sky130_fd_io__com_ctl_ls_octl".
+Reading "sky130_fd_io__gpiov2_octl".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808354".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808626".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808627".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808628".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808629".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808630".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808631".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr2".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808633".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808632".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808634".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808635".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808636".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808637".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808638".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr3".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808327".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808328".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808329".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808330".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808304".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808331".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808134".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808332".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808333".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808334".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808343".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808344".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808345".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808347".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808348".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808639".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808640".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808641".
+Reading "sky130_fd_pr__via_pol1__example_55959141808320".
+Reading "sky130_fd_pr__via_pol1__example_55959141808321".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808323".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808291".
+Reading "sky130_fd_io__com_pdpredrvr_pbiasv2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180888".
+Reading "sky130_fd_io__gpiov2_octl_mux".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808642".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808141".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808184".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808643".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808183".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808139".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808143".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808364".
+Reading "sky130_fd_io__com_pdpredrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808363".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808314".
+Reading "sky130_fd_pr__via_pol1__example_5595914180854".
+Reading "sky130_fd_io__com_pupredrvr_strong_slowv2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808644".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808281".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808282".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808287".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808283".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808284".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808285".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808286".
+Reading "sky130_fd_pr__via_pol1__example_55959141808275".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808276".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808301".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808302".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808303".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808305".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808307".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808308".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808309".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808310".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808311".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808312".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808313".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808315".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808317".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808318".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808319".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808293".
+Reading "sky130_fd_pr__via_pol1__example_55959141808296".
+Reading "sky130_fd_pr__via_pol1__example_55959141808297".
+Reading "sky130_fd_pr__tpl1__example_55959141808299".
+Reading "sky130_fd_pr__tpl1__example_55959141808300".
+Reading "sky130_fd_io__feascom_pupredrvr_nbiasv2".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808144".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_5595914180899".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808142".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808101".
+Reading "sky130_fd_io__gpio_pupredrvr_strongv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808365".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808366".
+Reading "sky130_fd_io__com_pdpredrvr_weakv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808361".
+Reading "sky130_fd_io__feas_com_pupredrvr_weak".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808266".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808267".
+Reading "sky130_fd_io__gpiov2_obpredrvr".
+Reading "sky130_fd_io__gpiov2_octl_dat".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418082".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418083".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpiov2_pddrvr_strong".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808655".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808654".
+Reading "sky130_fd_io__com_pudrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808656".
+Reading "sky130_fd_io__com_pudrvr_weakv2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180850".
+Reading "sky130_fd_io__gpio_pddrvr_weakv2".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418085".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpio_pudrvr_strongv2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_slowv2".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180852".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180853".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180855".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180856".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180832".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418080".
+Reading "sky130_fd_io__gpio_odrvr_subv2".
+Reading "sky130_fd_io__gpio_odrvrv2".
+Reading "sky130_fd_io__gpio_opathv2".
+Reading "sky130_fd_io__top_gpiov2".
+Reading "sky130_ef_io__gpiov2_pad".
+Reading "sky130_ef_io__gpiov2_pad_wrapped".
+Reading "sky130_ef_io__lvc_vccdx_overlay".
+Reading "sky130_fd_io__overlay_vssd_lvc".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808683".
+Reading "sky130_fd_io__gnd2gnd_strap".
+Reading "sky130_fd_io__gnd2gnd_tap".
+Reading "sky130_fd_io__gnd2gnd_diff".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808684".
+Reading "sky130_fd_pr__tpl1__example_55959141808685".
+Reading "sky130_fd_pr__tpl1__example_55959141808686".
+Reading "sky130_fd_io__gnd2gnd_sub_dnwl".
+Reading "sky130_fd_io__gnd2gnd_120x2_lv_isosub".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808687".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808691".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808690".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808702".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808705".
+Reading "sky130_fd_pr__dfl1__example_55959141808682".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808694".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808693".
+Reading "sky130_fd_pr__dfl1__example_55959141808681".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808688".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808696".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808697".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808698".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808699".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808695".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808704".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808703".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808701".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808692".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808689".
+Reading "sky130_fd_io__top_ground_lvc_wpad".
+Reading "sky130_ef_io__vssd_lvc_clamped_pad".
+Reading "sky130_ef_io__hvc_vssio_overlay".
+Reading "sky130_fd_io__overlay_vssio_hvc".
+Reading "sky130_ef_io__vssio_hvc_clamped_pad".
+Reading "sky130_fd_io__overlay_vdda_hvc".
+Reading "sky130_fd_io__hvc_clampv2".
+Reading "sky130_fd_io__top_power_hvc_wpadv2".
+Reading "sky130_ef_io__vdda_hvc_clamped_pad".
+Reading "sky130_fd_io__overlay_vccd_lvc".
+Reading "sky130_fd_io__top_power_lvc_wpad".
+Reading "sky130_ef_io__vccd_lvc_clamped_pad".
+Reading "sky130_ef_io__disconnect_vdda_slice_5um".
+Reading "sky130_ef_io__hvc_vddio_overlay".
+Reading "sky130_fd_io__overlay_vddio_hvc".
+Reading "sky130_ef_io__vddio_hvc_clamped_pad".
+Reading "sky130_ef_io__lvc_vccdy_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped3_pad".
+Reading "sky130_ef_io__vccd_lvc_clamped3_pad".
+Reading "chip_io".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_11$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_12$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_360_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w1_120_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_15$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_29$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_28$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m2_w0_740_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m2_w1_260_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_13$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_14$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_16$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w7_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w7_000_sli_dli_da_p$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_nand2_dec$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_dec$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_nand3_dec$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_740_sactive_dli$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_740_sli_dactive$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w1_120_sli_dli$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m22_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m22_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m7_w1_680_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m7_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m18_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m18_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m3_w1_680_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m3_w1_680_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_dec_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_20$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_and2_dec$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_17$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_and3_dec$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w2_880_sli_dli$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pnand2$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_23$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_22$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_21$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_19$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w0_550_sli_dli$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_7$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_15$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m40_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m40_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_3$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m12_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m12_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m4_w1_260_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m4_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_16$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_740_sactive_dactive$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m24_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m24_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m8_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m8_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m3_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m3_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m39_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m39_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m13_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m13_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m5_w1_680_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m5_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m2_w1_260_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m2_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_fd_bd_sram__openram_dff$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_2$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_1$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_wordline_driver$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_hierarchical_predecode3x8$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_hierarchical_predecode2x4$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_column_mux_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_precharge_1$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_27$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_26$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_25$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_24$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_column_mux$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pand2$1".
+Reading "KP_sky130_fd_bd_sram__openram_write_driver$1".
+Reading "KP_sky130_fd_bd_sram__openram_sense_amp$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_precharge_0$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_cell_cap_row$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_cell_cap_col$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_cell_dummy$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_cell_replica$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_cell$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_3$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_10$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pnand2_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_dff_buf_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_18$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_17$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_19$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_4$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pnand3$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_14$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_13$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_12$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_11$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_20$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_9$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_8$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_7$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_6$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_and2_dec_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_wordline_driver_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_hierarchical_decoder$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_column_mux_array_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_precharge_array_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_column_mux_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_write_mask_and_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_write_driver_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_sense_amp_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_precharge_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_9$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_8$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_row_cap_array_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_row_cap_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_col_cap_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_col_cap_array_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_dummy_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_replica_column_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_replica_column$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_bitcell_array$1".
+    5000 uses
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_dff_buf_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pand3$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_1$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_33$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pnand2_1$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pand2_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_dff_buf_array_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_5$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_delay_chain$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pand3_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_2$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_6$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_34$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinvbuf$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_port_address_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_port_address$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_port_data_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_port_data$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_replica_bitcell_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_wmask_dff$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_cr_3$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_row_addr_dff$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_control_logic_rw$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_col_addr_dff$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_cr_5$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_40$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_39$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_control_logic_r$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_cr_4$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_data_dff$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_bank$1".
+Reading "KP_sky130_fd_sc_hd__decap_6$1".
+Reading "KP_sky130_fd_sc_hd__fill_2$1".
+Reading "KP_sky130_fd_sc_hd__fill_4$1".
+Reading "KP_sky130_fd_sc_hd__decap_6$2".
+Reading "KP_sky130_fd_sc_hd__fill_4$2".
+Reading "KP_sky130_fd_sc_hd__fill_2$2".
+Reading "KP_sky130_fd_sc_hd__decap_6_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__nand2_2$1".
+Reading "KP_sky130_fd_sc_hd__o21ai_2$1".
+Reading "KP_sky130_fd_sc_hd__nor2b_2$1".
+Reading "KP_sky130_fd_sc_hd__or2_2$3".
+Reading "KP_sky130_fd_sc_hd__dlxtn_1$1".
+Reading "KP_sky130_fd_sc_hd__nor2_2$1".
+Reading "KP_sky130_fd_sc_hd__and2_2$1".
+Reading "KP_sky130_fd_sc_hd__mux4_1$2".
+Reading "KP_M1M2_PR_M$3".
+Reading "KP_sky130_fd_sc_hd__decap_3$3".
+Reading "KP_sky130_fd_sc_hd__decap_4$3".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2$3".
+Reading "KP_BlockRAM_1KB_VIA3$1".
+Reading "KP_BlockRAM_1KB_VIA2$1".
+Reading "KP_BlockRAM_1KB_VIA1$1".
+Reading "KP_BlockRAM_1KB_VIA0$1".
+Reading "KP_M3M4_PR$3".
+Reading "KP_sky130_fd_sc_hd__diode_2$3".
+Reading "KP_M2M3_PR$3".
+Reading "KP_sky130_fd_sc_hd__conb_1$2".
+Reading "KP_sky130_fd_sc_hd__decap_6$3".
+Reading "KP_M1M2_PR$3".
+Reading "KP_L1M1_PR$3".
+Reading "KP_sky130_fd_sc_hd__fill_1$3".
+Reading "KP_sky130_fd_sc_hd__fill_4$3".
+Reading "KP_sky130_fd_sc_hd__fill_8$1".
+Reading "KP_sky130_fd_sc_hd__fill_2$3".
+Reading "KP_sky130_fd_sc_hd__decap_8$3".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1$3".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8$1".
+    5000 uses
+Reading "KP_sky130_fd_sc_hd__mux2_1$3".
+Reading "KP_sky130_fd_sc_hd__inv_2$3".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_N_term_RAM_IO_gds".
+Reading "KP_M3M4_PR_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1_N_term_RAM_IO_gds".
+Reading "KP_N_term_RAM_IO_VIA4".
+Reading "KP_N_term_RAM_IO_VIA5".
+Reading "KP_N_term_RAM_IO_VIA6".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_N_term_RAM_IO_gds".
+Reading "KP_M1M2_PR_M_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_RAM_IO_gds".
+Reading "KP_L1M1_PR_N_term_RAM_IO_gds".
+Reading "KP_M2M3_PR_N_term_RAM_IO_gds".
+Reading "KP_N_term_RAM_IO_VIA1".
+Reading "KP_N_term_RAM_IO_VIA2".
+Reading "KP_N_term_RAM_IO_VIA3".
+Reading "KP_N_term_RAM_IO_VIA0".
+Reading "KP_M1M2_PR_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_N_term_DSP_gds".
+Reading "KP_M1M2_PR_M_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__buf_2_N_term_DSP_gds".
+Reading "KP_N_term_DSP_VIA6".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_N_term_DSP_gds".
+Reading "KP_N_term_DSP_VIA4".
+Reading "KP_N_term_DSP_VIA5".
+Reading "KP_sky130_fd_sc_hd__fill_4_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_N_term_DSP_gds".
+Reading "KP_N_term_DSP_VIA0".
+Reading "KP_N_term_DSP_VIA1".
+Reading "KP_N_term_DSP_VIA2".
+Reading "KP_N_term_DSP_VIA3".
+Reading "KP_M2M3_PR_N_term_DSP_gds".
+Reading "KP_M1M2_PR_N_term_DSP_gds".
+Reading "KP_L1M1_PR_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_N_term_single2_gds".
+Reading "KP_M1M2_PR_M_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__buf_2_N_term_single2_gds".
+Reading "KP_N_term_single2_VIA6".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_N_term_single2_gds".
+Reading "KP_N_term_single2_VIA4".
+Reading "KP_N_term_single2_VIA5".
+Reading "KP_sky130_fd_sc_hd__fill_4_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_N_term_single2_gds".
+Reading "KP_N_term_single2_VIA0".
+Reading "KP_N_term_single2_VIA1".
+Reading "KP_N_term_single2_VIA2".
+Reading "KP_N_term_single2_VIA3".
+Reading "KP_M2M3_PR_N_term_single2_gds".
+Reading "KP_M1M2_PR_N_term_single2_gds".
+Reading "KP_L1M1_PR_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__buf_2_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_N_term_single_gds".
+Reading "KP_N_term_single_VIA4".
+Reading "KP_N_term_single_VIA5".
+Reading "KP_N_term_single_VIA6".
+Reading "KP_sky130_fd_sc_hd__decap_8_N_term_single_gds".
+Reading "KP_M1M2_PR_M_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_N_term_single_gds".
+Reading "KP_N_term_single_VIA1".
+Reading "KP_N_term_single_VIA2".
+Reading "KP_N_term_single_VIA3".
+Reading "KP_N_term_single_VIA0".
+Reading "KP_L1M1_PR_N_term_single_gds".
+Reading "KP_M1M2_PR_N_term_single_gds".
+Reading "KP_M2M3_PR_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s25_1$1".
+Reading "KP_sky130_fd_sc_hd__clkbuf_4$1".
+Reading "KP_M1M2_PR_R$1".
+Reading "KP_M2M3_PR_R$1".
+Reading "KP_sky130_ef_sc_hd__fill_12$1".
+Reading "KP_sky130_fd_sc_hd__clkinv_4$1".
+Reading "KP_RegFile_VIA6$1".
+Reading "KP_RegFile_VIA5$1".
+Reading "KP_RegFile_VIA4$1".
+Reading "KP_sky130_ef_sc_hd__fill_8$1".
+Reading "KP_sky130_fd_sc_hd__buf_2$1".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_1$1".
+Reading "KP_sky130_fd_sc_hd__buf_4$1".
+Reading "KP_sky130_ef_sc_hd__decap_12$1".
+Moving label "VGND" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12$1.
+Moving label "VNB" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12$1.
+Moving label "decap_12" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12$1.
+Reading "KP_sky130_fd_sc_hd__decap_8$1".
+Reading "KP_sky130_fd_sc_hd__mux2_4$1".
+Reading "KP_sky130_fd_sc_hd__or3_1$1".
+Reading "KP_sky130_fd_sc_hd__mux4_4$1".
+Reading "KP_sky130_fd_sc_hd__mux2_1$1".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1$1".
+Reading "KP_sky130_fd_sc_hd__buf_12$1".
+Reading "KP_sky130_fd_sc_hd__mux4_1$1".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1$1".
+Reading "KP_M1M2_PR_MR$1".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1$1".
+Reading "KP_sky130_fd_sc_hd__clkinv_8$1".
+Reading "KP_sky130_fd_sc_hd__mux4_2$1".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1$1".
+Reading "KP_sky130_fd_sc_hd__or2_2$1".
+Reading "KP_sky130_fd_sc_hd__clkinv_16$1".
+Reading "KP_sky130_fd_sc_hd__buf_1$1".
+Reading "KP_sky130_fd_sc_hd__decap_3$1".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2$1".
+Reading "KP_sky130_fd_sc_hd__diode_2$1".
+Reading "KP_sky130_fd_sc_hd__inv_2$1".
+Reading "KP_M1M2_PR_M$1".
+Reading "KP_sky130_fd_sc_hd__buf_8$1".
+Reading "KP_sky130_fd_sc_hd__a22o_1$1".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1$1".
+Reading "KP_RegFile_VIA3$1".
+Reading "KP_sky130_fd_sc_hd__decap_4$1".
+Reading "KP_sky130_fd_sc_hd__fill_1$1".
+Reading "KP_RegFile_VIA0$1".
+Reading "KP_RegFile_VIA1$1".
+Reading "KP_M3M4_PR$1".
+Reading "KP_RegFile_VIA2$1".
+Reading "KP_M1M2_PR$1".
+Reading "KP_M2M3_PR$1".
+Reading "KP_L1M1_PR$1".
+Reading "KP_sky130_fd_sc_hd__buf_1_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__decap_6_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_S_term_single2_gds".
+Reading "KP_S_term_single2_VIA4".
+Reading "KP_S_term_single2_VIA5".
+Reading "KP_S_term_single2_VIA6".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_S_term_single2_gds".
+Reading "KP_L1M1_PR_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_S_term_single2_gds".
+Reading "KP_M1M2_PR_M_S_term_single2_gds".
+Reading "KP_S_term_single2_VIA2".
+Reading "KP_S_term_single2_VIA3".
+Reading "KP_M2M3_PR_S_term_single2_gds".
+Reading "KP_S_term_single2_VIA0".
+Reading "KP_S_term_single2_VIA1".
+Reading "KP_M1M2_PR_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__buf_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1_W_IO_gds".
+Reading "KP_M1M2_PR_MR_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__conb_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__inv_2_W_IO_gds".
+Reading "KP_W_IO_VIA6".
+Reading "KP_W_IO_VIA4".
+Reading "KP_W_IO_VIA5".
+Reading "KP_sky130_fd_sc_hd__buf_8_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__mux4_2_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__mux2_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_6_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__diode_2_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_4_W_IO_gds".
+Reading "KP_M1M2_PR_M_W_IO_gds".
+Reading "KP_M3M4_PR_W_IO_gds".
+Reading "KP_L1M1_PR_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_W_IO_gds".
+Reading "KP_M1M2_PR_W_IO_gds".
+Reading "KP_W_IO_VIA0".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_W_IO_gds".
+Reading "KP_M2M3_PR_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_3_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_W_IO_gds".
+Reading "KP_W_IO_VIA1".
+Reading "KP_W_IO_VIA2".
+Reading "KP_W_IO_VIA3".
+Reading "KP_sky130_fd_sc_hd__clkinv_8_RAM_IO_gds".
+Reading "KP_M2M3_PR_R".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_RAM_IO_gds".
+Reading "KP_RAM_IO_VIA4".
+Reading "KP_RAM_IO_VIA5".
+Reading "KP_RAM_IO_VIA6".
+Reading "KP_sky130_fd_sc_hd__dfxtp_1".
+Reading "KP_sky130_fd_sc_hd__buf_4_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s25_1_RAM_IO_gds".
+Reading "KP_M1M2_PR_R_RAM_IO_gds".
+Reading "KP_L1M1_PR_R_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__conb_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__mux4_2_RAM_IO_gds".
+Reading "KP_M1M2_PR_MR_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__buf_2_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_16_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__diode_2_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_4_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_3_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_4_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__buf_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_RAM_IO_gds".
+Reading "KP_M1M2_PR_M_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__mux2_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_RAM_IO_gds".
+Reading "KP_RAM_IO_VIA1".
+Reading "KP_L1M1_PR_RAM_IO_gds".
+Reading "KP_RAM_IO_VIA2".
+Reading "KP_M2M3_PR_RAM_IO_gds".
+Reading "KP_RAM_IO_VIA3".
+Reading "KP_sky130_fd_sc_hd__fill_1_RAM_IO_gds".
+Reading "KP_RAM_IO_VIA0".
+Reading "KP_M1M2_PR_RAM_IO_gds".
+Reading "KP_M3M4_PR_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_4_S_term_RAM_IO_gds".
+Reading "KP_M1M2_PR_M_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_S_term_RAM_IO_gds".
+Reading "KP_S_term_RAM_IO_VIA4".
+Reading "KP_S_term_RAM_IO_VIA5".
+Reading "KP_S_term_RAM_IO_VIA6".
+Reading "KP_sky130_fd_sc_hd__decap_6_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__diode_2_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_S_term_RAM_IO_gds".
+Reading "KP_M2M3_PR_S_term_RAM_IO_gds".
+Reading "KP_L1M1_PR_S_term_RAM_IO_gds".
+Reading "KP_M1M2_PR_S_term_RAM_IO_gds".
+Reading "KP_S_term_RAM_IO_VIA0".
+Reading "KP_S_term_RAM_IO_VIA1".
+Reading "KP_S_term_RAM_IO_VIA2".
+Reading "KP_S_term_RAM_IO_VIA3".
+Reading "KP_sky130_fd_sc_hd__o31a_1$1".
+Reading "KP_sky130_fd_sc_hd__and2b_1$1".
+Reading "KP_sky130_fd_sc_hd__a2bb2oi_1$1".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1$2".
+Reading "KP_sky130_fd_sc_hd__clkbuf_4$2".
+Reading "KP_sky130_fd_sc_hd__xor2_1$1".
+Reading "KP_sky130_fd_sc_hd__o22ai_1$1".
+Reading "KP_sky130_fd_sc_hd__a31oi_1$1".
+Reading "KP_sky130_fd_sc_hd__a21oi_1$1".
+Reading "KP_sky130_fd_sc_hd__a22o_1$2".
+Reading "KP_sky130_fd_sc_hd__o221a_2$1".
+Reading "KP_sky130_fd_sc_hd__a22oi_1$1".
+Reading "KP_sky130_fd_sc_hd__mux2_2$1".
+Reading "KP_sky130_fd_sc_hd__o21ai_1$1".
+Reading "KP_sky130_fd_sc_hd__buf_12$2".
+Reading "KP_sky130_fd_sc_hd__a221o_1$1".
+Reading "KP_sky130_fd_sc_hd__o2bb2a_1$1".
+Reading "KP_sky130_fd_sc_hd__a32o_1$1".
+Reading "KP_sky130_fd_sc_hd__a31o_2$1".
+Reading "KP_sky130_fd_sc_hd__and4_1$1".
+Reading "KP_sky130_fd_sc_hd__or3_1$2".
+Reading "KP_sky130_fd_sc_hd__o32a_1$1".
+Reading "KP_DSP_VIA5$1".
+Reading "KP_DSP_VIA4$1".
+Reading "KP_DSP_VIA6$1".
+Reading "KP_sky130_fd_sc_hd__conb_1$1".
+Reading "KP_M1M2_PR_MR$2".
+Reading "KP_sky130_fd_sc_hd__o21a_1$1".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1$2".
+Reading "KP_sky130_fd_sc_hd__buf_2$2".
+Reading "KP_sky130_fd_sc_hd__decap_3$2".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_1$2".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s25_1$2".
+Reading "KP_sky130_fd_sc_hd__nand2_1$1".
+Reading "KP_sky130_fd_sc_hd__mux2_4$2".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2$2".
+Reading "KP_sky130_fd_sc_hd__a2bb2o_1$1".
+Reading "KP_sky130_fd_sc_hd__a21o_1$1".
+Reading "KP_sky130_fd_sc_hd__a21bo_2$1".
+Reading "KP_sky130_fd_sc_hd__and2_1$1".
+Reading "KP_sky130_fd_sc_hd__o21ba_2$1".
+Reading "KP_sky130_fd_sc_hd__o22a_1$1".
+Reading "KP_sky130_fd_sc_hd__or4_1$1".
+Reading "KP_sky130_fd_sc_hd__xnor2_1$1".
+Reading "KP_sky130_fd_sc_hd__or2b_1$1".
+Reading "KP_sky130_fd_sc_hd__nor2_1$1".
+Reading "KP_sky130_fd_sc_hd__or2_2$2".
+Reading "KP_sky130_fd_sc_hd__inv_2$2".
+Reading "KP_sky130_fd_sc_hd__mux2_1$2".
+Reading "KP_sky130_fd_sc_hd__buf_1$2".
+Reading "KP_L1M1_PR_R$1".
+Reading "KP_sky130_fd_sc_hd__clkinv_4$2".
+Reading "KP_sky130_fd_sc_hd__mux4_2$2".
+Reading "KP_M1M2_PR_R$2".
+Reading "KP_sky130_fd_sc_hd__decap_4$2".
+Reading "KP_sky130_fd_sc_hd__buf_8$2".
+Reading "KP_sky130_ef_sc_hd__fill_12$2".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1$2".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1$2".
+Reading "KP_M1M2_PR_M$2".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1$2".
+Reading "KP_sky130_ef_sc_hd__fill_8$2".
+Reading "KP_sky130_ef_sc_hd__decap_12$2".
+Moving label "VGND" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12$2.
+Moving label "VNB" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12$2.
+Moving label "decap_12" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12$2.
+Reading "KP_sky130_fd_sc_hd__diode_2$2".
+Reading "KP_sky130_fd_sc_hd__decap_8$2".
+Reading "KP_M3M4_PR$2".
+Reading "KP_DSP_VIA0$1".
+Reading "KP_DSP_VIA2$1".
+Reading "KP_DSP_VIA3$1".
+Reading "KP_M2M3_PR$2".
+Reading "KP_M1M2_PR$2".
+Reading "KP_DSP_VIA1$1".
+Reading "KP_L1M1_PR$2".
+Reading "KP_sky130_fd_sc_hd__fill_1$2".
+Reading "KP_sky130_fd_sc_hd__buf_1_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__decap_6_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_S_term_DSP_gds".
+Reading "KP_S_term_DSP_VIA4".
+Reading "KP_S_term_DSP_VIA5".
+Reading "KP_S_term_DSP_VIA6".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_S_term_DSP_gds".
+Reading "KP_L1M1_PR_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_S_term_DSP_gds".
+Reading "KP_M1M2_PR_M_S_term_DSP_gds".
+Reading "KP_S_term_DSP_VIA2".
+Reading "KP_S_term_DSP_VIA3".
+Reading "KP_M2M3_PR_S_term_DSP_gds".
+Reading "KP_S_term_DSP_VIA0".
+Reading "KP_S_term_DSP_VIA1".
+Reading "KP_M1M2_PR_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_16_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_LUT4AB_gds".
+Reading "KP_L1M1_PR_R_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__buf_2_LUT4AB_gds".
+Reading "KP_LUT4AB_VIA4".
+Reading "KP_LUT4AB_VIA5".
+Reading "KP_LUT4AB_VIA6".
+Reading "KP_sky130_fd_sc_hd__clkinv_8_LUT4AB_gds".
+Reading "KP_M1M2_PR_R_LUT4AB_gds".
+Reading "KP_M1M2_PR_MR_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__decap_4_LUT4AB_gds".
+Reading "KP_sky130_ef_sc_hd__fill_12_LUT4AB_gds".
+Reading "KP_sky130_ef_sc_hd__decap_12_LUT4AB_gds".
+Moving label "VGND" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12_LUT4AB_gds.
+Moving label "VNB" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12_LUT4AB_gds.
+Moving label "decap_12" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12_LUT4AB_gds.
+Reading "KP_sky130_fd_sc_hd__conb_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__mux2_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__mux2_4_LUT4AB_gds".
+Reading "KP_sky130_ef_sc_hd__fill_8_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__inv_2_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__nor2_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__mux4_2_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__decap_3_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__o22a_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__mux2_2_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_LUT4AB_gds".
+Reading "KP_M3M4_PR_LUT4AB_gds".
+Reading "KP_M1M2_PR_M_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_LUT4AB_gds".
+Reading "KP_M2M3_PR_LUT4AB_gds".
+Reading "KP_M1M2_PR_LUT4AB_gds".
+Reading "KP_LUT4AB_VIA1".
+Reading "KP_LUT4AB_VIA2".
+Reading "KP_LUT4AB_VIA0".
+Reading "KP_sky130_fd_sc_hd__diode_2_LUT4AB_gds".
+Reading "KP_L1M1_PR_LUT4AB_gds".
+Reading "KP_LUT4AB_VIA3".
+Reading "KP_sky130_fd_sc_hd__conb_1_S_term_single_gds".
+Reading "KP_M1M2_PR_M_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__buf_1_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__decap_6_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_S_term_single_gds".
+Reading "KP_S_term_single_VIA4".
+Reading "KP_S_term_single_VIA5".
+Reading "KP_S_term_single_VIA6".
+Reading "KP_S_term_single_VIA0".
+Reading "KP_sky130_fd_sc_hd__fill_4_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_S_term_single_gds".
+Reading "KP_M2M3_PR_S_term_single_gds".
+Reading "KP_M1M2_PR_S_term_single_gds".
+Reading "KP_S_term_single_VIA1".
+Reading "KP_S_term_single_VIA2".
+Reading "KP_S_term_single_VIA3".
+Reading "KP_L1M1_PR_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4".
+Reading "KP_sky130_fd_sc_hd__fill_2".
+Reading "KP_sky130_fd_sc_hd__decap_6".
+Reading "KP_BlockRAM_1KB".
+    5000 uses
+Reading "KP_N_term_RAM_IO".
+Reading "KP_eFPGA_top_VIA7".
+Reading "KP_eFPGA_top_VIA23".
+Reading "KP_eFPGA_top_VIA24".
+Reading "KP_eFPGA_top_VIA25".
+Reading "KP_eFPGA_top_VIA6".
+Reading "KP_eFPGA_top_VIA8".
+Reading "KP_eFPGA_top_VIA19".
+Reading "KP_N_term_DSP".
+Reading "KP_eFPGA_top_VIA11".
+Reading "KP_N_term_single2".
+Reading "KP_N_term_single".
+Reading "KP_eFPGA_top_VIA22".
+Reading "KP_eFPGA_top_VIA36".
+Reading "KP_eFPGA_top_VIA20".
+Reading "KP_eFPGA_top_VIA21".
+Reading "KP_sky130_fd_sc_hd__inv_8".
+Reading "KP_sky130_fd_sc_hd__buf_16".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s25_2".
+Reading "KP_RegFile".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+Reading "KP_S_term_single2".
+Reading "KP_sky130_fd_sc_hd__a211o_2".
+Reading "KP_sky130_fd_sc_hd__a221oi_1".
+Reading "KP_sky130_fd_sc_hd__o21ba_2".
+Reading "KP_sky130_fd_sc_hd__or2_4".
+Reading "KP_sky130_fd_sc_hd__or2b_1".
+Reading "KP_sky130_fd_sc_hd__nand4_1".
+Reading "KP_sky130_fd_sc_hd__a32o_1".
+Reading "KP_sky130_fd_sc_hd__o21bai_1".
+Reading "KP_sky130_fd_sc_hd__a2bb2oi_1".
+Reading "KP_sky130_fd_sc_hd__a31oi_1".
+Reading "KP_sky130_fd_sc_hd__a2111o_1".
+Reading "KP_sky130_fd_sc_hd__and4_1".
+Reading "KP_sky130_fd_sc_hd__and3b_1".
+Reading "KP_sky130_fd_sc_hd__a2bb2oi_2".
+Reading "KP_sky130_fd_sc_hd__o22ai_1".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1".
+Reading "KP_sky130_fd_sc_hd__nand2b_1".
+Reading "KP_sky130_fd_sc_hd__a21oi_1".
+Reading "KP_sky130_fd_sc_hd__and4b_1".
+Reading "KP_sky130_fd_sc_hd__and3_1".
+Reading "KP_sky130_fd_sc_hd__o2111a_1".
+Reading "KP_sky130_fd_sc_hd__or3b_2".
+Reading "KP_sky130_fd_sc_hd__a211oi_1".
+Reading "KP_sky130_fd_sc_hd__xnor2_1".
+Reading "KP_sky130_fd_sc_hd__o32a_1".
+Reading "KP_sky130_fd_sc_hd__a211o_1".
+Reading "KP_sky130_fd_sc_hd__o221ai_1".
+Reading "KP_sky130_fd_sc_hd__a31o_2".
+Reading "KP_sky130_fd_sc_hd__xor2_1".
+Reading "KP_sky130_fd_sc_hd__a221o_1".
+Reading "KP_sky130_fd_sc_hd__o211a_2".
+Reading "KP_sky130_fd_sc_hd__and2b_1".
+Reading "KP_sky130_fd_sc_hd__o311a_1".
+Reading "KP_sky130_fd_sc_hd__o31a_1".
+Reading "KP_sky130_fd_sc_hd__nor3_1".
+Reading "KP_sky130_fd_sc_hd__o211ai_1".
+Reading "KP_sky130_fd_sc_hd__and2_1".
+Reading "KP_sky130_fd_sc_hd__nand3b_1".
+Reading "KP_sky130_fd_sc_hd__or4b_2".
+Reading "KP_sky130_fd_sc_hd__nand2_1".
+Reading "KP_sky130_fd_sc_hd__o221a_2".
+Reading "KP_sky130_fd_sc_hd__mux2_2".
+Reading "KP_sky130_fd_sc_hd__nand4b_1".
+Reading "KP_sky130_fd_sc_hd__nand2_2".
+Reading "KP_sky130_fd_sc_hd__or4bb_1".
+Reading "KP_sky130_fd_sc_hd__a2bb2o_1".
+Reading "KP_sky130_fd_sc_hd__o22a_1".
+Reading "KP_sky130_fd_sc_hd__o21a_1".
+Reading "KP_L1M1_PR_R".
+Reading "KP_W_IO".
+    5000 uses
+Reading "KP_sky130_fd_sc_hd__o21ai_1".
+Reading "KP_sky130_fd_sc_hd__a21o_1".
+Reading "KP_sky130_fd_sc_hd__or4_1".
+Reading "KP_sky130_fd_sc_hd__or3_1".
+Reading "KP_eFPGA_top_VIA35".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s15_1".
+Reading "KP_sky130_fd_sc_hd__a21bo_2".
+Reading "KP_sky130_fd_sc_hd__or2_2".
+Reading "KP_M1M2_PR_R".
+Reading "KP_sky130_fd_sc_hd__mux2_4".
+Reading "KP_sky130_fd_sc_hd__a22o_1".
+Reading "KP_M1M2_PR_MR".
+Reading "KP_sky130_fd_sc_hd__or4_4".
+Reading "KP_sky130_fd_sc_hd__or4_2".
+Reading "KP_eFPGA_top_VIA29".
+Reading "KP_eFPGA_top_VIA30".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s18_2".
+Reading "KP_sky130_fd_sc_hd__or3_4".
+Reading "KP_sky130_fd_sc_hd__or3_2".
+Reading "KP_RAM_IO".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "KP_S_term_RAM_IO".
+Reading "KP_sky130_fd_sc_hd__buf_12".
+Reading "KP_M1M2_PR_M".
+Reading "KP_sky130_fd_sc_hd__mux2_1".
+Reading "KP_DSP".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+Reading "KP_S_term_DSP".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1".
+Reading "KP_sky130_fd_sc_hd__inv_6".
+Reading "KP_eFPGA_top_VIA10".
+Reading "KP_sky130_fd_sc_hd__diode_2".
+Reading "KP_LUT4AB".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+Reading "KP_S_term_single".
+Reading "KP_sky130_fd_sc_hd__bufbuf_8".
+Reading "KP_sky130_fd_sc_hd__nor2_2".
+Reading "KP_sky130_fd_sc_hd__clkbuf_8".
+Reading "KP_sky130_fd_sc_hd__nor2_1".
+Reading "KP_sky130_fd_sc_hd__buf_4".
+Reading "KP_eFPGA_top_VIA9".
+Reading "KP_eFPGA_top_VIA34".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "KP_eFPGA_top_VIA37".
+Reading "KP_eFPGA_top_VIA38".
+Reading "KP_eFPGA_top_VIA39".
+Reading "KP_sky130_fd_sc_hd__inv_4".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_2".
+Reading "KP_sky130_fd_sc_hd__buf_2".
+Reading "KP_sky130_fd_sc_hd__clkbuf_4".
+Reading "KP_sky130_fd_sc_hd__bufbuf_16".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1".
+Reading "KP_sky130_fd_sc_hd__clkbuf_2".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "KP_sky130_fd_sc_hd__buf_6".
+Reading "KP_sky130_fd_sc_hd__mux2_8".
+Reading "KP_sky130_fd_sc_hd__inv_2".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2".
+Reading "KP_sky130_fd_sc_hd__clkinv_4".
+Reading "KP_eFPGA_top_VIA18".
+Reading "KP_eFPGA_top_VIA4".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "KP_eFPGA_top_VIA32".
+Reading "KP_eFPGA_top_VIA31".
+Reading "KP_eFPGA_top_VIA5".
+Reading "KP_eFPGA_top_VIA15".
+Reading "KP_eFPGA_top_VIA33".
+Reading "KP_eFPGA_top_VIA16".
+Reading "KP_eFPGA_top_VIA17".
+Reading "KP_eFPGA_top_VIA14".
+Reading "KP_eFPGA_top_VIA1".
+Reading "KP_eFPGA_top_VIA3".
+Reading "KP_eFPGA_top_VIA12".
+Reading "KP_eFPGA_top_VIA2".
+Reading "KP_eFPGA_top_VIA13".
+Reading "KP_sky130_fd_sc_hd__conb_1".
+Reading "KP_sky130_fd_sc_hd__buf_1".
+Reading "KP_sky130_fd_sc_hd__buf_8".
+Reading "KP_sky130_fd_sc_hd__clkinv_8".
+Reading "KP_sky130_fd_sc_hd__clkinv_16".
+Reading "KP_sky130_fd_sc_hd__decap_8".
+Reading "KP_eFPGA_top_VIA0".
+Reading "KP_sky130_fd_sc_hd__fill_1".
+Reading "KP_M2M3_PR".
+Reading "KP_sky130_ef_sc_hd__decap_12".
+Moving label "VGND" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12.
+Moving label "VNB" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12.
+Moving label "decap_12" from space to metal1 in cell KP_sky130_ef_sc_hd__decap_12.
+Reading "KP_M3M4_PR".
+Reading "KP_eFPGA_top_VIA27".
+Reading "KP_L1M1_PR".
+Reading "KP_eFPGA_top_VIA28".
+Reading "KP_sky130_ef_sc_hd__fill_12".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "KP_M1M2_PR".
+Reading "KP_sky130_ef_sc_hd__fill_8".
+Reading "KP_eFPGA_top_VIA26".
+Reading "KP_eFPGA_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+    105000 uses
+    110000 uses
+    115000 uses
+    120000 uses
+    125000 uses
+    130000 uses
+    135000 uses
+    140000 uses
+    145000 uses
+    150000 uses
+    155000 uses
+    160000 uses
+    165000 uses
+    170000 uses
+    175000 uses
+    180000 uses
+    185000 uses
+    190000 uses
+Reading "user_project_wrapper".
+Reading "caravel".
+Flattening layout of tile x=0 y=0. . . 
+Flattening layout of tile x=1 y=0. . . 
+Flattening layout of tile x=2 y=0. . . 
+Flattening layout of tile x=3 y=0. . . 
+Flattening layout of tile x=4 y=0. . . 
+Flattening layout of tile x=5 y=0. . . 
+Flattening layout of tile x=0 y=1. . . 
+Flattening layout of tile x=1 y=1. . . 
+Flattening layout of tile x=2 y=1. . . 
+Flattening layout of tile x=3 y=1. . . 
+Flattening layout of tile x=4 y=1. . . 
+Flattening layout of tile x=5 y=1. . . 
+Flattening layout of tile x=0 y=2. . . 
+Flattening layout of tile x=1 y=2. . . 
+Flattening layout of tile x=2 y=2. . . 
+Flattening layout of tile x=3 y=2. . . 
+Flattening layout of tile x=4 y=2. . . 
+Flattening layout of tile x=5 y=2. . . 
+Flattening layout of tile x=0 y=3. . . 
+Flattening layout of tile x=1 y=3. . . 
+Flattening layout of tile x=2 y=3. . . 
+Flattening layout of tile x=3 y=3. . . 
+Flattening layout of tile x=4 y=3. . . 
+Flattening layout of tile x=5 y=3. . . 
+Flattening layout of tile x=0 y=4. . . 
+Flattening layout of tile x=1 y=4. . . 
+Flattening layout of tile x=2 y=4. . . 
+Flattening layout of tile x=3 y=4. . . 
+Flattening layout of tile x=4 y=4. . . 
+Flattening layout of tile x=5 y=4. . . 
+Flattening layout of tile x=0 y=5. . . 
+Flattening layout of tile x=1 y=5. . . 
+Flattening layout of tile x=2 y=5. . . 
+Flattening layout of tile x=3 y=5. . . 
+Flattening layout of tile x=4 y=5. . . 
+Flattening layout of tile x=5 y=5. . . 
+Flattening layout of tile x=0 y=6. . . 
+Flattening layout of tile x=1 y=6. . . 
+Flattening layout of tile x=2 y=6. . . 
+Flattening layout of tile x=3 y=6. . . 
+Flattening layout of tile x=4 y=6. . . 
+Flattening layout of tile x=5 y=6. . . 
+Flattening layout of tile x=0 y=7. . . 
+Flattening layout of tile x=1 y=7. . . 
+Flattening layout of tile x=2 y=7. . . 
+Flattening layout of tile x=3 y=7. . . 
+Flattening layout of tile x=4 y=7. . . 
+Flattening layout of tile x=5 y=7. . . 
+Error message output from magic:
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228174798): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228174830): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228177422): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228177454): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228177486): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228177518): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228177550): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 228177646): NODE elements not supported: skipping.
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_4_0: 10000 rects
+caravel_00020005_fill_pattern_4_0: 20000 rects
+caravel_00020005_fill_pattern_4_0: 30000 rects
+caravel_00020005_fill_pattern_4_0: 40000 rects
+caravel_00020005_fill_pattern_4_0: 50000 rects
+caravel_00020005_fill_pattern_4_0: 60000 rects
+caravel_00020005_fill_pattern_4_0: 70000 rects
+caravel_00020005_fill_pattern_4_0: 80000 rects
+caravel_00020005_fill_pattern_4_0: 90000 rects
+caravel_00020005_fill_pattern_4_0: 100000 rects
+caravel_00020005_fill_pattern_4_0: 110000 rects
+caravel_00020005_fill_pattern_4_0: 120000 rects
+caravel_00020005_fill_pattern_4_0: 130000 rects
+caravel_00020005_fill_pattern_4_0: 140000 rects
+caravel_00020005_fill_pattern_4_0: 150000 rects
+caravel_00020005_fill_pattern_4_0: 160000 rects
+caravel_00020005_fill_pattern_4_0: 170000 rects
+caravel_00020005_fill_pattern_4_0: 180000 rects
+caravel_00020005_fill_pattern_4_0: 190000 rects
+caravel_00020005_fill_pattern_4_0: 200000 rects
+caravel_00020005_fill_pattern_4_0: 210000 rects
+caravel_00020005_fill_pattern_4_0: 220000 rects
+caravel_00020005_fill_pattern_4_0: 230000 rects
+caravel_00020005_fill_pattern_4_0: 240000 rects
+caravel_00020005_fill_pattern_4_0: 250000 rects
+caravel_00020005_fill_pattern_4_0: 260000 rects
+caravel_00020005_fill_pattern_4_0: 270000 rects
+caravel_00020005_fill_pattern_4_0: 280000 rects
+caravel_00020005_fill_pattern_4_0: 290000 rects
+caravel_00020005_fill_pattern_4_0: 300000 rects
+caravel_00020005_fill_pattern_4_0: 310000 rects
+caravel_00020005_fill_pattern_4_0: 320000 rects
+caravel_00020005_fill_pattern_4_0: 330000 rects
+caravel_00020005_fill_pattern_4_0: 340000 rects
+caravel_00020005_fill_pattern_4_0: 350000 rects
+caravel_00020005_fill_pattern_4_0: 360000 rects
+caravel_00020005_fill_pattern_4_0: 370000 rects
+caravel_00020005_fill_pattern_4_0: 380000 rects
+caravel_00020005_fill_pattern_4_0: 390000 rects
+caravel_00020005_fill_pattern_4_0: 400000 rects
+caravel_00020005_fill_pattern_4_0: 410000 rects
+caravel_00020005_fill_pattern_4_0: 420000 rects
+caravel_00020005_fill_pattern_4_0: 430000 rects
+caravel_00020005_fill_pattern_4_0: 440000 rects
+caravel_00020005_fill_pattern_4_0: 450000 rects
+caravel_00020005_fill_pattern_4_0: 460000 rects
+caravel_00020005_fill_pattern_4_0: 470000 rects
+caravel_00020005_fill_pattern_4_0: 480000 rects
+caravel_00020005_fill_pattern_4_0: 490000 rects
+caravel_00020005_fill_pattern_4_0: 500000 rects
+caravel_00020005_fill_pattern_4_0: 510000 rects
+caravel_00020005_fill_pattern_4_0: 520000 rects
+caravel_00020005_fill_pattern_4_0: 530000 rects
+caravel_00020005_fill_pattern_4_0: 540000 rects
+caravel_00020005_fill_pattern_4_0: 550000 rects
+caravel_00020005_fill_pattern_4_0: 560000 rects
+caravel_00020005_fill_pattern_4_0: 570000 rects
+caravel_00020005_fill_pattern_4_0: 580000 rects
+caravel_00020005_fill_pattern_4_0: 590000 rects
+caravel_00020005_fill_pattern_4_0: 600000 rects
+caravel_00020005_fill_pattern_4_0: 610000 rects
+caravel_00020005_fill_pattern_4_0: 620000 rects
+caravel_00020005_fill_pattern_4_0: 630000 rects
+caravel_00020005_fill_pattern_4_0: 640000 rects
+caravel_00020005_fill_pattern_4_0: 650000 rects
+caravel_00020005_fill_pattern_4_0: 660000 rects
+caravel_00020005_fill_pattern_4_0: 670000 rects
+caravel_00020005_fill_pattern_4_0: 680000 rects
+caravel_00020005_fill_pattern_4_0: 690000 rects
+caravel_00020005_fill_pattern_4_0: 700000 rects
+caravel_00020005_fill_pattern_4_0: 710000 rects
+caravel_00020005_fill_pattern_4_0: 720000 rects
+caravel_00020005_fill_pattern_4_0: 730000 rects
+caravel_00020005_fill_pattern_4_0: 740000 rects
+caravel_00020005_fill_pattern_4_0: 750000 rects
+caravel_00020005_fill_pattern_4_0: 760000 rects
+caravel_00020005_fill_pattern_4_0: 770000 rects
+caravel_00020005_fill_pattern_4_0: 780000 rects
+caravel_00020005_fill_pattern_4_0: 790000 rects
+caravel_00020005_fill_pattern_4_0: 800000 rects
+caravel_00020005_fill_pattern_4_0: 810000 rects
+caravel_00020005_fill_pattern_4_0: 820000 rects
+caravel_00020005_fill_pattern_4_0: 830000 rects
+caravel_00020005_fill_pattern_4_0: 840000 rects
+caravel_00020005_fill_pattern_4_0: 850000 rects
+caravel_00020005_fill_pattern_4_0: 860000 rects
+caravel_00020005_fill_pattern_4_0: 870000 rects
+caravel_00020005_fill_pattern_4_0: 880000 rects
+caravel_00020005_fill_pattern_4_0: 890000 rects
+caravel_00020005_fill_pattern_4_0: 900000 rects
+caravel_00020005_fill_pattern_4_0: 910000 rects
+caravel_00020005_fill_pattern_4_0: 920000 rects
+caravel_00020005_fill_pattern_4_0: 930000 rects
+caravel_00020005_fill_pattern_4_0: 940000 rects
+caravel_00020005_fill_pattern_4_0: 950000 rects
+caravel_00020005_fill_pattern_4_0: 960000 rects
+caravel_00020005_fill_pattern_4_0: 970000 rects
+caravel_00020005_fill_pattern_4_0: 980000 rects
+caravel_00020005_fill_pattern_4_0: 990000 rects
+caravel_00020005_fill_pattern_4_0: 1000000 rects
+caravel_00020005_fill_pattern_4_0: 1010000 rects
+caravel_00020005_fill_pattern_4_0: 1020000 rects
+caravel_00020005_fill_pattern_4_0: 1030000 rects
+caravel_00020005_fill_pattern_4_0: 1040000 rects
+caravel_00020005_fill_pattern_4_0: 1050000 rects
+caravel_00020005_fill_pattern_4_0: 1060000 rects
+caravel_00020005_fill_pattern_4_0: 1070000 rects
+caravel_00020005_fill_pattern_4_0: 1080000 rects
+caravel_00020005_fill_pattern_4_0: 1090000 rects
+caravel_00020005_fill_pattern_4_0: 1100000 rects
+caravel_00020005_fill_pattern_4_0: 1110000 rects
+caravel_00020005_fill_pattern_4_0: 1120000 rects
+caravel_00020005_fill_pattern_4_0: 1130000 rects
+caravel_00020005_fill_pattern_4_0: 1140000 rects
+caravel_00020005_fill_pattern_4_0: 1150000 rects
+caravel_00020005_fill_pattern_4_0: 1160000 rects
+caravel_00020005_fill_pattern_4_0: 1170000 rects
+caravel_00020005_fill_pattern_4_0: 1180000 rects
+caravel_00020005_fill_pattern_4_0: 1190000 rects
+caravel_00020005_fill_pattern_4_0: 1200000 rects
+caravel_00020005_fill_pattern_4_0: 1210000 rects
+caravel_00020005_fill_pattern_4_0: 1220000 rects
+caravel_00020005_fill_pattern_4_0: 1230000 rects
+caravel_00020005_fill_pattern_4_0: 1240000 rects
+caravel_00020005_fill_pattern_4_0: 1250000 rects
+caravel_00020005_fill_pattern_4_0: 1260000 rects
+caravel_00020005_fill_pattern_4_0: 1270000 rects
+caravel_00020005_fill_pattern_4_0: 1280000 rects
+caravel_00020005_fill_pattern_4_0: 1290000 rects
+caravel_00020005_fill_pattern_4_0: 1300000 rects
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+caravel_00020005_fill_pattern_4_0: 1540000 rects
+caravel_00020005_fill_pattern_4_0: 1550000 rects
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_4_1: 10000 rects
+caravel_00020005_fill_pattern_4_1: 20000 rects
+caravel_00020005_fill_pattern_4_1: 30000 rects
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+caravel_00020005_fill_pattern_4_1: 1550000 rects
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_0_6: 10000 rects
+caravel_00020005_fill_pattern_0_6: 20000 rects
+caravel_00020005_fill_pattern_0_6: 30000 rects
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
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+caravel_00020005_fill_pattern_1_5: 11200000 rects
+caravel_00020005_fill_pattern_1_5: 11210000 rects
+caravel_00020005_fill_pattern_1_5: 11220000 rects
+caravel_00020005_fill_pattern_1_5: 11230000 rects
+caravel_00020005_fill_pattern_1_5: 11240000 rects
+caravel_00020005_fill_pattern_1_5: 11250000 rects
+caravel_00020005_fill_pattern_1_5: 11260000 rects
+caravel_00020005_fill_pattern_1_5: 11270000 rects
+caravel_00020005_fill_pattern_1_5: 11280000 rects
+caravel_00020005_fill_pattern_1_5: 11290000 rects
+caravel_00020005_fill_pattern_1_5: 11300000 rects
+caravel_00020005_fill_pattern_1_5: 11310000 rects
+caravel_00020005_fill_pattern_1_5: 11320000 rects
+caravel_00020005_fill_pattern_1_5: 11330000 rects
+caravel_00020005_fill_pattern_1_5: 11340000 rects
+caravel_00020005_fill_pattern_1_5: 11350000 rects
+caravel_00020005_fill_pattern_1_5: 11360000 rects
+caravel_00020005_fill_pattern_1_5: 11370000 rects
+caravel_00020005_fill_pattern_1_5: 11380000 rects
+caravel_00020005_fill_pattern_1_5: 11390000 rects
+caravel_00020005_fill_pattern_1_5: 11400000 rects
+caravel_00020005_fill_pattern_1_5: 11410000 rects
+caravel_00020005_fill_pattern_1_5: 11420000 rects
+caravel_00020005_fill_pattern_1_5: 11430000 rects
+caravel_00020005_fill_pattern_1_5: 11440000 rects
+caravel_00020005_fill_pattern_1_5: 11450000 rects
+caravel_00020005_fill_pattern_1_5: 11460000 rects
+caravel_00020005_fill_pattern_1_5: 11470000 rects
+caravel_00020005_fill_pattern_1_5: 11480000 rects
+caravel_00020005_fill_pattern_1_5: 11490000 rects
+caravel_00020005_fill_pattern_1_5: 11500000 rects
+caravel_00020005_fill_pattern_1_5: 11510000 rects
+caravel_00020005_fill_pattern_1_5: 11520000 rects
+caravel_00020005_fill_pattern_1_5: 11530000 rects
+caravel_00020005_fill_pattern_1_5: 11540000 rects
+caravel_00020005_fill_pattern_1_5: 11550000 rects
+caravel_00020005_fill_pattern_1_5: 11560000 rects
+caravel_00020005_fill_pattern_1_5: 11570000 rects
+caravel_00020005_fill_pattern_1_5: 11580000 rects
+caravel_00020005_fill_pattern_1_5: 11590000 rects
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_final.tcl" from command line.
+CIF output style is now "wafflefill(tiled)"
+Writing final GDS
+   Generating output for cell caravel_00020005_fill_pattern_0_0
+Reading "caravel_00020005_fill_pattern_0_0".
+   Generating output for cell caravel_00020005_fill_pattern_1_0
+Reading "caravel_00020005_fill_pattern_1_0".
+   Generating output for cell caravel_00020005_fill_pattern_0_1
+Reading "caravel_00020005_fill_pattern_0_1".
+   Generating output for cell caravel_00020005_fill_pattern_1_1
+Reading "caravel_00020005_fill_pattern_1_1".
+   Generating output for cell caravel_00020005_fill_pattern_2_0
+Reading "caravel_00020005_fill_pattern_2_0".
+   Generating output for cell caravel_00020005_fill_pattern_2_1
+Reading "caravel_00020005_fill_pattern_2_1".
+   Generating output for cell caravel_00020005_fill_pattern_3_0
+Reading "caravel_00020005_fill_pattern_3_0".
+   Generating output for cell caravel_00020005_fill_pattern_3_1
+Reading "caravel_00020005_fill_pattern_3_1".
+   Generating output for cell caravel_00020005_fill_pattern_4_0
+Reading "caravel_00020005_fill_pattern_4_0".
+   Generating output for cell caravel_00020005_fill_pattern_4_1
+Reading "caravel_00020005_fill_pattern_4_1".
+   Generating output for cell caravel_00020005_fill_pattern_5_0
+Reading "caravel_00020005_fill_pattern_5_0".
+   Generating output for cell caravel_00020005_fill_pattern_5_1
+Reading "caravel_00020005_fill_pattern_5_1".
+   Generating output for cell caravel_00020005_fill_pattern_0_2
+Reading "caravel_00020005_fill_pattern_0_2".
+   Generating output for cell caravel_00020005_fill_pattern_1_2
+Reading "caravel_00020005_fill_pattern_1_2".
+   Generating output for cell caravel_00020005_fill_pattern_2_2
+Reading "caravel_00020005_fill_pattern_2_2".
+   Generating output for cell caravel_00020005_fill_pattern_3_2
+Reading "caravel_00020005_fill_pattern_3_2".
+   Generating output for cell caravel_00020005_fill_pattern_4_2
+Reading "caravel_00020005_fill_pattern_4_2".
+   Generating output for cell caravel_00020005_fill_pattern_5_2
+Reading "caravel_00020005_fill_pattern_5_2".
+   Generating output for cell caravel_00020005_fill_pattern_0_3
+Reading "caravel_00020005_fill_pattern_0_3".
+   Generating output for cell caravel_00020005_fill_pattern_1_3
+Reading "caravel_00020005_fill_pattern_1_3".
+   Generating output for cell caravel_00020005_fill_pattern_2_3
+Reading "caravel_00020005_fill_pattern_2_3".
+   Generating output for cell caravel_00020005_fill_pattern_3_3
+Reading "caravel_00020005_fill_pattern_3_3".
+   Generating output for cell caravel_00020005_fill_pattern_4_3
+Reading "caravel_00020005_fill_pattern_4_3".
+   Generating output for cell caravel_00020005_fill_pattern_5_3
+Reading "caravel_00020005_fill_pattern_5_3".
+   Generating output for cell caravel_00020005_fill_pattern_0_4
+Reading "caravel_00020005_fill_pattern_0_4".
+   Generating output for cell caravel_00020005_fill_pattern_1_4
+   Generating output for cell caravel_00020005_fill_pattern_2_4
+Reading "caravel_00020005_fill_pattern_2_4".
+   Generating output for cell caravel_00020005_fill_pattern_3_4
+Reading "caravel_00020005_fill_pattern_3_4".
+   Generating output for cell caravel_00020005_fill_pattern_4_4
+Reading "caravel_00020005_fill_pattern_4_4".
+   Generating output for cell caravel_00020005_fill_pattern_5_4
+Reading "caravel_00020005_fill_pattern_5_4".
+   Generating output for cell caravel_00020005_fill_pattern_0_5
+Reading "caravel_00020005_fill_pattern_0_5".
+   Generating output for cell caravel_00020005_fill_pattern_1_5
+Reading "caravel_00020005_fill_pattern_1_5".
+   Generating output for cell caravel_00020005_fill_pattern_2_5
+Reading "caravel_00020005_fill_pattern_2_5".
+   Generating output for cell caravel_00020005_fill_pattern_3_5
+Reading "caravel_00020005_fill_pattern_3_5".
+   Generating output for cell caravel_00020005_fill_pattern_4_5
+Reading "caravel_00020005_fill_pattern_4_5".
+   Generating output for cell caravel_00020005_fill_pattern_5_5
+Reading "caravel_00020005_fill_pattern_5_5".
+   Generating output for cell caravel_00020005_fill_pattern_0_6
+Reading "caravel_00020005_fill_pattern_0_6".
+   Generating output for cell caravel_00020005_fill_pattern_1_6
+Reading "caravel_00020005_fill_pattern_1_6".
+   Generating output for cell caravel_00020005_fill_pattern_2_6
+Reading "caravel_00020005_fill_pattern_2_6".
+   Generating output for cell caravel_00020005_fill_pattern_3_6
+Reading "caravel_00020005_fill_pattern_3_6".
+   Generating output for cell caravel_00020005_fill_pattern_4_6
+Reading "caravel_00020005_fill_pattern_4_6".
+   Generating output for cell caravel_00020005_fill_pattern_5_6
+Reading "caravel_00020005_fill_pattern_5_6".
+   Generating output for cell caravel_00020005_fill_pattern_0_7
+Reading "caravel_00020005_fill_pattern_0_7".
+   Generating output for cell caravel_00020005_fill_pattern_1_7
+Reading "caravel_00020005_fill_pattern_1_7".
+   Generating output for cell caravel_00020005_fill_pattern_2_7
+Reading "caravel_00020005_fill_pattern_2_7".
+   Generating output for cell caravel_00020005_fill_pattern_3_7
+Reading "caravel_00020005_fill_pattern_3_7".
+   Generating output for cell caravel_00020005_fill_pattern_4_7
+Reading "caravel_00020005_fill_pattern_4_7".
+   Generating output for cell caravel_00020005_fill_pattern_5_7
+Reading "caravel_00020005_fill_pattern_5_7".
+   Generating output for cell caravel_00020005_fill_pattern
+Ended: 12/09/2021 16:57:04
+Error message output from magic:
+Error while reading cell "caravel_00020005_fill_pattern_1_4" (byte position 0): Unexpected EOF.
+Done!
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_7
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_5_3: 10000 rects
+caravel_00020005_fill_pattern_5_3: 20000 rects
+caravel_00020005_fill_pattern_5_3: 30000 rects
+caravel_00020005_fill_pattern_5_3: 40000 rects
+caravel_00020005_fill_pattern_5_3: 50000 rects
+caravel_00020005_fill_pattern_5_3: 60000 rects
+caravel_00020005_fill_pattern_5_3: 70000 rects
+caravel_00020005_fill_pattern_5_3: 80000 rects
+caravel_00020005_fill_pattern_5_3: 90000 rects
+caravel_00020005_fill_pattern_5_3: 100000 rects
+caravel_00020005_fill_pattern_5_3: 110000 rects
+caravel_00020005_fill_pattern_5_3: 120000 rects
+caravel_00020005_fill_pattern_5_3: 130000 rects
+caravel_00020005_fill_pattern_5_3: 140000 rects
+caravel_00020005_fill_pattern_5_3: 150000 rects
+caravel_00020005_fill_pattern_5_3: 160000 rects
+caravel_00020005_fill_pattern_5_3: 170000 rects
+caravel_00020005_fill_pattern_5_3: 180000 rects
+caravel_00020005_fill_pattern_5_3: 190000 rects
+caravel_00020005_fill_pattern_5_3: 200000 rects
+caravel_00020005_fill_pattern_5_3: 210000 rects
+caravel_00020005_fill_pattern_5_3: 220000 rects
+caravel_00020005_fill_pattern_5_3: 230000 rects
+caravel_00020005_fill_pattern_5_3: 240000 rects
+caravel_00020005_fill_pattern_5_3: 250000 rects
+caravel_00020005_fill_pattern_5_3: 260000 rects
+caravel_00020005_fill_pattern_5_3: 270000 rects
+caravel_00020005_fill_pattern_5_3: 280000 rects
+caravel_00020005_fill_pattern_5_3: 290000 rects
+caravel_00020005_fill_pattern_5_3: 300000 rects
+caravel_00020005_fill_pattern_5_3: 310000 rects
+caravel_00020005_fill_pattern_5_3: 320000 rects
+caravel_00020005_fill_pattern_5_3: 330000 rects
+caravel_00020005_fill_pattern_5_3: 340000 rects
+caravel_00020005_fill_pattern_5_3: 350000 rects
+caravel_00020005_fill_pattern_5_3: 360000 rects
+caravel_00020005_fill_pattern_5_3: 370000 rects
+caravel_00020005_fill_pattern_5_3: 380000 rects
+caravel_00020005_fill_pattern_5_3: 390000 rects
+caravel_00020005_fill_pattern_5_3: 400000 rects
+caravel_00020005_fill_pattern_5_3: 410000 rects
+caravel_00020005_fill_pattern_5_3: 420000 rects
+caravel_00020005_fill_pattern_5_3: 430000 rects
+caravel_00020005_fill_pattern_5_3: 440000 rects
+caravel_00020005_fill_pattern_5_3: 450000 rects
+caravel_00020005_fill_pattern_5_3: 460000 rects
+caravel_00020005_fill_pattern_5_3: 470000 rects
+caravel_00020005_fill_pattern_5_3: 480000 rects
+caravel_00020005_fill_pattern_5_3: 490000 rects
+caravel_00020005_fill_pattern_5_3: 500000 rects
+caravel_00020005_fill_pattern_5_3: 510000 rects
+caravel_00020005_fill_pattern_5_3: 520000 rects
+caravel_00020005_fill_pattern_5_3: 530000 rects
+caravel_00020005_fill_pattern_5_3: 540000 rects
+caravel_00020005_fill_pattern_5_3: 550000 rects
+caravel_00020005_fill_pattern_5_3: 560000 rects
+caravel_00020005_fill_pattern_5_3: 570000 rects
+caravel_00020005_fill_pattern_5_3: 580000 rects
+caravel_00020005_fill_pattern_5_3: 590000 rects
+caravel_00020005_fill_pattern_5_3: 600000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_3
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_5_0: 10000 rects
+caravel_00020005_fill_pattern_5_0: 20000 rects
+caravel_00020005_fill_pattern_5_0: 30000 rects
+caravel_00020005_fill_pattern_5_0: 40000 rects
+caravel_00020005_fill_pattern_5_0: 50000 rects
+caravel_00020005_fill_pattern_5_0: 60000 rects
+caravel_00020005_fill_pattern_5_0: 70000 rects
+caravel_00020005_fill_pattern_5_0: 80000 rects
+caravel_00020005_fill_pattern_5_0: 90000 rects
+caravel_00020005_fill_pattern_5_0: 100000 rects
+caravel_00020005_fill_pattern_5_0: 110000 rects
+caravel_00020005_fill_pattern_5_0: 120000 rects
+caravel_00020005_fill_pattern_5_0: 130000 rects
+caravel_00020005_fill_pattern_5_0: 140000 rects
+caravel_00020005_fill_pattern_5_0: 150000 rects
+caravel_00020005_fill_pattern_5_0: 160000 rects
+caravel_00020005_fill_pattern_5_0: 170000 rects
+caravel_00020005_fill_pattern_5_0: 180000 rects
+caravel_00020005_fill_pattern_5_0: 190000 rects
+caravel_00020005_fill_pattern_5_0: 200000 rects
+caravel_00020005_fill_pattern_5_0: 210000 rects
+caravel_00020005_fill_pattern_5_0: 220000 rects
+caravel_00020005_fill_pattern_5_0: 230000 rects
+caravel_00020005_fill_pattern_5_0: 240000 rects
+caravel_00020005_fill_pattern_5_0: 250000 rects
+caravel_00020005_fill_pattern_5_0: 260000 rects
+caravel_00020005_fill_pattern_5_0: 270000 rects
+caravel_00020005_fill_pattern_5_0: 280000 rects
+caravel_00020005_fill_pattern_5_0: 290000 rects
+caravel_00020005_fill_pattern_5_0: 300000 rects
+caravel_00020005_fill_pattern_5_0: 310000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_0
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_5_6: 10000 rects
+caravel_00020005_fill_pattern_5_6: 20000 rects
+caravel_00020005_fill_pattern_5_6: 30000 rects
+caravel_00020005_fill_pattern_5_6: 40000 rects
+caravel_00020005_fill_pattern_5_6: 50000 rects
+caravel_00020005_fill_pattern_5_6: 60000 rects
+caravel_00020005_fill_pattern_5_6: 70000 rects
+caravel_00020005_fill_pattern_5_6: 80000 rects
+caravel_00020005_fill_pattern_5_6: 90000 rects
+caravel_00020005_fill_pattern_5_6: 100000 rects
+caravel_00020005_fill_pattern_5_6: 110000 rects
+caravel_00020005_fill_pattern_5_6: 120000 rects
+caravel_00020005_fill_pattern_5_6: 130000 rects
+caravel_00020005_fill_pattern_5_6: 140000 rects
+caravel_00020005_fill_pattern_5_6: 150000 rects
+caravel_00020005_fill_pattern_5_6: 160000 rects
+caravel_00020005_fill_pattern_5_6: 170000 rects
+caravel_00020005_fill_pattern_5_6: 180000 rects
+caravel_00020005_fill_pattern_5_6: 190000 rects
+caravel_00020005_fill_pattern_5_6: 200000 rects
+caravel_00020005_fill_pattern_5_6: 210000 rects
+caravel_00020005_fill_pattern_5_6: 220000 rects
+caravel_00020005_fill_pattern_5_6: 230000 rects
+caravel_00020005_fill_pattern_5_6: 240000 rects
+caravel_00020005_fill_pattern_5_6: 250000 rects
+caravel_00020005_fill_pattern_5_6: 260000 rects
+caravel_00020005_fill_pattern_5_6: 270000 rects
+caravel_00020005_fill_pattern_5_6: 280000 rects
+caravel_00020005_fill_pattern_5_6: 290000 rects
+caravel_00020005_fill_pattern_5_6: 300000 rects
+caravel_00020005_fill_pattern_5_6: 310000 rects
+caravel_00020005_fill_pattern_5_6: 320000 rects
+caravel_00020005_fill_pattern_5_6: 330000 rects
+caravel_00020005_fill_pattern_5_6: 340000 rects
+caravel_00020005_fill_pattern_5_6: 350000 rects
+caravel_00020005_fill_pattern_5_6: 360000 rects
+caravel_00020005_fill_pattern_5_6: 370000 rects
+caravel_00020005_fill_pattern_5_6: 380000 rects
+caravel_00020005_fill_pattern_5_6: 390000 rects
+caravel_00020005_fill_pattern_5_6: 400000 rects
+caravel_00020005_fill_pattern_5_6: 410000 rects
+caravel_00020005_fill_pattern_5_6: 420000 rects
+caravel_00020005_fill_pattern_5_6: 430000 rects
+caravel_00020005_fill_pattern_5_6: 440000 rects
+caravel_00020005_fill_pattern_5_6: 450000 rects
+caravel_00020005_fill_pattern_5_6: 460000 rects
+caravel_00020005_fill_pattern_5_6: 470000 rects
+caravel_00020005_fill_pattern_5_6: 480000 rects
+caravel_00020005_fill_pattern_5_6: 490000 rects
+caravel_00020005_fill_pattern_5_6: 500000 rects
+caravel_00020005_fill_pattern_5_6: 510000 rects
+caravel_00020005_fill_pattern_5_6: 520000 rects
+caravel_00020005_fill_pattern_5_6: 530000 rects
+caravel_00020005_fill_pattern_5_6: 540000 rects
+caravel_00020005_fill_pattern_5_6: 550000 rects
+caravel_00020005_fill_pattern_5_6: 560000 rects
+caravel_00020005_fill_pattern_5_6: 570000 rects
+caravel_00020005_fill_pattern_5_6: 580000 rects
+caravel_00020005_fill_pattern_5_6: 590000 rects
+caravel_00020005_fill_pattern_5_6: 600000 rects
+caravel_00020005_fill_pattern_5_6: 610000 rects
+caravel_00020005_fill_pattern_5_6: 620000 rects
+caravel_00020005_fill_pattern_5_6: 630000 rects
+caravel_00020005_fill_pattern_5_6: 640000 rects
+caravel_00020005_fill_pattern_5_6: 650000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_6
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_5_5: 10000 rects
+caravel_00020005_fill_pattern_5_5: 20000 rects
+caravel_00020005_fill_pattern_5_5: 30000 rects
+caravel_00020005_fill_pattern_5_5: 40000 rects
+caravel_00020005_fill_pattern_5_5: 50000 rects
+caravel_00020005_fill_pattern_5_5: 60000 rects
+caravel_00020005_fill_pattern_5_5: 70000 rects
+caravel_00020005_fill_pattern_5_5: 80000 rects
+caravel_00020005_fill_pattern_5_5: 90000 rects
+caravel_00020005_fill_pattern_5_5: 100000 rects
+caravel_00020005_fill_pattern_5_5: 110000 rects
+caravel_00020005_fill_pattern_5_5: 120000 rects
+caravel_00020005_fill_pattern_5_5: 130000 rects
+caravel_00020005_fill_pattern_5_5: 140000 rects
+caravel_00020005_fill_pattern_5_5: 150000 rects
+caravel_00020005_fill_pattern_5_5: 160000 rects
+caravel_00020005_fill_pattern_5_5: 170000 rects
+caravel_00020005_fill_pattern_5_5: 180000 rects
+caravel_00020005_fill_pattern_5_5: 190000 rects
+caravel_00020005_fill_pattern_5_5: 200000 rects
+caravel_00020005_fill_pattern_5_5: 210000 rects
+caravel_00020005_fill_pattern_5_5: 220000 rects
+caravel_00020005_fill_pattern_5_5: 230000 rects
+caravel_00020005_fill_pattern_5_5: 240000 rects
+caravel_00020005_fill_pattern_5_5: 250000 rects
+caravel_00020005_fill_pattern_5_5: 260000 rects
+caravel_00020005_fill_pattern_5_5: 270000 rects
+caravel_00020005_fill_pattern_5_5: 280000 rects
+caravel_00020005_fill_pattern_5_5: 290000 rects
+caravel_00020005_fill_pattern_5_5: 300000 rects
+caravel_00020005_fill_pattern_5_5: 310000 rects
+caravel_00020005_fill_pattern_5_5: 320000 rects
+caravel_00020005_fill_pattern_5_5: 330000 rects
+caravel_00020005_fill_pattern_5_5: 340000 rects
+caravel_00020005_fill_pattern_5_5: 350000 rects
+caravel_00020005_fill_pattern_5_5: 360000 rects
+caravel_00020005_fill_pattern_5_5: 370000 rects
+caravel_00020005_fill_pattern_5_5: 380000 rects
+caravel_00020005_fill_pattern_5_5: 390000 rects
+caravel_00020005_fill_pattern_5_5: 400000 rects
+caravel_00020005_fill_pattern_5_5: 410000 rects
+caravel_00020005_fill_pattern_5_5: 420000 rects
+caravel_00020005_fill_pattern_5_5: 430000 rects
+caravel_00020005_fill_pattern_5_5: 440000 rects
+caravel_00020005_fill_pattern_5_5: 450000 rects
+caravel_00020005_fill_pattern_5_5: 460000 rects
+caravel_00020005_fill_pattern_5_5: 470000 rects
+caravel_00020005_fill_pattern_5_5: 480000 rects
+caravel_00020005_fill_pattern_5_5: 490000 rects
+caravel_00020005_fill_pattern_5_5: 500000 rects
+caravel_00020005_fill_pattern_5_5: 510000 rects
+caravel_00020005_fill_pattern_5_5: 520000 rects
+caravel_00020005_fill_pattern_5_5: 530000 rects
+caravel_00020005_fill_pattern_5_5: 540000 rects
+caravel_00020005_fill_pattern_5_5: 550000 rects
+caravel_00020005_fill_pattern_5_5: 560000 rects
+caravel_00020005_fill_pattern_5_5: 570000 rects
+caravel_00020005_fill_pattern_5_5: 580000 rects
+caravel_00020005_fill_pattern_5_5: 590000 rects
+caravel_00020005_fill_pattern_5_5: 600000 rects
+caravel_00020005_fill_pattern_5_5: 610000 rects
+caravel_00020005_fill_pattern_5_5: 620000 rects
+caravel_00020005_fill_pattern_5_5: 630000 rects
+caravel_00020005_fill_pattern_5_5: 640000 rects
+caravel_00020005_fill_pattern_5_5: 650000 rects
+caravel_00020005_fill_pattern_5_5: 660000 rects
+caravel_00020005_fill_pattern_5_5: 670000 rects
+caravel_00020005_fill_pattern_5_5: 680000 rects
+caravel_00020005_fill_pattern_5_5: 690000 rects
+caravel_00020005_fill_pattern_5_5: 700000 rects
+caravel_00020005_fill_pattern_5_5: 710000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_5
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_5_1: 10000 rects
+caravel_00020005_fill_pattern_5_1: 20000 rects
+caravel_00020005_fill_pattern_5_1: 30000 rects
+caravel_00020005_fill_pattern_5_1: 40000 rects
+caravel_00020005_fill_pattern_5_1: 50000 rects
+caravel_00020005_fill_pattern_5_1: 60000 rects
+caravel_00020005_fill_pattern_5_1: 70000 rects
+caravel_00020005_fill_pattern_5_1: 80000 rects
+caravel_00020005_fill_pattern_5_1: 90000 rects
+caravel_00020005_fill_pattern_5_1: 100000 rects
+caravel_00020005_fill_pattern_5_1: 110000 rects
+caravel_00020005_fill_pattern_5_1: 120000 rects
+caravel_00020005_fill_pattern_5_1: 130000 rects
+caravel_00020005_fill_pattern_5_1: 140000 rects
+caravel_00020005_fill_pattern_5_1: 150000 rects
+caravel_00020005_fill_pattern_5_1: 160000 rects
+caravel_00020005_fill_pattern_5_1: 170000 rects
+caravel_00020005_fill_pattern_5_1: 180000 rects
+caravel_00020005_fill_pattern_5_1: 190000 rects
+caravel_00020005_fill_pattern_5_1: 200000 rects
+caravel_00020005_fill_pattern_5_1: 210000 rects
+caravel_00020005_fill_pattern_5_1: 220000 rects
+caravel_00020005_fill_pattern_5_1: 230000 rects
+caravel_00020005_fill_pattern_5_1: 240000 rects
+caravel_00020005_fill_pattern_5_1: 250000 rects
+caravel_00020005_fill_pattern_5_1: 260000 rects
+caravel_00020005_fill_pattern_5_1: 270000 rects
+caravel_00020005_fill_pattern_5_1: 280000 rects
+caravel_00020005_fill_pattern_5_1: 290000 rects
+caravel_00020005_fill_pattern_5_1: 300000 rects
+caravel_00020005_fill_pattern_5_1: 310000 rects
+caravel_00020005_fill_pattern_5_1: 320000 rects
+caravel_00020005_fill_pattern_5_1: 330000 rects
+caravel_00020005_fill_pattern_5_1: 340000 rects
+caravel_00020005_fill_pattern_5_1: 350000 rects
+caravel_00020005_fill_pattern_5_1: 360000 rects
+caravel_00020005_fill_pattern_5_1: 370000 rects
+caravel_00020005_fill_pattern_5_1: 380000 rects
+caravel_00020005_fill_pattern_5_1: 390000 rects
+caravel_00020005_fill_pattern_5_1: 400000 rects
+caravel_00020005_fill_pattern_5_1: 410000 rects
+caravel_00020005_fill_pattern_5_1: 420000 rects
+caravel_00020005_fill_pattern_5_1: 430000 rects
+caravel_00020005_fill_pattern_5_1: 440000 rects
+caravel_00020005_fill_pattern_5_1: 450000 rects
+caravel_00020005_fill_pattern_5_1: 460000 rects
+caravel_00020005_fill_pattern_5_1: 470000 rects
+caravel_00020005_fill_pattern_5_1: 480000 rects
+caravel_00020005_fill_pattern_5_1: 490000 rects
+caravel_00020005_fill_pattern_5_1: 500000 rects
+caravel_00020005_fill_pattern_5_1: 510000 rects
+caravel_00020005_fill_pattern_5_1: 520000 rects
+caravel_00020005_fill_pattern_5_1: 530000 rects
+caravel_00020005_fill_pattern_5_1: 540000 rects
+caravel_00020005_fill_pattern_5_1: 550000 rects
+caravel_00020005_fill_pattern_5_1: 560000 rects
+caravel_00020005_fill_pattern_5_1: 570000 rects
+caravel_00020005_fill_pattern_5_1: 580000 rects
+caravel_00020005_fill_pattern_5_1: 590000 rects
+caravel_00020005_fill_pattern_5_1: 600000 rects
+caravel_00020005_fill_pattern_5_1: 610000 rects
+caravel_00020005_fill_pattern_5_1: 620000 rects
+caravel_00020005_fill_pattern_5_1: 630000 rects
+caravel_00020005_fill_pattern_5_1: 640000 rects
+caravel_00020005_fill_pattern_5_1: 650000 rects
+caravel_00020005_fill_pattern_5_1: 660000 rects
+caravel_00020005_fill_pattern_5_1: 670000 rects
+caravel_00020005_fill_pattern_5_1: 680000 rects
+caravel_00020005_fill_pattern_5_1: 690000 rects
+caravel_00020005_fill_pattern_5_1: 700000 rects
+caravel_00020005_fill_pattern_5_1: 710000 rects
+caravel_00020005_fill_pattern_5_1: 720000 rects
+caravel_00020005_fill_pattern_5_1: 730000 rects
+caravel_00020005_fill_pattern_5_1: 740000 rects
+caravel_00020005_fill_pattern_5_1: 750000 rects
+caravel_00020005_fill_pattern_5_1: 760000 rects
+caravel_00020005_fill_pattern_5_1: 770000 rects
+caravel_00020005_fill_pattern_5_1: 780000 rects
+caravel_00020005_fill_pattern_5_1: 790000 rects
+caravel_00020005_fill_pattern_5_1: 800000 rects
+caravel_00020005_fill_pattern_5_1: 810000 rects
+caravel_00020005_fill_pattern_5_1: 820000 rects
+caravel_00020005_fill_pattern_5_1: 830000 rects
+caravel_00020005_fill_pattern_5_1: 840000 rects
+caravel_00020005_fill_pattern_5_1: 850000 rects
+caravel_00020005_fill_pattern_5_1: 860000 rects
+caravel_00020005_fill_pattern_5_1: 870000 rects
+caravel_00020005_fill_pattern_5_1: 880000 rects
+caravel_00020005_fill_pattern_5_1: 890000 rects
+caravel_00020005_fill_pattern_5_1: 900000 rects
+caravel_00020005_fill_pattern_5_1: 910000 rects
+caravel_00020005_fill_pattern_5_1: 920000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_1
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_5_2: 10000 rects
+caravel_00020005_fill_pattern_5_2: 20000 rects
+caravel_00020005_fill_pattern_5_2: 30000 rects
+caravel_00020005_fill_pattern_5_2: 40000 rects
+caravel_00020005_fill_pattern_5_2: 50000 rects
+caravel_00020005_fill_pattern_5_2: 60000 rects
+caravel_00020005_fill_pattern_5_2: 70000 rects
+caravel_00020005_fill_pattern_5_2: 80000 rects
+caravel_00020005_fill_pattern_5_2: 90000 rects
+caravel_00020005_fill_pattern_5_2: 100000 rects
+caravel_00020005_fill_pattern_5_2: 110000 rects
+caravel_00020005_fill_pattern_5_2: 120000 rects
+caravel_00020005_fill_pattern_5_2: 130000 rects
+caravel_00020005_fill_pattern_5_2: 140000 rects
+caravel_00020005_fill_pattern_5_2: 150000 rects
+caravel_00020005_fill_pattern_5_2: 160000 rects
+caravel_00020005_fill_pattern_5_2: 170000 rects
+caravel_00020005_fill_pattern_5_2: 180000 rects
+caravel_00020005_fill_pattern_5_2: 190000 rects
+caravel_00020005_fill_pattern_5_2: 200000 rects
+caravel_00020005_fill_pattern_5_2: 210000 rects
+caravel_00020005_fill_pattern_5_2: 220000 rects
+caravel_00020005_fill_pattern_5_2: 230000 rects
+caravel_00020005_fill_pattern_5_2: 240000 rects
+caravel_00020005_fill_pattern_5_2: 250000 rects
+caravel_00020005_fill_pattern_5_2: 260000 rects
+caravel_00020005_fill_pattern_5_2: 270000 rects
+caravel_00020005_fill_pattern_5_2: 280000 rects
+caravel_00020005_fill_pattern_5_2: 290000 rects
+caravel_00020005_fill_pattern_5_2: 300000 rects
+caravel_00020005_fill_pattern_5_2: 310000 rects
+caravel_00020005_fill_pattern_5_2: 320000 rects
+caravel_00020005_fill_pattern_5_2: 330000 rects
+caravel_00020005_fill_pattern_5_2: 340000 rects
+caravel_00020005_fill_pattern_5_2: 350000 rects
+caravel_00020005_fill_pattern_5_2: 360000 rects
+caravel_00020005_fill_pattern_5_2: 370000 rects
+caravel_00020005_fill_pattern_5_2: 380000 rects
+caravel_00020005_fill_pattern_5_2: 390000 rects
+caravel_00020005_fill_pattern_5_2: 400000 rects
+caravel_00020005_fill_pattern_5_2: 410000 rects
+caravel_00020005_fill_pattern_5_2: 420000 rects
+caravel_00020005_fill_pattern_5_2: 430000 rects
+caravel_00020005_fill_pattern_5_2: 440000 rects
+caravel_00020005_fill_pattern_5_2: 450000 rects
+caravel_00020005_fill_pattern_5_2: 460000 rects
+caravel_00020005_fill_pattern_5_2: 470000 rects
+caravel_00020005_fill_pattern_5_2: 480000 rects
+caravel_00020005_fill_pattern_5_2: 490000 rects
+caravel_00020005_fill_pattern_5_2: 500000 rects
+caravel_00020005_fill_pattern_5_2: 510000 rects
+caravel_00020005_fill_pattern_5_2: 520000 rects
+caravel_00020005_fill_pattern_5_2: 530000 rects
+caravel_00020005_fill_pattern_5_2: 540000 rects
+caravel_00020005_fill_pattern_5_2: 550000 rects
+caravel_00020005_fill_pattern_5_2: 560000 rects
+caravel_00020005_fill_pattern_5_2: 570000 rects
+caravel_00020005_fill_pattern_5_2: 580000 rects
+caravel_00020005_fill_pattern_5_2: 590000 rects
+caravel_00020005_fill_pattern_5_2: 600000 rects
+caravel_00020005_fill_pattern_5_2: 610000 rects
+caravel_00020005_fill_pattern_5_2: 620000 rects
+caravel_00020005_fill_pattern_5_2: 630000 rects
+caravel_00020005_fill_pattern_5_2: 640000 rects
+caravel_00020005_fill_pattern_5_2: 650000 rects
+caravel_00020005_fill_pattern_5_2: 660000 rects
+caravel_00020005_fill_pattern_5_2: 670000 rects
+caravel_00020005_fill_pattern_5_2: 680000 rects
+caravel_00020005_fill_pattern_5_2: 690000 rects
+caravel_00020005_fill_pattern_5_2: 700000 rects
+caravel_00020005_fill_pattern_5_2: 710000 rects
+caravel_00020005_fill_pattern_5_2: 720000 rects
+caravel_00020005_fill_pattern_5_2: 730000 rects
+caravel_00020005_fill_pattern_5_2: 740000 rects
+caravel_00020005_fill_pattern_5_2: 750000 rects
+caravel_00020005_fill_pattern_5_2: 760000 rects
+caravel_00020005_fill_pattern_5_2: 770000 rects
+caravel_00020005_fill_pattern_5_2: 780000 rects
+caravel_00020005_fill_pattern_5_2: 790000 rects
+caravel_00020005_fill_pattern_5_2: 800000 rects
+caravel_00020005_fill_pattern_5_2: 810000 rects
+caravel_00020005_fill_pattern_5_2: 820000 rects
+caravel_00020005_fill_pattern_5_2: 830000 rects
+caravel_00020005_fill_pattern_5_2: 840000 rects
+caravel_00020005_fill_pattern_5_2: 850000 rects
+caravel_00020005_fill_pattern_5_2: 860000 rects
+caravel_00020005_fill_pattern_5_2: 870000 rects
+caravel_00020005_fill_pattern_5_2: 880000 rects
+caravel_00020005_fill_pattern_5_2: 890000 rects
+caravel_00020005_fill_pattern_5_2: 900000 rects
+caravel_00020005_fill_pattern_5_2: 910000 rects
+caravel_00020005_fill_pattern_5_2: 920000 rects
+caravel_00020005_fill_pattern_5_2: 930000 rects
+caravel_00020005_fill_pattern_5_2: 940000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_2
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_5_4: 10000 rects
+caravel_00020005_fill_pattern_5_4: 20000 rects
+caravel_00020005_fill_pattern_5_4: 30000 rects
+caravel_00020005_fill_pattern_5_4: 40000 rects
+caravel_00020005_fill_pattern_5_4: 50000 rects
+caravel_00020005_fill_pattern_5_4: 60000 rects
+caravel_00020005_fill_pattern_5_4: 70000 rects
+caravel_00020005_fill_pattern_5_4: 80000 rects
+caravel_00020005_fill_pattern_5_4: 90000 rects
+caravel_00020005_fill_pattern_5_4: 100000 rects
+caravel_00020005_fill_pattern_5_4: 110000 rects
+caravel_00020005_fill_pattern_5_4: 120000 rects
+caravel_00020005_fill_pattern_5_4: 130000 rects
+caravel_00020005_fill_pattern_5_4: 140000 rects
+caravel_00020005_fill_pattern_5_4: 150000 rects
+caravel_00020005_fill_pattern_5_4: 160000 rects
+caravel_00020005_fill_pattern_5_4: 170000 rects
+caravel_00020005_fill_pattern_5_4: 180000 rects
+caravel_00020005_fill_pattern_5_4: 190000 rects
+caravel_00020005_fill_pattern_5_4: 200000 rects
+caravel_00020005_fill_pattern_5_4: 210000 rects
+caravel_00020005_fill_pattern_5_4: 220000 rects
+caravel_00020005_fill_pattern_5_4: 230000 rects
+caravel_00020005_fill_pattern_5_4: 240000 rects
+caravel_00020005_fill_pattern_5_4: 250000 rects
+caravel_00020005_fill_pattern_5_4: 260000 rects
+caravel_00020005_fill_pattern_5_4: 270000 rects
+caravel_00020005_fill_pattern_5_4: 280000 rects
+caravel_00020005_fill_pattern_5_4: 290000 rects
+caravel_00020005_fill_pattern_5_4: 300000 rects
+caravel_00020005_fill_pattern_5_4: 310000 rects
+caravel_00020005_fill_pattern_5_4: 320000 rects
+caravel_00020005_fill_pattern_5_4: 330000 rects
+caravel_00020005_fill_pattern_5_4: 340000 rects
+caravel_00020005_fill_pattern_5_4: 350000 rects
+caravel_00020005_fill_pattern_5_4: 360000 rects
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+caravel_00020005_fill_pattern_5_4: 430000 rects
+caravel_00020005_fill_pattern_5_4: 440000 rects
+caravel_00020005_fill_pattern_5_4: 450000 rects
+caravel_00020005_fill_pattern_5_4: 460000 rects
+caravel_00020005_fill_pattern_5_4: 470000 rects
+caravel_00020005_fill_pattern_5_4: 480000 rects
+caravel_00020005_fill_pattern_5_4: 490000 rects
+caravel_00020005_fill_pattern_5_4: 500000 rects
+caravel_00020005_fill_pattern_5_4: 510000 rects
+caravel_00020005_fill_pattern_5_4: 520000 rects
+caravel_00020005_fill_pattern_5_4: 530000 rects
+caravel_00020005_fill_pattern_5_4: 540000 rects
+caravel_00020005_fill_pattern_5_4: 550000 rects
+caravel_00020005_fill_pattern_5_4: 560000 rects
+caravel_00020005_fill_pattern_5_4: 570000 rects
+caravel_00020005_fill_pattern_5_4: 580000 rects
+caravel_00020005_fill_pattern_5_4: 590000 rects
+caravel_00020005_fill_pattern_5_4: 600000 rects
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+caravel_00020005_fill_pattern_5_4: 680000 rects
+caravel_00020005_fill_pattern_5_4: 690000 rects
+caravel_00020005_fill_pattern_5_4: 700000 rects
+caravel_00020005_fill_pattern_5_4: 710000 rects
+caravel_00020005_fill_pattern_5_4: 720000 rects
+caravel_00020005_fill_pattern_5_4: 730000 rects
+caravel_00020005_fill_pattern_5_4: 740000 rects
+caravel_00020005_fill_pattern_5_4: 750000 rects
+caravel_00020005_fill_pattern_5_4: 760000 rects
+caravel_00020005_fill_pattern_5_4: 770000 rects
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+caravel_00020005_fill_pattern_5_4: 790000 rects
+caravel_00020005_fill_pattern_5_4: 800000 rects
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+caravel_00020005_fill_pattern_5_4: 830000 rects
+caravel_00020005_fill_pattern_5_4: 840000 rects
+caravel_00020005_fill_pattern_5_4: 850000 rects
+caravel_00020005_fill_pattern_5_4: 860000 rects
+caravel_00020005_fill_pattern_5_4: 870000 rects
+caravel_00020005_fill_pattern_5_4: 880000 rects
+caravel_00020005_fill_pattern_5_4: 890000 rects
+caravel_00020005_fill_pattern_5_4: 900000 rects
+caravel_00020005_fill_pattern_5_4: 910000 rects
+caravel_00020005_fill_pattern_5_4: 920000 rects
+caravel_00020005_fill_pattern_5_4: 930000 rects
+caravel_00020005_fill_pattern_5_4: 940000 rects
+caravel_00020005_fill_pattern_5_4: 950000 rects
+caravel_00020005_fill_pattern_5_4: 960000 rects
+caravel_00020005_fill_pattern_5_4: 970000 rects
+caravel_00020005_fill_pattern_5_4: 980000 rects
+caravel_00020005_fill_pattern_5_4: 990000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_5_4
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_4_7: 10000 rects
+caravel_00020005_fill_pattern_4_7: 20000 rects
+caravel_00020005_fill_pattern_4_7: 30000 rects
+caravel_00020005_fill_pattern_4_7: 40000 rects
+caravel_00020005_fill_pattern_4_7: 50000 rects
+caravel_00020005_fill_pattern_4_7: 60000 rects
+caravel_00020005_fill_pattern_4_7: 70000 rects
+caravel_00020005_fill_pattern_4_7: 80000 rects
+caravel_00020005_fill_pattern_4_7: 90000 rects
+caravel_00020005_fill_pattern_4_7: 100000 rects
+caravel_00020005_fill_pattern_4_7: 110000 rects
+caravel_00020005_fill_pattern_4_7: 120000 rects
+caravel_00020005_fill_pattern_4_7: 130000 rects
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+caravel_00020005_fill_pattern_4_7: 160000 rects
+caravel_00020005_fill_pattern_4_7: 170000 rects
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+caravel_00020005_fill_pattern_4_7: 260000 rects
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+caravel_00020005_fill_pattern_4_7: 760000 rects
+caravel_00020005_fill_pattern_4_7: 770000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_7
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_3_7: 10000 rects
+caravel_00020005_fill_pattern_3_7: 20000 rects
+caravel_00020005_fill_pattern_3_7: 30000 rects
+caravel_00020005_fill_pattern_3_7: 40000 rects
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+caravel_00020005_fill_pattern_3_7: 100000 rects
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+caravel_00020005_fill_pattern_3_7: 1000000 rects
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+caravel_00020005_fill_pattern_3_7: 1210000 rects
+caravel_00020005_fill_pattern_3_7: 1220000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_7
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_2_7: 10000 rects
+caravel_00020005_fill_pattern_2_7: 20000 rects
+caravel_00020005_fill_pattern_2_7: 30000 rects
+caravel_00020005_fill_pattern_2_7: 40000 rects
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+caravel_00020005_fill_pattern_2_7: 1010000 rects
+caravel_00020005_fill_pattern_2_7: 1020000 rects
+caravel_00020005_fill_pattern_2_7: 1030000 rects
+caravel_00020005_fill_pattern_2_7: 1040000 rects
+caravel_00020005_fill_pattern_2_7: 1050000 rects
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+caravel_00020005_fill_pattern_2_7: 1070000 rects
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+caravel_00020005_fill_pattern_2_7: 1090000 rects
+caravel_00020005_fill_pattern_2_7: 1100000 rects
+caravel_00020005_fill_pattern_2_7: 1110000 rects
+caravel_00020005_fill_pattern_2_7: 1120000 rects
+caravel_00020005_fill_pattern_2_7: 1130000 rects
+caravel_00020005_fill_pattern_2_7: 1140000 rects
+caravel_00020005_fill_pattern_2_7: 1150000 rects
+caravel_00020005_fill_pattern_2_7: 1160000 rects
+caravel_00020005_fill_pattern_2_7: 1170000 rects
+caravel_00020005_fill_pattern_2_7: 1180000 rects
+caravel_00020005_fill_pattern_2_7: 1190000 rects
+caravel_00020005_fill_pattern_2_7: 1200000 rects
+caravel_00020005_fill_pattern_2_7: 1210000 rects
+caravel_00020005_fill_pattern_2_7: 1220000 rects
+caravel_00020005_fill_pattern_2_7: 1230000 rects
+caravel_00020005_fill_pattern_2_7: 1240000 rects
+caravel_00020005_fill_pattern_2_7: 1250000 rects
+caravel_00020005_fill_pattern_2_7: 1260000 rects
+caravel_00020005_fill_pattern_2_7: 1270000 rects
+caravel_00020005_fill_pattern_2_7: 1280000 rects
+caravel_00020005_fill_pattern_2_7: 1290000 rects
+caravel_00020005_fill_pattern_2_7: 1300000 rects
+caravel_00020005_fill_pattern_2_7: 1310000 rects
+caravel_00020005_fill_pattern_2_7: 1320000 rects
+caravel_00020005_fill_pattern_2_7: 1330000 rects
+caravel_00020005_fill_pattern_2_7: 1340000 rects
+caravel_00020005_fill_pattern_2_7: 1350000 rects
+caravel_00020005_fill_pattern_2_7: 1360000 rects
+caravel_00020005_fill_pattern_2_7: 1370000 rects
+caravel_00020005_fill_pattern_2_7: 1380000 rects
+caravel_00020005_fill_pattern_2_7: 1390000 rects
+caravel_00020005_fill_pattern_2_7: 1400000 rects
+caravel_00020005_fill_pattern_2_7: 1410000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_7
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_1_7: 10000 rects
+caravel_00020005_fill_pattern_1_7: 20000 rects
+caravel_00020005_fill_pattern_1_7: 30000 rects
+caravel_00020005_fill_pattern_1_7: 40000 rects
+caravel_00020005_fill_pattern_1_7: 50000 rects
+caravel_00020005_fill_pattern_1_7: 60000 rects
+caravel_00020005_fill_pattern_1_7: 70000 rects
+caravel_00020005_fill_pattern_1_7: 80000 rects
+caravel_00020005_fill_pattern_1_7: 90000 rects
+caravel_00020005_fill_pattern_1_7: 100000 rects
+caravel_00020005_fill_pattern_1_7: 110000 rects
+caravel_00020005_fill_pattern_1_7: 120000 rects
+caravel_00020005_fill_pattern_1_7: 130000 rects
+caravel_00020005_fill_pattern_1_7: 140000 rects
+caravel_00020005_fill_pattern_1_7: 150000 rects
+caravel_00020005_fill_pattern_1_7: 160000 rects
+caravel_00020005_fill_pattern_1_7: 170000 rects
+caravel_00020005_fill_pattern_1_7: 180000 rects
+caravel_00020005_fill_pattern_1_7: 190000 rects
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+caravel_00020005_fill_pattern_1_7: 1160000 rects
+caravel_00020005_fill_pattern_1_7: 1170000 rects
+caravel_00020005_fill_pattern_1_7: 1180000 rects
+caravel_00020005_fill_pattern_1_7: 1190000 rects
+caravel_00020005_fill_pattern_1_7: 1200000 rects
+caravel_00020005_fill_pattern_1_7: 1210000 rects
+caravel_00020005_fill_pattern_1_7: 1220000 rects
+caravel_00020005_fill_pattern_1_7: 1230000 rects
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+caravel_00020005_fill_pattern_1_7: 1250000 rects
+caravel_00020005_fill_pattern_1_7: 1260000 rects
+caravel_00020005_fill_pattern_1_7: 1270000 rects
+caravel_00020005_fill_pattern_1_7: 1280000 rects
+caravel_00020005_fill_pattern_1_7: 1290000 rects
+caravel_00020005_fill_pattern_1_7: 1300000 rects
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+caravel_00020005_fill_pattern_1_7: 1320000 rects
+caravel_00020005_fill_pattern_1_7: 1330000 rects
+caravel_00020005_fill_pattern_1_7: 1340000 rects
+caravel_00020005_fill_pattern_1_7: 1350000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_7
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/generate_fill_dist.tcl" from command line.
+caravel_00020005_fill_pattern_0_7: 10000 rects
+caravel_00020005_fill_pattern_0_7: 20000 rects
+caravel_00020005_fill_pattern_0_7: 30000 rects
+caravel_00020005_fill_pattern_0_7: 40000 rects
+caravel_00020005_fill_pattern_0_7: 50000 rects
+caravel_00020005_fill_pattern_0_7: 60000 rects
+caravel_00020005_fill_pattern_0_7: 70000 rects
+caravel_00020005_fill_pattern_0_7: 80000 rects
+caravel_00020005_fill_pattern_0_7: 90000 rects
+caravel_00020005_fill_pattern_0_7: 100000 rects
+caravel_00020005_fill_pattern_0_7: 110000 rects
+caravel_00020005_fill_pattern_0_7: 120000 rects
+caravel_00020005_fill_pattern_0_7: 130000 rects
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+caravel_00020005_fill_pattern_0_7: 400000 rects
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+caravel_00020005_fill_pattern_0_7: 980000 rects
+caravel_00020005_fill_pattern_0_7: 990000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_0_7
+
+caravel_00020005_fill_pattern_4_0: 1560000 rects
+caravel_00020005_fill_pattern_4_0: 1570000 rects
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+caravel_00020005_fill_pattern_4_0: 2400000 rects
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+caravel_00020005_fill_pattern_4_0: 2430000 rects
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+caravel_00020005_fill_pattern_4_0: 2450000 rects
+caravel_00020005_fill_pattern_4_0: 2460000 rects
+caravel_00020005_fill_pattern_4_0: 2470000 rects
+caravel_00020005_fill_pattern_4_0: 2480000 rects
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+caravel_00020005_fill_pattern_4_0: 2510000 rects
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+caravel_00020005_fill_pattern_4_0: 2550000 rects
+caravel_00020005_fill_pattern_4_0: 2560000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_0
+
+caravel_00020005_fill_pattern_4_1: 1560000 rects
+caravel_00020005_fill_pattern_4_1: 1570000 rects
+caravel_00020005_fill_pattern_4_1: 1580000 rects
+caravel_00020005_fill_pattern_4_1: 1590000 rects
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+caravel_00020005_fill_pattern_4_1: 1750000 rects
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+caravel_00020005_fill_pattern_4_1: 3090000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_1
+
+caravel_00020005_fill_pattern_0_6: 3240000 rects
+caravel_00020005_fill_pattern_0_6: 3250000 rects
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+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_0_6
+
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_4
+
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+caravel_00020005_fill_pattern_1_1: 3810000 rects
+caravel_00020005_fill_pattern_1_1: 3820000 rects
+caravel_00020005_fill_pattern_1_1: 3830000 rects
+caravel_00020005_fill_pattern_1_1: 3840000 rects
+caravel_00020005_fill_pattern_1_1: 3850000 rects
+caravel_00020005_fill_pattern_1_1: 3860000 rects
+caravel_00020005_fill_pattern_1_1: 3870000 rects
+caravel_00020005_fill_pattern_1_1: 3880000 rects
+caravel_00020005_fill_pattern_1_1: 3890000 rects
+caravel_00020005_fill_pattern_1_1: 3900000 rects
+caravel_00020005_fill_pattern_1_1: 3910000 rects
+caravel_00020005_fill_pattern_1_1: 3920000 rects
+caravel_00020005_fill_pattern_1_1: 3930000 rects
+caravel_00020005_fill_pattern_1_1: 3940000 rects
+caravel_00020005_fill_pattern_1_1: 3950000 rects
+caravel_00020005_fill_pattern_1_1: 3960000 rects
+caravel_00020005_fill_pattern_1_1: 3970000 rects
+caravel_00020005_fill_pattern_1_1: 3980000 rects
+caravel_00020005_fill_pattern_1_1: 3990000 rects
+caravel_00020005_fill_pattern_1_1: 4000000 rects
+caravel_00020005_fill_pattern_1_1: 4010000 rects
+caravel_00020005_fill_pattern_1_1: 4020000 rects
+caravel_00020005_fill_pattern_1_1: 4030000 rects
+caravel_00020005_fill_pattern_1_1: 4040000 rects
+caravel_00020005_fill_pattern_1_1: 4050000 rects
+caravel_00020005_fill_pattern_1_1: 4060000 rects
+caravel_00020005_fill_pattern_1_1: 4070000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_1
+
+caravel_00020005_fill_pattern_0_4: 4920000 rects
+caravel_00020005_fill_pattern_0_4: 4930000 rects
+caravel_00020005_fill_pattern_0_4: 4940000 rects
+caravel_00020005_fill_pattern_0_4: 4950000 rects
+caravel_00020005_fill_pattern_0_4: 4960000 rects
+caravel_00020005_fill_pattern_0_4: 4970000 rects
+caravel_00020005_fill_pattern_0_4: 4980000 rects
+caravel_00020005_fill_pattern_0_4: 4990000 rects
+caravel_00020005_fill_pattern_0_4: 5000000 rects
+caravel_00020005_fill_pattern_0_4: 5010000 rects
+caravel_00020005_fill_pattern_0_4: 5020000 rects
+caravel_00020005_fill_pattern_0_4: 5030000 rects
+caravel_00020005_fill_pattern_0_4: 5040000 rects
+caravel_00020005_fill_pattern_0_4: 5050000 rects
+caravel_00020005_fill_pattern_0_4: 5060000 rects
+caravel_00020005_fill_pattern_0_4: 5070000 rects
+caravel_00020005_fill_pattern_0_4: 5080000 rects
+caravel_00020005_fill_pattern_0_4: 5090000 rects
+caravel_00020005_fill_pattern_0_4: 5100000 rects
+caravel_00020005_fill_pattern_0_4: 5110000 rects
+caravel_00020005_fill_pattern_0_4: 5120000 rects
+caravel_00020005_fill_pattern_0_4: 5130000 rects
+caravel_00020005_fill_pattern_0_4: 5140000 rects
+caravel_00020005_fill_pattern_0_4: 5150000 rects
+caravel_00020005_fill_pattern_0_4: 5160000 rects
+caravel_00020005_fill_pattern_0_4: 5170000 rects
+caravel_00020005_fill_pattern_0_4: 5180000 rects
+caravel_00020005_fill_pattern_0_4: 5190000 rects
+caravel_00020005_fill_pattern_0_4: 5200000 rects
+caravel_00020005_fill_pattern_0_4: 5210000 rects
+caravel_00020005_fill_pattern_0_4: 5220000 rects
+caravel_00020005_fill_pattern_0_4: 5230000 rects
+caravel_00020005_fill_pattern_0_4: 5240000 rects
+caravel_00020005_fill_pattern_0_4: 5250000 rects
+caravel_00020005_fill_pattern_0_4: 5260000 rects
+caravel_00020005_fill_pattern_0_4: 5270000 rects
+caravel_00020005_fill_pattern_0_4: 5280000 rects
+caravel_00020005_fill_pattern_0_4: 5290000 rects
+caravel_00020005_fill_pattern_0_4: 5300000 rects
+caravel_00020005_fill_pattern_0_4: 5310000 rects
+caravel_00020005_fill_pattern_0_4: 5320000 rects
+caravel_00020005_fill_pattern_0_4: 5330000 rects
+caravel_00020005_fill_pattern_0_4: 5340000 rects
+caravel_00020005_fill_pattern_0_4: 5350000 rects
+caravel_00020005_fill_pattern_0_4: 5360000 rects
+caravel_00020005_fill_pattern_0_4: 5370000 rects
+caravel_00020005_fill_pattern_0_4: 5380000 rects
+caravel_00020005_fill_pattern_0_4: 5390000 rects
+caravel_00020005_fill_pattern_0_4: 5400000 rects
+caravel_00020005_fill_pattern_0_4: 5410000 rects
+caravel_00020005_fill_pattern_0_4: 5420000 rects
+caravel_00020005_fill_pattern_0_4: 5430000 rects
+caravel_00020005_fill_pattern_0_4: 5440000 rects
+caravel_00020005_fill_pattern_0_4: 5450000 rects
+caravel_00020005_fill_pattern_0_4: 5460000 rects
+caravel_00020005_fill_pattern_0_4: 5470000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_0_4
+
+caravel_00020005_fill_pattern_0_1: 4920000 rects
+caravel_00020005_fill_pattern_0_1: 4930000 rects
+caravel_00020005_fill_pattern_0_1: 4940000 rects
+caravel_00020005_fill_pattern_0_1: 4950000 rects
+caravel_00020005_fill_pattern_0_1: 4960000 rects
+caravel_00020005_fill_pattern_0_1: 4970000 rects
+caravel_00020005_fill_pattern_0_1: 4980000 rects
+caravel_00020005_fill_pattern_0_1: 4990000 rects
+caravel_00020005_fill_pattern_0_1: 5000000 rects
+caravel_00020005_fill_pattern_0_1: 5010000 rects
+caravel_00020005_fill_pattern_0_1: 5020000 rects
+caravel_00020005_fill_pattern_0_1: 5030000 rects
+caravel_00020005_fill_pattern_0_1: 5040000 rects
+caravel_00020005_fill_pattern_0_1: 5050000 rects
+caravel_00020005_fill_pattern_0_1: 5060000 rects
+caravel_00020005_fill_pattern_0_1: 5070000 rects
+caravel_00020005_fill_pattern_0_1: 5080000 rects
+caravel_00020005_fill_pattern_0_1: 5090000 rects
+caravel_00020005_fill_pattern_0_1: 5100000 rects
+caravel_00020005_fill_pattern_0_1: 5110000 rects
+caravel_00020005_fill_pattern_0_1: 5120000 rects
+caravel_00020005_fill_pattern_0_1: 5130000 rects
+caravel_00020005_fill_pattern_0_1: 5140000 rects
+caravel_00020005_fill_pattern_0_1: 5150000 rects
+caravel_00020005_fill_pattern_0_1: 5160000 rects
+caravel_00020005_fill_pattern_0_1: 5170000 rects
+caravel_00020005_fill_pattern_0_1: 5180000 rects
+caravel_00020005_fill_pattern_0_1: 5190000 rects
+caravel_00020005_fill_pattern_0_1: 5200000 rects
+caravel_00020005_fill_pattern_0_1: 5210000 rects
+caravel_00020005_fill_pattern_0_1: 5220000 rects
+caravel_00020005_fill_pattern_0_1: 5230000 rects
+caravel_00020005_fill_pattern_0_1: 5240000 rects
+caravel_00020005_fill_pattern_0_1: 5250000 rects
+caravel_00020005_fill_pattern_0_1: 5260000 rects
+caravel_00020005_fill_pattern_0_1: 5270000 rects
+caravel_00020005_fill_pattern_0_1: 5280000 rects
+caravel_00020005_fill_pattern_0_1: 5290000 rects
+caravel_00020005_fill_pattern_0_1: 5300000 rects
+caravel_00020005_fill_pattern_0_1: 5310000 rects
+caravel_00020005_fill_pattern_0_1: 5320000 rects
+caravel_00020005_fill_pattern_0_1: 5330000 rects
+caravel_00020005_fill_pattern_0_1: 5340000 rects
+caravel_00020005_fill_pattern_0_1: 5350000 rects
+caravel_00020005_fill_pattern_0_1: 5360000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_0_1
+
+   Generating output for cell caravel_00020005_fill_pattern_0_2
+
+caravel_00020005_fill_pattern_0_5: 4920000 rects
+caravel_00020005_fill_pattern_0_5: 4930000 rects
+caravel_00020005_fill_pattern_0_5: 4940000 rects
+caravel_00020005_fill_pattern_0_5: 4950000 rects
+caravel_00020005_fill_pattern_0_5: 4960000 rects
+caravel_00020005_fill_pattern_0_5: 4970000 rects
+caravel_00020005_fill_pattern_0_5: 4980000 rects
+caravel_00020005_fill_pattern_0_5: 4990000 rects
+caravel_00020005_fill_pattern_0_5: 5000000 rects
+caravel_00020005_fill_pattern_0_5: 5010000 rects
+caravel_00020005_fill_pattern_0_5: 5020000 rects
+caravel_00020005_fill_pattern_0_5: 5030000 rects
+caravel_00020005_fill_pattern_0_5: 5040000 rects
+caravel_00020005_fill_pattern_0_5: 5050000 rects
+caravel_00020005_fill_pattern_0_5: 5060000 rects
+caravel_00020005_fill_pattern_0_5: 5070000 rects
+caravel_00020005_fill_pattern_0_5: 5080000 rects
+caravel_00020005_fill_pattern_0_5: 5090000 rects
+caravel_00020005_fill_pattern_0_5: 5100000 rects
+caravel_00020005_fill_pattern_0_5: 5110000 rects
+caravel_00020005_fill_pattern_0_5: 5120000 rects
+caravel_00020005_fill_pattern_0_5: 5130000 rects
+caravel_00020005_fill_pattern_0_5: 5140000 rects
+caravel_00020005_fill_pattern_0_5: 5150000 rects
+caravel_00020005_fill_pattern_0_5: 5160000 rects
+caravel_00020005_fill_pattern_0_5: 5170000 rects
+caravel_00020005_fill_pattern_0_5: 5180000 rects
+caravel_00020005_fill_pattern_0_5: 5190000 rects
+caravel_00020005_fill_pattern_0_5: 5200000 rects
+caravel_00020005_fill_pattern_0_5: 5210000 rects
+caravel_00020005_fill_pattern_0_5: 5220000 rects
+caravel_00020005_fill_pattern_0_5: 5230000 rects
+caravel_00020005_fill_pattern_0_5: 5240000 rects
+caravel_00020005_fill_pattern_0_5: 5250000 rects
+caravel_00020005_fill_pattern_0_5: 5260000 rects
+caravel_00020005_fill_pattern_0_5: 5270000 rects
+caravel_00020005_fill_pattern_0_5: 5280000 rects
+caravel_00020005_fill_pattern_0_5: 5290000 rects
+caravel_00020005_fill_pattern_0_5: 5300000 rects
+caravel_00020005_fill_pattern_0_5: 5310000 rects
+caravel_00020005_fill_pattern_0_5: 5320000 rects
+caravel_00020005_fill_pattern_0_5: 5330000 rects
+caravel_00020005_fill_pattern_0_5: 5340000 rects
+caravel_00020005_fill_pattern_0_5: 5350000 rects
+caravel_00020005_fill_pattern_0_5: 5360000 rects
+caravel_00020005_fill_pattern_0_5: 5370000 rects
+caravel_00020005_fill_pattern_0_5: 5380000 rects
+caravel_00020005_fill_pattern_0_5: 5390000 rects
+caravel_00020005_fill_pattern_0_5: 5400000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_0_5
+
+caravel_00020005_fill_pattern_0_3: 4920000 rects
+caravel_00020005_fill_pattern_0_3: 4930000 rects
+caravel_00020005_fill_pattern_0_3: 4940000 rects
+caravel_00020005_fill_pattern_0_3: 4950000 rects
+caravel_00020005_fill_pattern_0_3: 4960000 rects
+caravel_00020005_fill_pattern_0_3: 4970000 rects
+caravel_00020005_fill_pattern_0_3: 4980000 rects
+caravel_00020005_fill_pattern_0_3: 4990000 rects
+caravel_00020005_fill_pattern_0_3: 5000000 rects
+caravel_00020005_fill_pattern_0_3: 5010000 rects
+caravel_00020005_fill_pattern_0_3: 5020000 rects
+caravel_00020005_fill_pattern_0_3: 5030000 rects
+caravel_00020005_fill_pattern_0_3: 5040000 rects
+caravel_00020005_fill_pattern_0_3: 5050000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_0_3
+
+caravel_00020005_fill_pattern_3_1: 3240000 rects
+caravel_00020005_fill_pattern_3_1: 3250000 rects
+caravel_00020005_fill_pattern_3_1: 3260000 rects
+caravel_00020005_fill_pattern_3_1: 3270000 rects
+caravel_00020005_fill_pattern_3_1: 3280000 rects
+caravel_00020005_fill_pattern_3_1: 3290000 rects
+caravel_00020005_fill_pattern_3_1: 3300000 rects
+caravel_00020005_fill_pattern_3_1: 3310000 rects
+caravel_00020005_fill_pattern_3_1: 3320000 rects
+caravel_00020005_fill_pattern_3_1: 3330000 rects
+caravel_00020005_fill_pattern_3_1: 3340000 rects
+caravel_00020005_fill_pattern_3_1: 3350000 rects
+caravel_00020005_fill_pattern_3_1: 3360000 rects
+caravel_00020005_fill_pattern_3_1: 3370000 rects
+caravel_00020005_fill_pattern_3_1: 3380000 rects
+caravel_00020005_fill_pattern_3_1: 3390000 rects
+caravel_00020005_fill_pattern_3_1: 3400000 rects
+caravel_00020005_fill_pattern_3_1: 3410000 rects
+caravel_00020005_fill_pattern_3_1: 3420000 rects
+caravel_00020005_fill_pattern_3_1: 3430000 rects
+caravel_00020005_fill_pattern_3_1: 3440000 rects
+caravel_00020005_fill_pattern_3_1: 3450000 rects
+caravel_00020005_fill_pattern_3_1: 3460000 rects
+caravel_00020005_fill_pattern_3_1: 3470000 rects
+caravel_00020005_fill_pattern_3_1: 3480000 rects
+caravel_00020005_fill_pattern_3_1: 3490000 rects
+caravel_00020005_fill_pattern_3_1: 3500000 rects
+caravel_00020005_fill_pattern_3_1: 3510000 rects
+caravel_00020005_fill_pattern_3_1: 3520000 rects
+caravel_00020005_fill_pattern_3_1: 3530000 rects
+caravel_00020005_fill_pattern_3_1: 3540000 rects
+caravel_00020005_fill_pattern_3_1: 3550000 rects
+caravel_00020005_fill_pattern_3_1: 3560000 rects
+caravel_00020005_fill_pattern_3_1: 3570000 rects
+caravel_00020005_fill_pattern_3_1: 3580000 rects
+caravel_00020005_fill_pattern_3_1: 3590000 rects
+caravel_00020005_fill_pattern_3_1: 3600000 rects
+caravel_00020005_fill_pattern_3_1: 3610000 rects
+caravel_00020005_fill_pattern_3_1: 3620000 rects
+caravel_00020005_fill_pattern_3_1: 3630000 rects
+caravel_00020005_fill_pattern_3_1: 3640000 rects
+caravel_00020005_fill_pattern_3_1: 3650000 rects
+caravel_00020005_fill_pattern_3_1: 3660000 rects
+caravel_00020005_fill_pattern_3_1: 3670000 rects
+caravel_00020005_fill_pattern_3_1: 3680000 rects
+caravel_00020005_fill_pattern_3_1: 3690000 rects
+caravel_00020005_fill_pattern_3_1: 3700000 rects
+caravel_00020005_fill_pattern_3_1: 3710000 rects
+caravel_00020005_fill_pattern_3_1: 3720000 rects
+caravel_00020005_fill_pattern_3_1: 3730000 rects
+caravel_00020005_fill_pattern_3_1: 3740000 rects
+caravel_00020005_fill_pattern_3_1: 3750000 rects
+caravel_00020005_fill_pattern_3_1: 3760000 rects
+caravel_00020005_fill_pattern_3_1: 3770000 rects
+caravel_00020005_fill_pattern_3_1: 3780000 rects
+caravel_00020005_fill_pattern_3_1: 3790000 rects
+caravel_00020005_fill_pattern_3_1: 3800000 rects
+caravel_00020005_fill_pattern_3_1: 3810000 rects
+caravel_00020005_fill_pattern_3_1: 3820000 rects
+caravel_00020005_fill_pattern_3_1: 3830000 rects
+caravel_00020005_fill_pattern_3_1: 3840000 rects
+caravel_00020005_fill_pattern_3_1: 3850000 rects
+caravel_00020005_fill_pattern_3_1: 3860000 rects
+caravel_00020005_fill_pattern_3_1: 3870000 rects
+caravel_00020005_fill_pattern_3_1: 3880000 rects
+caravel_00020005_fill_pattern_3_1: 3890000 rects
+caravel_00020005_fill_pattern_3_1: 3900000 rects
+caravel_00020005_fill_pattern_3_1: 3910000 rects
+caravel_00020005_fill_pattern_3_1: 3920000 rects
+caravel_00020005_fill_pattern_3_1: 3930000 rects
+caravel_00020005_fill_pattern_3_1: 3940000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_1
+
+caravel_00020005_fill_pattern_4_3: 3240000 rects
+caravel_00020005_fill_pattern_4_3: 3250000 rects
+caravel_00020005_fill_pattern_4_3: 3260000 rects
+caravel_00020005_fill_pattern_4_3: 3270000 rects
+caravel_00020005_fill_pattern_4_3: 3280000 rects
+caravel_00020005_fill_pattern_4_3: 3290000 rects
+caravel_00020005_fill_pattern_4_3: 3300000 rects
+caravel_00020005_fill_pattern_4_3: 3310000 rects
+caravel_00020005_fill_pattern_4_3: 3320000 rects
+caravel_00020005_fill_pattern_4_3: 3330000 rects
+caravel_00020005_fill_pattern_4_3: 3340000 rects
+caravel_00020005_fill_pattern_4_3: 3350000 rects
+caravel_00020005_fill_pattern_4_3: 3360000 rects
+caravel_00020005_fill_pattern_4_3: 3370000 rects
+caravel_00020005_fill_pattern_4_3: 3380000 rects
+caravel_00020005_fill_pattern_4_3: 3390000 rects
+caravel_00020005_fill_pattern_4_3: 3400000 rects
+caravel_00020005_fill_pattern_4_3: 3410000 rects
+caravel_00020005_fill_pattern_4_3: 3420000 rects
+caravel_00020005_fill_pattern_4_3: 3430000 rects
+caravel_00020005_fill_pattern_4_3: 3440000 rects
+caravel_00020005_fill_pattern_4_3: 3450000 rects
+caravel_00020005_fill_pattern_4_3: 3460000 rects
+caravel_00020005_fill_pattern_4_3: 3470000 rects
+caravel_00020005_fill_pattern_4_3: 3480000 rects
+caravel_00020005_fill_pattern_4_3: 3490000 rects
+caravel_00020005_fill_pattern_4_3: 3500000 rects
+caravel_00020005_fill_pattern_4_3: 3510000 rects
+caravel_00020005_fill_pattern_4_3: 3520000 rects
+caravel_00020005_fill_pattern_4_3: 3530000 rects
+caravel_00020005_fill_pattern_4_3: 3540000 rects
+caravel_00020005_fill_pattern_4_3: 3550000 rects
+caravel_00020005_fill_pattern_4_3: 3560000 rects
+caravel_00020005_fill_pattern_4_3: 3570000 rects
+caravel_00020005_fill_pattern_4_3: 3580000 rects
+caravel_00020005_fill_pattern_4_3: 3590000 rects
+caravel_00020005_fill_pattern_4_3: 3600000 rects
+caravel_00020005_fill_pattern_4_3: 3610000 rects
+caravel_00020005_fill_pattern_4_3: 3620000 rects
+caravel_00020005_fill_pattern_4_3: 3630000 rects
+caravel_00020005_fill_pattern_4_3: 3640000 rects
+caravel_00020005_fill_pattern_4_3: 3650000 rects
+caravel_00020005_fill_pattern_4_3: 3660000 rects
+caravel_00020005_fill_pattern_4_3: 3670000 rects
+caravel_00020005_fill_pattern_4_3: 3680000 rects
+caravel_00020005_fill_pattern_4_3: 3690000 rects
+caravel_00020005_fill_pattern_4_3: 3700000 rects
+caravel_00020005_fill_pattern_4_3: 3710000 rects
+caravel_00020005_fill_pattern_4_3: 3720000 rects
+caravel_00020005_fill_pattern_4_3: 3730000 rects
+caravel_00020005_fill_pattern_4_3: 3740000 rects
+caravel_00020005_fill_pattern_4_3: 3750000 rects
+caravel_00020005_fill_pattern_4_3: 3760000 rects
+caravel_00020005_fill_pattern_4_3: 3770000 rects
+caravel_00020005_fill_pattern_4_3: 3780000 rects
+caravel_00020005_fill_pattern_4_3: 3790000 rects
+caravel_00020005_fill_pattern_4_3: 3800000 rects
+caravel_00020005_fill_pattern_4_3: 3810000 rects
+caravel_00020005_fill_pattern_4_3: 3820000 rects
+caravel_00020005_fill_pattern_4_3: 3830000 rects
+caravel_00020005_fill_pattern_4_3: 3840000 rects
+caravel_00020005_fill_pattern_4_3: 3850000 rects
+caravel_00020005_fill_pattern_4_3: 3860000 rects
+caravel_00020005_fill_pattern_4_3: 3870000 rects
+caravel_00020005_fill_pattern_4_3: 3880000 rects
+caravel_00020005_fill_pattern_4_3: 3890000 rects
+caravel_00020005_fill_pattern_4_3: 3900000 rects
+caravel_00020005_fill_pattern_4_3: 3910000 rects
+caravel_00020005_fill_pattern_4_3: 3920000 rects
+caravel_00020005_fill_pattern_4_3: 3930000 rects
+caravel_00020005_fill_pattern_4_3: 3940000 rects
+caravel_00020005_fill_pattern_4_3: 3950000 rects
+caravel_00020005_fill_pattern_4_3: 3960000 rects
+caravel_00020005_fill_pattern_4_3: 3970000 rects
+caravel_00020005_fill_pattern_4_3: 3980000 rects
+caravel_00020005_fill_pattern_4_3: 3990000 rects
+caravel_00020005_fill_pattern_4_3: 4000000 rects
+caravel_00020005_fill_pattern_4_3: 4010000 rects
+caravel_00020005_fill_pattern_4_3: 4020000 rects
+caravel_00020005_fill_pattern_4_3: 4030000 rects
+caravel_00020005_fill_pattern_4_3: 4040000 rects
+caravel_00020005_fill_pattern_4_3: 4050000 rects
+caravel_00020005_fill_pattern_4_3: 4060000 rects
+caravel_00020005_fill_pattern_4_3: 4070000 rects
+caravel_00020005_fill_pattern_4_3: 4080000 rects
+caravel_00020005_fill_pattern_4_3: 4090000 rects
+caravel_00020005_fill_pattern_4_3: 4100000 rects
+caravel_00020005_fill_pattern_4_3: 4110000 rects
+caravel_00020005_fill_pattern_4_3: 4120000 rects
+caravel_00020005_fill_pattern_4_3: 4130000 rects
+caravel_00020005_fill_pattern_4_3: 4140000 rects
+caravel_00020005_fill_pattern_4_3: 4150000 rects
+caravel_00020005_fill_pattern_4_3: 4160000 rects
+caravel_00020005_fill_pattern_4_3: 4170000 rects
+caravel_00020005_fill_pattern_4_3: 4180000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_3
+
+caravel_00020005_fill_pattern_4_6: 3240000 rects
+caravel_00020005_fill_pattern_4_6: 3250000 rects
+caravel_00020005_fill_pattern_4_6: 3260000 rects
+caravel_00020005_fill_pattern_4_6: 3270000 rects
+caravel_00020005_fill_pattern_4_6: 3280000 rects
+caravel_00020005_fill_pattern_4_6: 3290000 rects
+caravel_00020005_fill_pattern_4_6: 3300000 rects
+caravel_00020005_fill_pattern_4_6: 3310000 rects
+caravel_00020005_fill_pattern_4_6: 3320000 rects
+caravel_00020005_fill_pattern_4_6: 3330000 rects
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+caravel_00020005_fill_pattern_4_6: 3350000 rects
+caravel_00020005_fill_pattern_4_6: 3360000 rects
+caravel_00020005_fill_pattern_4_6: 3370000 rects
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+caravel_00020005_fill_pattern_4_6: 3390000 rects
+caravel_00020005_fill_pattern_4_6: 3400000 rects
+caravel_00020005_fill_pattern_4_6: 3410000 rects
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+caravel_00020005_fill_pattern_4_6: 3430000 rects
+caravel_00020005_fill_pattern_4_6: 3440000 rects
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+caravel_00020005_fill_pattern_4_6: 4100000 rects
+caravel_00020005_fill_pattern_4_6: 4110000 rects
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+caravel_00020005_fill_pattern_4_6: 4130000 rects
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+caravel_00020005_fill_pattern_4_6: 4180000 rects
+caravel_00020005_fill_pattern_4_6: 4190000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_6
+
+caravel_00020005_fill_pattern_0_0: 4920000 rects
+caravel_00020005_fill_pattern_0_0: 4930000 rects
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+caravel_00020005_fill_pattern_0_0: 6220000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_0_0
+
+caravel_00020005_fill_pattern_4_2: 3240000 rects
+caravel_00020005_fill_pattern_4_2: 3250000 rects
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+caravel_00020005_fill_pattern_4_2: 4150000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_2
+
+caravel_00020005_fill_pattern_4_5: 3240000 rects
+caravel_00020005_fill_pattern_4_5: 3250000 rects
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+caravel_00020005_fill_pattern_4_5: 4090000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_5
+
+caravel_00020005_fill_pattern_2_1: 3240000 rects
+caravel_00020005_fill_pattern_2_1: 3250000 rects
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+caravel_00020005_fill_pattern_2_1: 4820000 rects
+caravel_00020005_fill_pattern_2_1: 4830000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_1
+
+caravel_00020005_fill_pattern_3_0: 4920000 rects
+caravel_00020005_fill_pattern_3_0: 4930000 rects
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+caravel_00020005_fill_pattern_3_0: 5970000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_0
+
+caravel_00020005_fill_pattern_3_2: 8280000 rects
+caravel_00020005_fill_pattern_3_2: 8290000 rects
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+caravel_00020005_fill_pattern_3_2: 8400000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_2
+
+caravel_00020005_fill_pattern_4_4: 4920000 rects
+caravel_00020005_fill_pattern_4_4: 4930000 rects
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+caravel_00020005_fill_pattern_4_4: 5090000 rects
+caravel_00020005_fill_pattern_4_4: 5100000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_4_4
+
+caravel_00020005_fill_pattern_2_0: 4920000 rects
+caravel_00020005_fill_pattern_2_0: 4930000 rects
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+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_0
+
+caravel_00020005_fill_pattern_3_3: 9960000 rects
+caravel_00020005_fill_pattern_3_3: 9970000 rects
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+caravel_00020005_fill_pattern_3_3: 10070000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_3
+
+caravel_00020005_fill_pattern_3_6: 8280000 rects
+caravel_00020005_fill_pattern_3_6: 8290000 rects
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+caravel_00020005_fill_pattern_3_6: 9030000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_6
+
+caravel_00020005_fill_pattern_3_5: 9960000 rects
+caravel_00020005_fill_pattern_3_5: 9970000 rects
+caravel_00020005_fill_pattern_3_5: 9980000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_5
+
+caravel_00020005_fill_pattern_2_2: 8280000 rects
+caravel_00020005_fill_pattern_2_2: 8290000 rects
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+caravel_00020005_fill_pattern_2_2: 9570000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_2
+
+caravel_00020005_fill_pattern_3_4: 9960000 rects
+caravel_00020005_fill_pattern_3_4: 9970000 rects
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+caravel_00020005_fill_pattern_3_4: 9990000 rects
+caravel_00020005_fill_pattern_3_4: 10000000 rects
+caravel_00020005_fill_pattern_3_4: 10010000 rects
+caravel_00020005_fill_pattern_3_4: 10020000 rects
+caravel_00020005_fill_pattern_3_4: 10030000 rects
+caravel_00020005_fill_pattern_3_4: 10040000 rects
+caravel_00020005_fill_pattern_3_4: 10050000 rects
+caravel_00020005_fill_pattern_3_4: 10060000 rects
+caravel_00020005_fill_pattern_3_4: 10070000 rects
+caravel_00020005_fill_pattern_3_4: 10080000 rects
+caravel_00020005_fill_pattern_3_4: 10090000 rects
+caravel_00020005_fill_pattern_3_4: 10100000 rects
+caravel_00020005_fill_pattern_3_4: 10110000 rects
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+caravel_00020005_fill_pattern_3_4: 10150000 rects
+caravel_00020005_fill_pattern_3_4: 10160000 rects
+caravel_00020005_fill_pattern_3_4: 10170000 rects
+caravel_00020005_fill_pattern_3_4: 10180000 rects
+caravel_00020005_fill_pattern_3_4: 10190000 rects
+caravel_00020005_fill_pattern_3_4: 10200000 rects
+caravel_00020005_fill_pattern_3_4: 10210000 rects
+caravel_00020005_fill_pattern_3_4: 10220000 rects
+caravel_00020005_fill_pattern_3_4: 10230000 rects
+caravel_00020005_fill_pattern_3_4: 10240000 rects
+caravel_00020005_fill_pattern_3_4: 10250000 rects
+caravel_00020005_fill_pattern_3_4: 10260000 rects
+caravel_00020005_fill_pattern_3_4: 10270000 rects
+caravel_00020005_fill_pattern_3_4: 10280000 rects
+caravel_00020005_fill_pattern_3_4: 10290000 rects
+caravel_00020005_fill_pattern_3_4: 10300000 rects
+caravel_00020005_fill_pattern_3_4: 10310000 rects
+caravel_00020005_fill_pattern_3_4: 10320000 rects
+caravel_00020005_fill_pattern_3_4: 10330000 rects
+caravel_00020005_fill_pattern_3_4: 10340000 rects
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+caravel_00020005_fill_pattern_3_4: 10390000 rects
+caravel_00020005_fill_pattern_3_4: 10400000 rects
+caravel_00020005_fill_pattern_3_4: 10410000 rects
+caravel_00020005_fill_pattern_3_4: 10420000 rects
+caravel_00020005_fill_pattern_3_4: 10430000 rects
+caravel_00020005_fill_pattern_3_4: 10440000 rects
+caravel_00020005_fill_pattern_3_4: 10450000 rects
+caravel_00020005_fill_pattern_3_4: 10460000 rects
+caravel_00020005_fill_pattern_3_4: 10470000 rects
+caravel_00020005_fill_pattern_3_4: 10480000 rects
+caravel_00020005_fill_pattern_3_4: 10490000 rects
+caravel_00020005_fill_pattern_3_4: 10500000 rects
+caravel_00020005_fill_pattern_3_4: 10510000 rects
+caravel_00020005_fill_pattern_3_4: 10520000 rects
+caravel_00020005_fill_pattern_3_4: 10530000 rects
+caravel_00020005_fill_pattern_3_4: 10540000 rects
+caravel_00020005_fill_pattern_3_4: 10550000 rects
+caravel_00020005_fill_pattern_3_4: 10560000 rects
+caravel_00020005_fill_pattern_3_4: 10570000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_3_4
+
+caravel_00020005_fill_pattern_2_6: 9960000 rects
+caravel_00020005_fill_pattern_2_6: 9970000 rects
+caravel_00020005_fill_pattern_2_6: 9980000 rects
+caravel_00020005_fill_pattern_2_6: 9990000 rects
+caravel_00020005_fill_pattern_2_6: 10000000 rects
+caravel_00020005_fill_pattern_2_6: 10010000 rects
+caravel_00020005_fill_pattern_2_6: 10020000 rects
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+caravel_00020005_fill_pattern_2_6: 10060000 rects
+caravel_00020005_fill_pattern_2_6: 10070000 rects
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+caravel_00020005_fill_pattern_2_6: 10090000 rects
+caravel_00020005_fill_pattern_2_6: 10100000 rects
+caravel_00020005_fill_pattern_2_6: 10110000 rects
+caravel_00020005_fill_pattern_2_6: 10120000 rects
+caravel_00020005_fill_pattern_2_6: 10130000 rects
+caravel_00020005_fill_pattern_2_6: 10140000 rects
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+caravel_00020005_fill_pattern_2_6: 10220000 rects
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+caravel_00020005_fill_pattern_2_6: 10240000 rects
+caravel_00020005_fill_pattern_2_6: 10250000 rects
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+caravel_00020005_fill_pattern_2_6: 10270000 rects
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+caravel_00020005_fill_pattern_2_6: 10300000 rects
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+caravel_00020005_fill_pattern_2_6: 10320000 rects
+caravel_00020005_fill_pattern_2_6: 10330000 rects
+caravel_00020005_fill_pattern_2_6: 10340000 rects
+caravel_00020005_fill_pattern_2_6: 10350000 rects
+caravel_00020005_fill_pattern_2_6: 10360000 rects
+caravel_00020005_fill_pattern_2_6: 10370000 rects
+caravel_00020005_fill_pattern_2_6: 10380000 rects
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+caravel_00020005_fill_pattern_2_6: 10400000 rects
+caravel_00020005_fill_pattern_2_6: 10410000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_6
+
+caravel_00020005_fill_pattern_2_4: 11600000 rects
+caravel_00020005_fill_pattern_2_4: 11610000 rects
+caravel_00020005_fill_pattern_2_4: 11620000 rects
+caravel_00020005_fill_pattern_2_4: 11630000 rects
+caravel_00020005_fill_pattern_2_4: 11640000 rects
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+caravel_00020005_fill_pattern_2_4: 11740000 rects
+caravel_00020005_fill_pattern_2_4: 11750000 rects
+caravel_00020005_fill_pattern_2_4: 11760000 rects
+caravel_00020005_fill_pattern_2_4: 11770000 rects
+caravel_00020005_fill_pattern_2_4: 11780000 rects
+caravel_00020005_fill_pattern_2_4: 11790000 rects
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+caravel_00020005_fill_pattern_2_4: 11840000 rects
+caravel_00020005_fill_pattern_2_4: 11850000 rects
+caravel_00020005_fill_pattern_2_4: 11860000 rects
+caravel_00020005_fill_pattern_2_4: 11870000 rects
+caravel_00020005_fill_pattern_2_4: 11880000 rects
+caravel_00020005_fill_pattern_2_4: 11890000 rects
+caravel_00020005_fill_pattern_2_4: 11900000 rects
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+caravel_00020005_fill_pattern_2_4: 11930000 rects
+caravel_00020005_fill_pattern_2_4: 11940000 rects
+caravel_00020005_fill_pattern_2_4: 11950000 rects
+caravel_00020005_fill_pattern_2_4: 11960000 rects
+caravel_00020005_fill_pattern_2_4: 11970000 rects
+caravel_00020005_fill_pattern_2_4: 11980000 rects
+caravel_00020005_fill_pattern_2_4: 11990000 rects
+caravel_00020005_fill_pattern_2_4: 12000000 rects
+caravel_00020005_fill_pattern_2_4: 12010000 rects
+caravel_00020005_fill_pattern_2_4: 12020000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_4
+
+caravel_00020005_fill_pattern_2_3: 11600000 rects
+caravel_00020005_fill_pattern_2_3: 11610000 rects
+caravel_00020005_fill_pattern_2_3: 11620000 rects
+caravel_00020005_fill_pattern_2_3: 11630000 rects
+caravel_00020005_fill_pattern_2_3: 11640000 rects
+caravel_00020005_fill_pattern_2_3: 11650000 rects
+caravel_00020005_fill_pattern_2_3: 11660000 rects
+caravel_00020005_fill_pattern_2_3: 11670000 rects
+caravel_00020005_fill_pattern_2_3: 11680000 rects
+caravel_00020005_fill_pattern_2_3: 11690000 rects
+caravel_00020005_fill_pattern_2_3: 11700000 rects
+caravel_00020005_fill_pattern_2_3: 11710000 rects
+caravel_00020005_fill_pattern_2_3: 11720000 rects
+caravel_00020005_fill_pattern_2_3: 11730000 rects
+caravel_00020005_fill_pattern_2_3: 11740000 rects
+caravel_00020005_fill_pattern_2_3: 11750000 rects
+caravel_00020005_fill_pattern_2_3: 11760000 rects
+caravel_00020005_fill_pattern_2_3: 11770000 rects
+caravel_00020005_fill_pattern_2_3: 11780000 rects
+caravel_00020005_fill_pattern_2_3: 11790000 rects
+caravel_00020005_fill_pattern_2_3: 11800000 rects
+caravel_00020005_fill_pattern_2_3: 11810000 rects
+caravel_00020005_fill_pattern_2_3: 11820000 rects
+caravel_00020005_fill_pattern_2_3: 11830000 rects
+caravel_00020005_fill_pattern_2_3: 11840000 rects
+caravel_00020005_fill_pattern_2_3: 11850000 rects
+caravel_00020005_fill_pattern_2_3: 11860000 rects
+caravel_00020005_fill_pattern_2_3: 11870000 rects
+caravel_00020005_fill_pattern_2_3: 11880000 rects
+caravel_00020005_fill_pattern_2_3: 11890000 rects
+caravel_00020005_fill_pattern_2_3: 11900000 rects
+caravel_00020005_fill_pattern_2_3: 11910000 rects
+caravel_00020005_fill_pattern_2_3: 11920000 rects
+caravel_00020005_fill_pattern_2_3: 11930000 rects
+caravel_00020005_fill_pattern_2_3: 11940000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_3
+
+caravel_00020005_fill_pattern_1_6: 9960000 rects
+caravel_00020005_fill_pattern_1_6: 9970000 rects
+caravel_00020005_fill_pattern_1_6: 9980000 rects
+caravel_00020005_fill_pattern_1_6: 9990000 rects
+caravel_00020005_fill_pattern_1_6: 10000000 rects
+caravel_00020005_fill_pattern_1_6: 10010000 rects
+caravel_00020005_fill_pattern_1_6: 10020000 rects
+caravel_00020005_fill_pattern_1_6: 10030000 rects
+caravel_00020005_fill_pattern_1_6: 10040000 rects
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+caravel_00020005_fill_pattern_1_6: 10070000 rects
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+caravel_00020005_fill_pattern_1_6: 10090000 rects
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+caravel_00020005_fill_pattern_1_6: 10150000 rects
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+caravel_00020005_fill_pattern_1_6: 10190000 rects
+caravel_00020005_fill_pattern_1_6: 10200000 rects
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+caravel_00020005_fill_pattern_1_6: 10330000 rects
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+caravel_00020005_fill_pattern_1_6: 10350000 rects
+caravel_00020005_fill_pattern_1_6: 10360000 rects
+caravel_00020005_fill_pattern_1_6: 10370000 rects
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+caravel_00020005_fill_pattern_1_6: 10430000 rects
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+caravel_00020005_fill_pattern_1_6: 10450000 rects
+caravel_00020005_fill_pattern_1_6: 10460000 rects
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+caravel_00020005_fill_pattern_1_6: 10540000 rects
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+caravel_00020005_fill_pattern_1_6: 10560000 rects
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+caravel_00020005_fill_pattern_1_6: 11000000 rects
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+caravel_00020005_fill_pattern_1_6: 11100000 rects
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+caravel_00020005_fill_pattern_1_6: 11130000 rects
+caravel_00020005_fill_pattern_1_6: 11140000 rects
+caravel_00020005_fill_pattern_1_6: 11150000 rects
+caravel_00020005_fill_pattern_1_6: 11160000 rects
+caravel_00020005_fill_pattern_1_6: 11170000 rects
+caravel_00020005_fill_pattern_1_6: 11180000 rects
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+caravel_00020005_fill_pattern_1_6: 11210000 rects
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+caravel_00020005_fill_pattern_1_6: 11230000 rects
+caravel_00020005_fill_pattern_1_6: 11240000 rects
+caravel_00020005_fill_pattern_1_6: 11250000 rects
+caravel_00020005_fill_pattern_1_6: 11260000 rects
+caravel_00020005_fill_pattern_1_6: 11270000 rects
+caravel_00020005_fill_pattern_1_6: 11280000 rects
+caravel_00020005_fill_pattern_1_6: 11290000 rects
+caravel_00020005_fill_pattern_1_6: 11300000 rects
+caravel_00020005_fill_pattern_1_6: 11310000 rects
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+caravel_00020005_fill_pattern_1_6: 11340000 rects
+caravel_00020005_fill_pattern_1_6: 11350000 rects
+caravel_00020005_fill_pattern_1_6: 11360000 rects
+caravel_00020005_fill_pattern_1_6: 11370000 rects
+caravel_00020005_fill_pattern_1_6: 11380000 rects
+caravel_00020005_fill_pattern_1_6: 11390000 rects
+caravel_00020005_fill_pattern_1_6: 11400000 rects
+caravel_00020005_fill_pattern_1_6: 11410000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_6
+
+caravel_00020005_fill_pattern_2_5: 11600000 rects
+caravel_00020005_fill_pattern_2_5: 11610000 rects
+caravel_00020005_fill_pattern_2_5: 11620000 rects
+caravel_00020005_fill_pattern_2_5: 11630000 rects
+caravel_00020005_fill_pattern_2_5: 11640000 rects
+caravel_00020005_fill_pattern_2_5: 11650000 rects
+caravel_00020005_fill_pattern_2_5: 11660000 rects
+caravel_00020005_fill_pattern_2_5: 11670000 rects
+caravel_00020005_fill_pattern_2_5: 11680000 rects
+caravel_00020005_fill_pattern_2_5: 11690000 rects
+caravel_00020005_fill_pattern_2_5: 11700000 rects
+caravel_00020005_fill_pattern_2_5: 11710000 rects
+caravel_00020005_fill_pattern_2_5: 11720000 rects
+caravel_00020005_fill_pattern_2_5: 11730000 rects
+caravel_00020005_fill_pattern_2_5: 11740000 rects
+caravel_00020005_fill_pattern_2_5: 11750000 rects
+caravel_00020005_fill_pattern_2_5: 11760000 rects
+caravel_00020005_fill_pattern_2_5: 11770000 rects
+caravel_00020005_fill_pattern_2_5: 11780000 rects
+caravel_00020005_fill_pattern_2_5: 11790000 rects
+caravel_00020005_fill_pattern_2_5: 11800000 rects
+caravel_00020005_fill_pattern_2_5: 11810000 rects
+caravel_00020005_fill_pattern_2_5: 11820000 rects
+caravel_00020005_fill_pattern_2_5: 11830000 rects
+caravel_00020005_fill_pattern_2_5: 11840000 rects
+caravel_00020005_fill_pattern_2_5: 11850000 rects
+caravel_00020005_fill_pattern_2_5: 11860000 rects
+caravel_00020005_fill_pattern_2_5: 11870000 rects
+caravel_00020005_fill_pattern_2_5: 11880000 rects
+caravel_00020005_fill_pattern_2_5: 11890000 rects
+caravel_00020005_fill_pattern_2_5: 11900000 rects
+caravel_00020005_fill_pattern_2_5: 11910000 rects
+caravel_00020005_fill_pattern_2_5: 11920000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_2_5
+
+caravel_00020005_fill_pattern_1_2: 9960000 rects
+caravel_00020005_fill_pattern_1_2: 9970000 rects
+caravel_00020005_fill_pattern_1_2: 9980000 rects
+caravel_00020005_fill_pattern_1_2: 9990000 rects
+caravel_00020005_fill_pattern_1_2: 10000000 rects
+caravel_00020005_fill_pattern_1_2: 10010000 rects
+caravel_00020005_fill_pattern_1_2: 10020000 rects
+caravel_00020005_fill_pattern_1_2: 10030000 rects
+caravel_00020005_fill_pattern_1_2: 10040000 rects
+caravel_00020005_fill_pattern_1_2: 10050000 rects
+caravel_00020005_fill_pattern_1_2: 10060000 rects
+caravel_00020005_fill_pattern_1_2: 10070000 rects
+caravel_00020005_fill_pattern_1_2: 10080000 rects
+caravel_00020005_fill_pattern_1_2: 10090000 rects
+caravel_00020005_fill_pattern_1_2: 10100000 rects
+caravel_00020005_fill_pattern_1_2: 10110000 rects
+caravel_00020005_fill_pattern_1_2: 10120000 rects
+caravel_00020005_fill_pattern_1_2: 10130000 rects
+caravel_00020005_fill_pattern_1_2: 10140000 rects
+caravel_00020005_fill_pattern_1_2: 10150000 rects
+caravel_00020005_fill_pattern_1_2: 10160000 rects
+caravel_00020005_fill_pattern_1_2: 10170000 rects
+caravel_00020005_fill_pattern_1_2: 10180000 rects
+caravel_00020005_fill_pattern_1_2: 10190000 rects
+caravel_00020005_fill_pattern_1_2: 10200000 rects
+caravel_00020005_fill_pattern_1_2: 10210000 rects
+caravel_00020005_fill_pattern_1_2: 10220000 rects
+caravel_00020005_fill_pattern_1_2: 10230000 rects
+caravel_00020005_fill_pattern_1_2: 10240000 rects
+caravel_00020005_fill_pattern_1_2: 10250000 rects
+caravel_00020005_fill_pattern_1_2: 10260000 rects
+caravel_00020005_fill_pattern_1_2: 10270000 rects
+caravel_00020005_fill_pattern_1_2: 10280000 rects
+caravel_00020005_fill_pattern_1_2: 10290000 rects
+caravel_00020005_fill_pattern_1_2: 10300000 rects
+caravel_00020005_fill_pattern_1_2: 10310000 rects
+caravel_00020005_fill_pattern_1_2: 10320000 rects
+caravel_00020005_fill_pattern_1_2: 10330000 rects
+caravel_00020005_fill_pattern_1_2: 10340000 rects
+caravel_00020005_fill_pattern_1_2: 10350000 rects
+caravel_00020005_fill_pattern_1_2: 10360000 rects
+caravel_00020005_fill_pattern_1_2: 10370000 rects
+caravel_00020005_fill_pattern_1_2: 10380000 rects
+caravel_00020005_fill_pattern_1_2: 10390000 rects
+caravel_00020005_fill_pattern_1_2: 10400000 rects
+caravel_00020005_fill_pattern_1_2: 10410000 rects
+caravel_00020005_fill_pattern_1_2: 10420000 rects
+caravel_00020005_fill_pattern_1_2: 10430000 rects
+caravel_00020005_fill_pattern_1_2: 10440000 rects
+caravel_00020005_fill_pattern_1_2: 10450000 rects
+caravel_00020005_fill_pattern_1_2: 10460000 rects
+caravel_00020005_fill_pattern_1_2: 10470000 rects
+caravel_00020005_fill_pattern_1_2: 10480000 rects
+caravel_00020005_fill_pattern_1_2: 10490000 rects
+caravel_00020005_fill_pattern_1_2: 10500000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_2
+
+caravel_00020005_fill_pattern_1_0: 6600000 rects
+caravel_00020005_fill_pattern_1_0: 6610000 rects
+caravel_00020005_fill_pattern_1_0: 6620000 rects
+caravel_00020005_fill_pattern_1_0: 6630000 rects
+caravel_00020005_fill_pattern_1_0: 6640000 rects
+caravel_00020005_fill_pattern_1_0: 6650000 rects
+caravel_00020005_fill_pattern_1_0: 6660000 rects
+caravel_00020005_fill_pattern_1_0: 6670000 rects
+caravel_00020005_fill_pattern_1_0: 6680000 rects
+caravel_00020005_fill_pattern_1_0: 6690000 rects
+caravel_00020005_fill_pattern_1_0: 6700000 rects
+caravel_00020005_fill_pattern_1_0: 6710000 rects
+caravel_00020005_fill_pattern_1_0: 6720000 rects
+caravel_00020005_fill_pattern_1_0: 6730000 rects
+caravel_00020005_fill_pattern_1_0: 6740000 rects
+caravel_00020005_fill_pattern_1_0: 6750000 rects
+caravel_00020005_fill_pattern_1_0: 6760000 rects
+caravel_00020005_fill_pattern_1_0: 6770000 rects
+caravel_00020005_fill_pattern_1_0: 6780000 rects
+caravel_00020005_fill_pattern_1_0: 6790000 rects
+caravel_00020005_fill_pattern_1_0: 6800000 rects
+caravel_00020005_fill_pattern_1_0: 6810000 rects
+caravel_00020005_fill_pattern_1_0: 6820000 rects
+caravel_00020005_fill_pattern_1_0: 6830000 rects
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+caravel_00020005_fill_pattern_1_0: 6940000 rects
+caravel_00020005_fill_pattern_1_0: 6950000 rects
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+caravel_00020005_fill_pattern_1_0: 6970000 rects
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+caravel_00020005_fill_pattern_1_0: 7130000 rects
+caravel_00020005_fill_pattern_1_0: 7140000 rects
+caravel_00020005_fill_pattern_1_0: 7150000 rects
+caravel_00020005_fill_pattern_1_0: 7160000 rects
+caravel_00020005_fill_pattern_1_0: 7170000 rects
+caravel_00020005_fill_pattern_1_0: 7180000 rects
+caravel_00020005_fill_pattern_1_0: 7190000 rects
+caravel_00020005_fill_pattern_1_0: 7200000 rects
+caravel_00020005_fill_pattern_1_0: 7210000 rects
+caravel_00020005_fill_pattern_1_0: 7220000 rects
+caravel_00020005_fill_pattern_1_0: 7230000 rects
+caravel_00020005_fill_pattern_1_0: 7240000 rects
+caravel_00020005_fill_pattern_1_0: 7250000 rects
+caravel_00020005_fill_pattern_1_0: 7260000 rects
+caravel_00020005_fill_pattern_1_0: 7270000 rects
+caravel_00020005_fill_pattern_1_0: 7280000 rects
+caravel_00020005_fill_pattern_1_0: 7290000 rects
+caravel_00020005_fill_pattern_1_0: 7300000 rects
+caravel_00020005_fill_pattern_1_0: 7310000 rects
+caravel_00020005_fill_pattern_1_0: 7320000 rects
+caravel_00020005_fill_pattern_1_0: 7330000 rects
+caravel_00020005_fill_pattern_1_0: 7340000 rects
+caravel_00020005_fill_pattern_1_0: 7350000 rects
+caravel_00020005_fill_pattern_1_0: 7360000 rects
+caravel_00020005_fill_pattern_1_0: 7370000 rects
+caravel_00020005_fill_pattern_1_0: 7380000 rects
+caravel_00020005_fill_pattern_1_0: 7390000 rects
+caravel_00020005_fill_pattern_1_0: 7400000 rects
+caravel_00020005_fill_pattern_1_0: 7410000 rects
+caravel_00020005_fill_pattern_1_0: 7420000 rects
+caravel_00020005_fill_pattern_1_0: 7430000 rects
+caravel_00020005_fill_pattern_1_0: 7440000 rects
+caravel_00020005_fill_pattern_1_0: 7450000 rects
+caravel_00020005_fill_pattern_1_0: 7460000 rects
+caravel_00020005_fill_pattern_1_0: 7470000 rects
+caravel_00020005_fill_pattern_1_0: 7480000 rects
+caravel_00020005_fill_pattern_1_0: 7490000 rects
+caravel_00020005_fill_pattern_1_0: 7500000 rects
+caravel_00020005_fill_pattern_1_0: 7510000 rects
+caravel_00020005_fill_pattern_1_0: 7520000 rects
+caravel_00020005_fill_pattern_1_0: 7530000 rects
+caravel_00020005_fill_pattern_1_0: 7540000 rects
+caravel_00020005_fill_pattern_1_0: 7550000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_0
+
+caravel_00020005_fill_pattern_1_3: 11600000 rects
+caravel_00020005_fill_pattern_1_3: 11610000 rects
+caravel_00020005_fill_pattern_1_3: 11620000 rects
+caravel_00020005_fill_pattern_1_3: 11630000 rects
+caravel_00020005_fill_pattern_1_3: 11640000 rects
+caravel_00020005_fill_pattern_1_3: 11650000 rects
+caravel_00020005_fill_pattern_1_3: 11660000 rects
+caravel_00020005_fill_pattern_1_3: 11670000 rects
+caravel_00020005_fill_pattern_1_3: 11680000 rects
+caravel_00020005_fill_pattern_1_3: 11690000 rects
+caravel_00020005_fill_pattern_1_3: 11700000 rects
+caravel_00020005_fill_pattern_1_3: 11710000 rects
+caravel_00020005_fill_pattern_1_3: 11720000 rects
+caravel_00020005_fill_pattern_1_3: 11730000 rects
+caravel_00020005_fill_pattern_1_3: 11740000 rects
+caravel_00020005_fill_pattern_1_3: 11750000 rects
+caravel_00020005_fill_pattern_1_3: 11760000 rects
+caravel_00020005_fill_pattern_1_3: 11770000 rects
+caravel_00020005_fill_pattern_1_3: 11780000 rects
+caravel_00020005_fill_pattern_1_3: 11790000 rects
+caravel_00020005_fill_pattern_1_3: 11800000 rects
+caravel_00020005_fill_pattern_1_3: 11810000 rects
+caravel_00020005_fill_pattern_1_3: 11820000 rects
+caravel_00020005_fill_pattern_1_3: 11830000 rects
+caravel_00020005_fill_pattern_1_3: 11840000 rects
+caravel_00020005_fill_pattern_1_3: 11850000 rects
+caravel_00020005_fill_pattern_1_3: 11860000 rects
+caravel_00020005_fill_pattern_1_3: 11870000 rects
+caravel_00020005_fill_pattern_1_3: 11880000 rects
+caravel_00020005_fill_pattern_1_3: 11890000 rects
+caravel_00020005_fill_pattern_1_3: 11900000 rects
+caravel_00020005_fill_pattern_1_3: 11910000 rects
+caravel_00020005_fill_pattern_1_3: 11920000 rects
+caravel_00020005_fill_pattern_1_3: 11930000 rects
+caravel_00020005_fill_pattern_1_3: 11940000 rects
+caravel_00020005_fill_pattern_1_3: 11950000 rects
+caravel_00020005_fill_pattern_1_3: 11960000 rects
+caravel_00020005_fill_pattern_1_3: 11970000 rects
+caravel_00020005_fill_pattern_1_3: 11980000 rects
+caravel_00020005_fill_pattern_1_3: 11990000 rects
+caravel_00020005_fill_pattern_1_3: 12000000 rects
+caravel_00020005_fill_pattern_1_3: 12010000 rects
+caravel_00020005_fill_pattern_1_3: 12020000 rects
+caravel_00020005_fill_pattern_1_3: 12030000 rects
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+caravel_00020005_fill_pattern_1_3: 12050000 rects
+caravel_00020005_fill_pattern_1_3: 12060000 rects
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+caravel_00020005_fill_pattern_1_3: 12090000 rects
+caravel_00020005_fill_pattern_1_3: 12100000 rects
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+caravel_00020005_fill_pattern_1_3: 12170000 rects
+caravel_00020005_fill_pattern_1_3: 12180000 rects
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+caravel_00020005_fill_pattern_1_3: 12200000 rects
+caravel_00020005_fill_pattern_1_3: 12210000 rects
+caravel_00020005_fill_pattern_1_3: 12220000 rects
+caravel_00020005_fill_pattern_1_3: 12230000 rects
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+caravel_00020005_fill_pattern_1_3: 12250000 rects
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+caravel_00020005_fill_pattern_1_3: 12270000 rects
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+caravel_00020005_fill_pattern_1_3: 12310000 rects
+caravel_00020005_fill_pattern_1_3: 12320000 rects
+caravel_00020005_fill_pattern_1_3: 12330000 rects
+caravel_00020005_fill_pattern_1_3: 12340000 rects
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+caravel_00020005_fill_pattern_1_3: 12370000 rects
+caravel_00020005_fill_pattern_1_3: 12380000 rects
+caravel_00020005_fill_pattern_1_3: 12390000 rects
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+caravel_00020005_fill_pattern_1_3: 12470000 rects
+caravel_00020005_fill_pattern_1_3: 12480000 rects
+caravel_00020005_fill_pattern_1_3: 12490000 rects
+caravel_00020005_fill_pattern_1_3: 12500000 rects
+caravel_00020005_fill_pattern_1_3: 12510000 rects
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+caravel_00020005_fill_pattern_1_3: 12550000 rects
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+caravel_00020005_fill_pattern_1_3: 12770000 rects
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+caravel_00020005_fill_pattern_1_3: 12800000 rects
+caravel_00020005_fill_pattern_1_3: 12810000 rects
+caravel_00020005_fill_pattern_1_3: 12820000 rects
+caravel_00020005_fill_pattern_1_3: 12830000 rects
+caravel_00020005_fill_pattern_1_3: 12840000 rects
+caravel_00020005_fill_pattern_1_3: 12850000 rects
+caravel_00020005_fill_pattern_1_3: 12860000 rects
+caravel_00020005_fill_pattern_1_3: 12870000 rects
+caravel_00020005_fill_pattern_1_3: 12880000 rects
+caravel_00020005_fill_pattern_1_3: 12890000 rects
+caravel_00020005_fill_pattern_1_3: 12900000 rects
+caravel_00020005_fill_pattern_1_3: 12910000 rects
+caravel_00020005_fill_pattern_1_3: 12920000 rects
+caravel_00020005_fill_pattern_1_3: 12930000 rects
+caravel_00020005_fill_pattern_1_3: 12940000 rects
+caravel_00020005_fill_pattern_1_3: 12950000 rects
+caravel_00020005_fill_pattern_1_3: 12960000 rects
+caravel_00020005_fill_pattern_1_3: 12970000 rects
+caravel_00020005_fill_pattern_1_3: 12980000 rects
+caravel_00020005_fill_pattern_1_3: 12990000 rects
+caravel_00020005_fill_pattern_1_3: 13000000 rects
+caravel_00020005_fill_pattern_1_3: 13010000 rects
+caravel_00020005_fill_pattern_1_3: 13020000 rects
+caravel_00020005_fill_pattern_1_3: 13030000 rects
+caravel_00020005_fill_pattern_1_3: 13040000 rects
+caravel_00020005_fill_pattern_1_3: 13050000 rects
+caravel_00020005_fill_pattern_1_3: 13060000 rects
+caravel_00020005_fill_pattern_1_3: 13070000 rects
+caravel_00020005_fill_pattern_1_3: 13080000 rects
+caravel_00020005_fill_pattern_1_3: 13090000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_3
+
+caravel_00020005_fill_pattern_1_5: 11600000 rects
+caravel_00020005_fill_pattern_1_5: 11610000 rects
+caravel_00020005_fill_pattern_1_5: 11620000 rects
+caravel_00020005_fill_pattern_1_5: 11630000 rects
+caravel_00020005_fill_pattern_1_5: 11640000 rects
+caravel_00020005_fill_pattern_1_5: 11650000 rects
+caravel_00020005_fill_pattern_1_5: 11660000 rects
+caravel_00020005_fill_pattern_1_5: 11670000 rects
+caravel_00020005_fill_pattern_1_5: 11680000 rects
+caravel_00020005_fill_pattern_1_5: 11690000 rects
+caravel_00020005_fill_pattern_1_5: 11700000 rects
+caravel_00020005_fill_pattern_1_5: 11710000 rects
+caravel_00020005_fill_pattern_1_5: 11720000 rects
+caravel_00020005_fill_pattern_1_5: 11730000 rects
+caravel_00020005_fill_pattern_1_5: 11740000 rects
+caravel_00020005_fill_pattern_1_5: 11750000 rects
+caravel_00020005_fill_pattern_1_5: 11760000 rects
+caravel_00020005_fill_pattern_1_5: 11770000 rects
+caravel_00020005_fill_pattern_1_5: 11780000 rects
+caravel_00020005_fill_pattern_1_5: 11790000 rects
+caravel_00020005_fill_pattern_1_5: 11800000 rects
+caravel_00020005_fill_pattern_1_5: 11810000 rects
+caravel_00020005_fill_pattern_1_5: 11820000 rects
+caravel_00020005_fill_pattern_1_5: 11830000 rects
+caravel_00020005_fill_pattern_1_5: 11840000 rects
+caravel_00020005_fill_pattern_1_5: 11850000 rects
+caravel_00020005_fill_pattern_1_5: 11860000 rects
+caravel_00020005_fill_pattern_1_5: 11870000 rects
+caravel_00020005_fill_pattern_1_5: 11880000 rects
+caravel_00020005_fill_pattern_1_5: 11890000 rects
+caravel_00020005_fill_pattern_1_5: 11900000 rects
+caravel_00020005_fill_pattern_1_5: 11910000 rects
+caravel_00020005_fill_pattern_1_5: 11920000 rects
+caravel_00020005_fill_pattern_1_5: 11930000 rects
+caravel_00020005_fill_pattern_1_5: 11940000 rects
+caravel_00020005_fill_pattern_1_5: 11950000 rects
+caravel_00020005_fill_pattern_1_5: 11960000 rects
+caravel_00020005_fill_pattern_1_5: 11970000 rects
+caravel_00020005_fill_pattern_1_5: 11980000 rects
+caravel_00020005_fill_pattern_1_5: 11990000 rects
+caravel_00020005_fill_pattern_1_5: 12000000 rects
+caravel_00020005_fill_pattern_1_5: 12010000 rects
+caravel_00020005_fill_pattern_1_5: 12020000 rects
+caravel_00020005_fill_pattern_1_5: 12030000 rects
+caravel_00020005_fill_pattern_1_5: 12040000 rects
+caravel_00020005_fill_pattern_1_5: 12050000 rects
+caravel_00020005_fill_pattern_1_5: 12060000 rects
+caravel_00020005_fill_pattern_1_5: 12070000 rects
+caravel_00020005_fill_pattern_1_5: 12080000 rects
+caravel_00020005_fill_pattern_1_5: 12090000 rects
+caravel_00020005_fill_pattern_1_5: 12100000 rects
+caravel_00020005_fill_pattern_1_5: 12110000 rects
+caravel_00020005_fill_pattern_1_5: 12120000 rects
+caravel_00020005_fill_pattern_1_5: 12130000 rects
+caravel_00020005_fill_pattern_1_5: 12140000 rects
+caravel_00020005_fill_pattern_1_5: 12150000 rects
+caravel_00020005_fill_pattern_1_5: 12160000 rects
+caravel_00020005_fill_pattern_1_5: 12170000 rects
+caravel_00020005_fill_pattern_1_5: 12180000 rects
+caravel_00020005_fill_pattern_1_5: 12190000 rects
+caravel_00020005_fill_pattern_1_5: 12200000 rects
+caravel_00020005_fill_pattern_1_5: 12210000 rects
+caravel_00020005_fill_pattern_1_5: 12220000 rects
+caravel_00020005_fill_pattern_1_5: 12230000 rects
+caravel_00020005_fill_pattern_1_5: 12240000 rects
+caravel_00020005_fill_pattern_1_5: 12250000 rects
+caravel_00020005_fill_pattern_1_5: 12260000 rects
+caravel_00020005_fill_pattern_1_5: 12270000 rects
+caravel_00020005_fill_pattern_1_5: 12280000 rects
+caravel_00020005_fill_pattern_1_5: 12290000 rects
+caravel_00020005_fill_pattern_1_5: 12300000 rects
+caravel_00020005_fill_pattern_1_5: 12310000 rects
+caravel_00020005_fill_pattern_1_5: 12320000 rects
+caravel_00020005_fill_pattern_1_5: 12330000 rects
+caravel_00020005_fill_pattern_1_5: 12340000 rects
+caravel_00020005_fill_pattern_1_5: 12350000 rects
+caravel_00020005_fill_pattern_1_5: 12360000 rects
+caravel_00020005_fill_pattern_1_5: 12370000 rects
+caravel_00020005_fill_pattern_1_5: 12380000 rects
+caravel_00020005_fill_pattern_1_5: 12390000 rects
+caravel_00020005_fill_pattern_1_5: 12400000 rects
+caravel_00020005_fill_pattern_1_5: 12410000 rects
+caravel_00020005_fill_pattern_1_5: 12420000 rects
+caravel_00020005_fill_pattern_1_5: 12430000 rects
+caravel_00020005_fill_pattern_1_5: 12440000 rects
+caravel_00020005_fill_pattern_1_5: 12450000 rects
+caravel_00020005_fill_pattern_1_5: 12460000 rects
+caravel_00020005_fill_pattern_1_5: 12470000 rects
+caravel_00020005_fill_pattern_1_5: 12480000 rects
+caravel_00020005_fill_pattern_1_5: 12490000 rects
+caravel_00020005_fill_pattern_1_5: 12500000 rects
+caravel_00020005_fill_pattern_1_5: 12510000 rects
+caravel_00020005_fill_pattern_1_5: 12520000 rects
+caravel_00020005_fill_pattern_1_5: 12530000 rects
+caravel_00020005_fill_pattern_1_5: 12540000 rects
+caravel_00020005_fill_pattern_1_5: 12550000 rects
+caravel_00020005_fill_pattern_1_5: 12560000 rects
+caravel_00020005_fill_pattern_1_5: 12570000 rects
+caravel_00020005_fill_pattern_1_5: 12580000 rects
+caravel_00020005_fill_pattern_1_5: 12590000 rects
+caravel_00020005_fill_pattern_1_5: 12600000 rects
+caravel_00020005_fill_pattern_1_5: 12610000 rects
+caravel_00020005_fill_pattern_1_5: 12620000 rects
+caravel_00020005_fill_pattern_1_5: 12630000 rects
+caravel_00020005_fill_pattern_1_5: 12640000 rects
+caravel_00020005_fill_pattern_1_5: 12650000 rects
+caravel_00020005_fill_pattern_1_5: 12660000 rects
+caravel_00020005_fill_pattern_1_5: 12670000 rects
+caravel_00020005_fill_pattern_1_5: 12680000 rects
+caravel_00020005_fill_pattern_1_5: 12690000 rects
+caravel_00020005_fill_pattern_1_5: 12700000 rects
+caravel_00020005_fill_pattern_1_5: 12710000 rects
+caravel_00020005_fill_pattern_1_5: 12720000 rects
+caravel_00020005_fill_pattern_1_5: 12730000 rects
+caravel_00020005_fill_pattern_1_5: 12740000 rects
+caravel_00020005_fill_pattern_1_5: 12750000 rects
+caravel_00020005_fill_pattern_1_5: 12760000 rects
+caravel_00020005_fill_pattern_1_5: 12770000 rects
+caravel_00020005_fill_pattern_1_5: 12780000 rects
+caravel_00020005_fill_pattern_1_5: 12790000 rects
+caravel_00020005_fill_pattern_1_5: 12800000 rects
+caravel_00020005_fill_pattern_1_5: 12810000 rects
+caravel_00020005_fill_pattern_1_5: 12820000 rects
+caravel_00020005_fill_pattern_1_5: 12830000 rects
+caravel_00020005_fill_pattern_1_5: 12840000 rects
+caravel_00020005_fill_pattern_1_5: 12850000 rects
+caravel_00020005_fill_pattern_1_5: 12860000 rects
+caravel_00020005_fill_pattern_1_5: 12870000 rects
+caravel_00020005_fill_pattern_1_5: 12880000 rects
+caravel_00020005_fill_pattern_1_5: 12890000 rects
+caravel_00020005_fill_pattern_1_5: 12900000 rects
+caravel_00020005_fill_pattern_1_5: 12910000 rects
+caravel_00020005_fill_pattern_1_5: 12920000 rects
+caravel_00020005_fill_pattern_1_5: 12930000 rects
+caravel_00020005_fill_pattern_1_5: 12940000 rects
+caravel_00020005_fill_pattern_1_5: 12950000 rects
+caravel_00020005_fill_pattern_1_5: 12960000 rects
+caravel_00020005_fill_pattern_1_5: 12970000 rects
+caravel_00020005_fill_pattern_1_5: 12980000 rects
+caravel_00020005_fill_pattern_1_5: 12990000 rects
+caravel_00020005_fill_pattern_1_5: 13000000 rects
+caravel_00020005_fill_pattern_1_5: 13010000 rects
+caravel_00020005_fill_pattern_1_5: 13020000 rects
+caravel_00020005_fill_pattern_1_5: 13030000 rects
+caravel_00020005_fill_pattern_1_5: 13040000 rects
+caravel_00020005_fill_pattern_1_5: 13050000 rects
+caravel_00020005_fill_pattern_1_5: 13060000 rects
+caravel_00020005_fill_pattern_1_5: 13070000 rects
+caravel_00020005_fill_pattern_1_5: 13080000 rects
+caravel_00020005_fill_pattern_1_5: 13090000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020005_fill_pattern_1_5
+#python3 /mnt/shuttles/shuttle/mpw-two/caravel/scripts/generate_fill.py 00020005 caravel /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel -keep 2>&1 | tee ./signoff/build/generate_fill.out
+make[1]: Leaving directory `/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel'
+Generate fill completed.
+-------------------------------------------------------------------------------------------
+{{ STEP 3 }} fill generated for mpw-two, slot-005 : eFPGA_v3_caravel
+-------------------------------------------------------------------------------------------
+okfatal: ambiguous argument 'develop': unknown revision or path not in the working tree.
+Use '--' to separate paths from revisions, like this:
+'git <command> [<revision>...] -- [<file>...]'
+USER_ID is set to 00020005
+PROJECT is set to caravel
+All files are uncompressed!
+cd /mnt/shuttles/shuttle/mpw-two/caravel && \
+make uncompress
+make[1]: Entering directory `/mnt/shuttles/shuttle/mpw-two/caravel'
+All files are uncompressed!
+make[1]: Leaving directory `/mnt/shuttles/shuttle/mpw-two/caravel'
+make -f /mnt/shuttles/shuttle/mpw-two/caravel/Makefile __final
+make[1]: Entering directory `/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel'
+python3 /mnt/shuttles/shuttle/mpw-two/caravel/scripts/compositor.py 00020005 caravel /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel /mnt/shuttles/shuttle/mpw-two/caravel/mag /mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/gds -keep
+Building final GDS file caravel_00020005.gds
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel/mag/compose_final.tcl" from command line.
+caravel: 10000 rects
+caravel: 20000 rects
+caravel: 30000 rects
+caravel: 40000 rects
+caravel: 50000 rects
+caravel: 60000 rects
+Scaled magic input cell advSeal_6um_gen geometry by factor of 2
+Writing final GDS. . . 
+Scaled magic input cell seal_ring_corner_abstract geometry by factor of 2
+Scaled magic input cell caravel_motto geometry by factor of 2
+Scaled magic input cell font_22 geometry by factor of 24
+Scaled magic input cell font_73 geometry by factor of 24
+Scaled magic input cell font_43 geometry by factor of 24
+Scaled magic input cell font_49 geometry by factor of 24
+Scaled magic input cell font_65 geometry by factor of 24
+Scaled magic input cell font_68 geometry by factor of 24
+Scaled magic input cell font_54 geometry by factor of 24
+Scaled magic input cell font_67 geometry by factor of 24
+Scaled magic input cell font_6E geometry by factor of 24
+Scaled magic input cell font_69 geometry by factor of 24
+Scaled magic input cell font_6C geometry by factor of 24
+Scaled magic input cell font_61 geometry by factor of 24
+Scaled magic input cell font_53 geometry by factor of 24
+Scaled magic input cell open_source geometry by factor of 2
+Scaled magic input cell user_id_textblock geometry by factor of 2
+Scaled magic input cell alpha_0 geometry by factor of 2
+Scaled magic input cell font_62 geometry by factor of 24
+Scaled magic input cell font_66 geometry by factor of 24
+Scaled magic input cell font_29 geometry by factor of 24
+Scaled magic input cell font_20 geometry by factor of 24
+Scaled magic input cell font_28 geometry by factor of 24
+Scaled magic input cell font_33 geometry by factor of 24
+Scaled magic input cell font_56 geometry by factor of 24
+Scaled magic input cell font_76 geometry by factor of 24
+Scaled magic input cell font_72 geometry by factor of 24
+Scaled magic input cell font_2D geometry by factor of 24
+Scaled magic input cell font_4B geometry by factor of 24
+Scaled magic input cell font_44 geometry by factor of 24
+Scaled magic input cell font_50 geometry by factor of 24
+Scaled magic input cell font_70 geometry by factor of 24
+Scaled magic input cell font_6F geometry by factor of 24
+Scaled magic input cell font_74 geometry by factor of 24
+Scaled magic input cell font_57 geometry by factor of 24
+Scaled magic input cell font_6B geometry by factor of 24
+Scaled magic input cell font_79 geometry by factor of 24
+Scaled magic input cell font_47 geometry by factor of 24
+Scaled magic input cell font_31 geometry by factor of 24
+Scaled magic input cell font_32 geometry by factor of 24
+Scaled magic input cell font_30 geometry by factor of 24
+Scaled magic input cell font_6D geometry by factor of 24
+Scaled magic input cell font_4E geometry by factor of 24
+Processing timestamp mismatches: user_project_wrapper, caravel_power_routing, sky130_fd_io__top_xres4v2, sky130_ef_io__vssd_lvc_clamped_pad, sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um, sky130_ef_io__vccd_lvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped3_pad, sky130_ef_io__vdda_hvc_clamped_pad, sky130_ef_io__vddio_hvc_clamped_pad, sky130_ef_io__vccd_lvc_clamped3_pad, sky130_ef_io__vssio_hvc_clamped_pad, sky130_ef_io__disconnect_vdda_slice_5um, sky130_ef_io__vssa_hvc_clamped_pad, sky130_ef_io__gpiov2_pad_wrapped, sky130_ef_io__com_bus_slice_10um, sky130_ef_io__com_bus_slice_20um, sky130_ef_io__corner_pad, sky130_ef_io__com_bus_slice_1um, sky130_ef_io__com_bus_slice_5um, gpio_defaults_block_0403, sky130_fd_sc_hd__decap_4, sky130_fd_sc_hd__tapvpwrvgnd_1, sky130_fd_sc_hd__decap_3, sky130_fd_sc_hd__fill_1, sky130_fd_sc_hd__decap_12, sky130_fd_sc_hd__fill_2, sky130_fd_sc_hd__conb_1, sky130_fd_sc_hd__decap_6, spare_logic_block, gpio_defaults_block, mgmt_protect, gpio_defaults_block_1803, gpio_control_block, user_id_programming, digital_pll, housekeeping, caravel_clocking, xres_buf, open_source, caravel_logo, seal_ring_corner_abstract.
+   Generating output for cell advSeal_6um_gen
+Reading "sealring_slots".
+Reading "seal_ring_slots_array".
+Reading "sr_polygon00011".
+Reading "sr_polygon00039".
+Reading "sr_polygon00035".
+Reading "sr_polygon00015".
+Reading "sr_polygon00007".
+Reading "sr_polygon00001".
+Reading "sr_polygon00002".
+Reading "sr_polygon00003".
+Reading "sr_polygon00004".
+Reading "sr_polygon00005".
+Reading "sr_polygon00006".
+Reading "nikon_sealring_shape".
+Reading "sr_polygon00019".
+Reading "sr_polygon00023".
+Reading "sr_polygon00027".
+Reading "sr_polygon00031".
+Reading "sr_polygon00036".
+Reading "sr_polygon00032".
+Reading "sr_polygon00016".
+Reading "sr_polygon00020".
+Reading "sr_polygon00024".
+Reading "sr_polygon00028".
+Reading "seal_ring_corner".
+Reading "advSeal_6um_gen".
+   Generating output for cell caravel_00020005_fill_pattern
+Reading "caravel_00020005_fill_pattern_0_0".
+Reading "caravel_00020005_fill_pattern_1_0".
+Reading "caravel_00020005_fill_pattern_0_1".
+Reading "caravel_00020005_fill_pattern_1_1".
+Reading "caravel_00020005_fill_pattern_2_0".
+Reading "caravel_00020005_fill_pattern_2_1".
+Reading "caravel_00020005_fill_pattern_3_0".
+Reading "caravel_00020005_fill_pattern_3_1".
+Reading "caravel_00020005_fill_pattern_4_0".
+Reading "caravel_00020005_fill_pattern_4_1".
+Reading "caravel_00020005_fill_pattern_5_0".
+Reading "caravel_00020005_fill_pattern_5_1".
+Reading "caravel_00020005_fill_pattern_0_2".
+Reading "caravel_00020005_fill_pattern_1_2".
+Reading "caravel_00020005_fill_pattern_2_2".
+Reading "caravel_00020005_fill_pattern_3_2".
+Reading "caravel_00020005_fill_pattern_4_2".
+Reading "caravel_00020005_fill_pattern_5_2".
+Reading "caravel_00020005_fill_pattern_0_3".
+Reading "caravel_00020005_fill_pattern_1_3".
+Reading "caravel_00020005_fill_pattern_2_3".
+Reading "caravel_00020005_fill_pattern_3_3".
+Reading "caravel_00020005_fill_pattern_4_3".
+Reading "caravel_00020005_fill_pattern_5_3".
+Reading "caravel_00020005_fill_pattern_0_4".
+Reading "caravel_00020005_fill_pattern_2_4".
+Reading "caravel_00020005_fill_pattern_3_4".
+Reading "caravel_00020005_fill_pattern_4_4".
+Reading "caravel_00020005_fill_pattern_5_4".
+Reading "caravel_00020005_fill_pattern_0_5".
+Reading "caravel_00020005_fill_pattern_1_5".
+Reading "caravel_00020005_fill_pattern_2_5".
+Reading "caravel_00020005_fill_pattern_3_5".
+Reading "caravel_00020005_fill_pattern_4_5".
+Reading "caravel_00020005_fill_pattern_5_5".
+Reading "caravel_00020005_fill_pattern_0_6".
+Reading "caravel_00020005_fill_pattern_1_6".
+Reading "caravel_00020005_fill_pattern_2_6".
+Reading "caravel_00020005_fill_pattern_3_6".
+Reading "caravel_00020005_fill_pattern_4_6".
+Reading "caravel_00020005_fill_pattern_5_6".
+Reading "caravel_00020005_fill_pattern_0_7".
+Reading "caravel_00020005_fill_pattern_1_7".
+Reading "caravel_00020005_fill_pattern_2_7".
+Reading "caravel_00020005_fill_pattern_3_7".
+Reading "caravel_00020005_fill_pattern_4_7".
+Reading "caravel_00020005_fill_pattern_5_7".
+Reading "caravel_00020005_fill_pattern".
+   Generating output for cell caravel
+Reading "caravel_logo".
+Reading "open_source".
+Reading "sky130_fd_sc_hvl__decap_8".
+Reading "sky130_fd_sc_hvl__diode_2".
+Reading "sky130_fd_sc_hvl__decap_4".
+Reading "sky130_fd_sc_hvl__fill_2".
+Reading "sky130_fd_sc_hvl__fill_1".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "xres_buf".
+Reading "font_22".
+Reading "font_73".
+Reading "font_43".
+Reading "font_49".
+Reading "font_65".
+Reading "font_68".
+Reading "font_54".
+Reading "font_67".
+Reading "font_6E".
+Reading "font_69".
+Reading "font_6C".
+Reading "font_61".
+Reading "font_53".
+Reading "caravel_motto".
+Reading "alpha_2".
+Reading "alpha_5".
+Reading "alpha_0".
+Reading "user_id_textblock".
+Reading "font_62".
+Reading "font_66".
+Reading "font_29".
+Reading "font_20".
+Reading "font_28".
+Reading "font_33".
+Reading "font_56".
+Reading "font_76".
+Reading "font_72".
+Reading "font_2D".
+Reading "font_4B".
+Reading "font_44".
+Reading "font_50".
+Reading "font_70".
+Reading "font_6F".
+Reading "font_74".
+Reading "font_57".
+Reading "font_6B".
+Reading "font_79".
+Reading "font_47".
+Reading "font_31".
+Reading "font_32".
+Reading "font_30".
+Reading "font_6D".
+Reading "font_4E".
+Reading "copyright_block".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__dfrtn_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "caravel_clocking".
+Reading "sky130_fd_sc_hd__ebufn_8".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__nand4bb_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__clkinvlp_2".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__ebufn_2".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "housekeeping".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__einvn_4".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "digital_pll".
+Reading "sky130_fd_sc_hd__dfbbn_1".
+Reading "sky130_fd_sc_hd__ebufn_1".
+Reading "gpio_logic_high".
+Reading "gpio_control_block".
+Reading "gpio_defaults_block_1803".
+Reading "OE_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "OE_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "OE_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "OE_sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "OE_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "OE_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "OE_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "OE_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "OE_sky130_fd_sc_hvl__schmittbuf_1".
+Reading "OE_sky130_fd_sc_hvl__buf_8".
+Reading "OE_sky130_fd_sc_hvl__fill_4".
+Reading "OE_sky130_fd_sc_hvl__inv_8".
+Reading "OE_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "OE_sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "OE_sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "simple_por".
+Reading "CD_sky130_fd_sc_hd__decap_3".
+Reading "CD_sky130_fd_sc_hd__conb_1".
+Reading "CD_sky130_fd_sc_hd__fill_1".
+Reading "CD_sky130_fd_sc_hd__decap_8".
+Reading "CD_sky130_fd_sc_hd__fill_2".
+Reading "CD_sky130_fd_sc_hd__decap_6".
+Reading "CD_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "CD_sky130_fd_sc_hd__decap_4".
+Reading "CD_sky130_fd_sc_hd__decap_12".
+Reading "user_id_programming".
+Reading "LO_sky130_fd_sc_hd__decap_3".
+Reading "LO_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "LO_sky130_fd_sc_hd__decap_12".
+Reading "LO_sky130_fd_sc_hd__decap_6".
+Reading "LO_sky130_fd_sc_hd__ebufn_2".
+Reading "LO_sky130_fd_sc_hd__decap_4".
+Reading "LO_sky130_fd_sc_hd__diode_2".
+Reading "LO_sky130_fd_sc_hd__fill_1".
+Reading "LO_sky130_fd_sc_hd__fill_2".
+Reading "LO_sky130_fd_sc_hd__dfxtp_1".
+Reading "LO_sky130_fd_sc_hd__decap_8".
+Reading "LO_sky130_fd_sc_hd__mux2_1".
+Reading "LO_sky130_fd_sc_hd__mux4_1".
+Reading "LO_sky130_fd_sc_hd__inv_1".
+Reading "LO_sky130_fd_sc_hd__and2_1".
+Reading "LO_sky130_fd_sc_hd__dlclkp_1".
+Reading "LO_sky130_fd_sc_hd__conb_1".
+Reading "LO_sky130_fd_sc_hd__clkbuf_2".
+Reading "LO_sky130_fd_sc_hd__clkbuf_16".
+Reading "LO_sky130_fd_sc_hd__and3b_4".
+Reading "LO_sky130_fd_sc_hd__and2_2".
+Reading "LO_sky130_fd_sc_hd__nor3b_4".
+Reading "LO_sky130_fd_sc_hd__clkbuf_1".
+Reading "LO_sky130_fd_sc_hd__and4bb_2".
+Reading "LO_sky130_fd_sc_hd__nor4b_2".
+Reading "LO_sky130_fd_sc_hd__and3_4".
+Reading "LO_sky130_fd_sc_hd__and4b_2".
+Reading "LO_sky130_fd_sc_hd__and4_2".
+Reading "LO_sky130_fd_sc_hd__and2b_2".
+Reading "LO_sky130_fd_sc_hd__clkbuf_4".
+Reading "LO_DFFRAM".
+Reading "LO_sky130_fd_sc_hd__buf_2".
+Reading "LO_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "LO_sky130_fd_sc_hd__buf_8".
+Reading "LO_sky130_fd_sc_hd__buf_6".
+Reading "LO_sky130_fd_sc_hd__clkbuf_8".
+Reading "LO_sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "LO_sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "LO_sky130_fd_sc_hd__dfxtp_2".
+Reading "LO_sky130_fd_sc_hd__buf_4".
+Reading "LO_sky130_fd_sc_hd__a221o_1".
+Reading "LO_sky130_fd_sc_hd__a22o_1".
+Reading "LO_sky130_fd_sc_hd__dfxtp_4".
+Reading "LO_sky130_fd_sc_hd__nand3_4".
+Reading "LO_sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "LO_sky130_fd_sc_hd__a2111o_1".
+Reading "LO_sky130_fd_sc_hd__and4_1".
+Reading "LO_sky130_fd_sc_hd__a2111o_2".
+Reading "LO_sky130_fd_sc_hd__o211a_1".
+Reading "LO_sky130_fd_sc_hd__and3_1".
+Reading "LO_sky130_fd_sc_hd__inv_2".
+Reading "LO_sky130_fd_sc_hd__clkinv_2".
+Reading "LO_sky130_fd_sc_hd__a2111oi_1".
+Reading "LO_sky130_fd_sc_hd__buf_12".
+Reading "LO_sky130_fd_sc_hd__and2b_1".
+Reading "LO_sky130_fd_sc_hd__nand3b_1".
+Reading "LO_sky130_fd_sc_hd__a221o_2".
+Reading "LO_sky130_fd_sc_hd__nor3b_1".
+Reading "LO_sky130_fd_sc_hd__nor3_4".
+Reading "LO_sky130_fd_sc_hd__inv_6".
+Reading "LO_sky130_fd_sc_hd__and3b_1".
+Reading "LO_sky130_fd_sc_hd__nor3b_2".
+Reading "LO_sky130_fd_sc_hd__or2_1".
+Reading "LO_sky130_fd_sc_hd__a211oi_1".
+Reading "LO_sky130_fd_sc_hd__nand2_1".
+Reading "LO_sky130_fd_sc_hd__nand3b_4".
+Reading "LO_sky130_fd_sc_hd__inv_8".
+Reading "LO_sky130_fd_sc_hd__nand3_1".
+Reading "LO_sky130_fd_sc_hd__inv_12".
+Reading "LO_sky130_fd_sc_hd__o2111a_1".
+Reading "LO_sky130_fd_sc_hd__a21oi_1".
+Reading "LO_sky130_fd_sc_hd__o21ai_4".
+Reading "LO_sky130_fd_sc_hd__mux2_2".
+Reading "LO_sky130_fd_sc_hd__inv_4".
+Reading "LO_sky130_fd_sc_hd__a21bo_1".
+Reading "LO_sky130_fd_sc_hd__o21a_1".
+Reading "LO_sky130_fd_sc_hd__a211o_2".
+Reading "LO_sky130_fd_sc_hd__or2b_1".
+Reading "LO_sky130_fd_sc_hd__a21oi_4".
+Reading "LO_sky130_fd_sc_hd__o21ai_1".
+Reading "LO_sky130_fd_sc_hd__a21boi_1".
+Reading "LO_sky130_fd_sc_hd__nor3_1".
+Reading "LO_sky130_fd_sc_hd__nor2_2".
+Reading "LO_sky130_fd_sc_hd__a31oi_1".
+Reading "LO_sky130_fd_sc_hd__a21o_1".
+Reading "LO_sky130_fd_sc_hd__o21bai_1".
+Reading "LO_sky130_fd_sc_hd__o211ai_1".
+Reading "LO_sky130_fd_sc_hd__o31ai_1".
+Reading "LO_sky130_fd_sc_hd__nor2_1".
+Reading "LO_sky130_fd_sc_hd__xor2_4".
+Reading "LO_sky130_fd_sc_hd__nand3_2".
+Reading "LO_sky130_fd_sc_hd__o21ba_1".
+Reading "LO_sky130_fd_sc_hd__a41oi_1".
+Reading "LO_sky130_fd_sc_hd__nor3_2".
+Reading "LO_sky130_fd_sc_hd__o41ai_1".
+Reading "LO_sky130_fd_sc_hd__o21bai_2".
+Reading "LO_sky130_fd_sc_hd__xnor2_4".
+Reading "LO_sky130_fd_sc_hd__a41oi_4".
+Reading "LO_sky130_fd_sc_hd__xnor2_2".
+Reading "LO_sky130_fd_sc_hd__or3b_1".
+Reading "LO_sky130_fd_sc_hd__nand2_4".
+Reading "LO_sky130_fd_sc_hd__xnor2_1".
+Reading "LO_sky130_fd_sc_hd__nand2_8".
+Reading "LO_sky130_fd_sc_hd__xor2_1".
+Reading "LO_sky130_fd_sc_hd__nor2b_1".
+Reading "LO_sky130_fd_sc_hd__o21a_2".
+Reading "LO_sky130_fd_sc_hd__o211a_2".
+Reading "LO_sky130_fd_sc_hd__o31a_1".
+Reading "LO_sky130_fd_sc_hd__mux2_4".
+Reading "LO_sky130_fd_sc_hd__mux2_8".
+Reading "LO_sky130_fd_sc_hd__a211o_1".
+Reading "LO_sky130_fd_sc_hd__a311o_1".
+Reading "LO_sky130_fd_sc_hd__a22oi_4".
+Reading "LO_sky130_fd_sc_hd__o2111a_4".
+Reading "LO_sky130_fd_sc_hd__o22a_1".
+Reading "LO_sky130_fd_sc_hd__a31o_1".
+Reading "LO_sky130_fd_sc_hd__nor2b_2".
+Reading "LO_sky130_fd_sc_hd__a22oi_2".
+Reading "LO_sky130_fd_sc_hd__o21bai_4".
+Reading "LO_sky130_fd_sc_hd__o41a_2".
+Reading "LO_sky130_fd_sc_hd__nand2_2".
+Reading "LO_sky130_fd_sc_hd__nor2_8".
+Reading "LO_sky130_fd_sc_hd__a32oi_2".
+Reading "LO_sky130_fd_sc_hd__a221oi_4".
+Reading "LO_sky130_fd_sc_hd__nor2b_4".
+Reading "LO_sky130_fd_sc_hd__or4_1".
+Reading "LO_sky130_fd_sc_hd__a211oi_2".
+Reading "LO_sky130_fd_sc_hd__clkinv_4".
+Reading "LO_sky130_fd_sc_hd__a2bb2oi_1".
+Reading "LO_sky130_fd_sc_hd__a31oi_4".
+Reading "LO_sky130_fd_sc_hd__a21oi_2".
+Reading "LO_sky130_fd_sc_hd__o311ai_1".
+Reading "LO_sky130_fd_sc_hd__a41oi_2".
+Reading "LO_sky130_fd_sc_hd__or3b_4".
+Reading "LO_sky130_fd_sc_hd__clkinv_16".
+Reading "LO_sky130_fd_sc_hd__o211ai_4".
+Reading "LO_sky130_fd_sc_hd__nor2_4".
+Reading "LO_sky130_fd_sc_hd__o21ba_2".
+Reading "LO_sky130_fd_sc_hd__o2111ai_2".
+Reading "LO_sky130_fd_sc_hd__o2111ai_1".
+Reading "LO_sky130_fd_sc_hd__a32o_1".
+Reading "LO_sky130_fd_sc_hd__a311oi_1".
+Reading "LO_sky130_fd_sc_hd__xor2_2".
+Reading "LO_sky130_fd_sc_hd__a2111o_4".
+Reading "LO_sky130_fd_sc_hd__or4_4".
+Reading "LO_sky130_fd_sc_hd__o21ai_2".
+Reading "LO_sky130_fd_sc_hd__a211oi_4".
+Reading "LO_sky130_fd_sc_hd__o311ai_4".
+Reading "LO_sky130_fd_sc_hd__nand3b_2".
+Reading "LO_sky130_fd_sc_hd__a2111oi_4".
+Reading "LO_sky130_fd_sc_hd__or2b_4".
+Reading "LO_sky130_fd_sc_hd__o21a_4".
+Reading "LO_sky130_fd_sc_hd__and4b_4".
+Reading "LO_sky130_fd_sc_hd__o2111ai_4".
+Reading "LO_sky130_fd_sc_hd__or2_2".
+Reading "LO_sky130_fd_sc_hd__a21boi_2".
+Reading "LO_sky130_fd_sc_hd__mux4_2".
+Reading "LO_sky130_fd_sc_hd__a221oi_2".
+Reading "LO_sky130_fd_sc_hd__o22ai_1".
+Reading "LO_sky130_fd_sc_hd__o2bb2ai_1".
+Reading "LO_sky130_fd_sc_hd__and4_4".
+Reading "LO_sky130_fd_sc_hd__a32oi_1".
+Reading "LO_sky130_fd_sc_hd__clkinv_8".
+Reading "LO_sky130_fd_sc_hd__o32ai_1".
+Reading "LO_sky130_fd_sc_hd__a41o_1".
+Reading "LO_sky130_fd_sc_hd__or4_2".
+Reading "LO_sky130_fd_sc_hd__o221ai_1".
+Reading "LO_sky130_fd_sc_hd__o32a_1".
+Reading "LO_sky130_fd_sc_hd__a22o_2".
+Reading "LO_sky130_fd_sc_hd__o41a_1".
+Reading "LO_sky130_fd_sc_hd__a22oi_1".
+Reading "LO_sky130_fd_sc_hd__and3_2".
+Reading "LO_sky130_fd_sc_hd__o221a_2".
+Reading "LO_sky130_fd_sc_hd__o221a_1".
+Reading "LO_sky130_fd_sc_hd__and2_4".
+Reading "LO_sky130_fd_sc_hd__or3_1".
+Reading "LO_sky130_fd_sc_hd__o22ai_2".
+Reading "LO_sky130_fd_sc_hd__a221oi_1".
+Reading "LO_sky130_fd_sc_hd__a221o_4".
+Reading "LO_sky130_fd_sc_hd__o311ai_2".
+Reading "LO_sky130_fd_sc_hd__o31ai_2".
+Reading "LO_sky130_fd_sc_hd__a311oi_2".
+Reading "LO_sky130_fd_sc_hd__a31oi_2".
+Reading "LO_sky130_fd_sc_hd__o311a_2".
+Reading "LO_sky130_fd_sc_hd__o211ai_2".
+Reading "LO_sky130_fd_sc_hd__o41ai_4".
+Reading "LO_sky130_fd_sc_hd__o31a_4".
+Reading "LO_sky130_fd_sc_hd__a311oi_4".
+Reading "LO_sky130_fd_sc_hd__and2b_4".
+Reading "LO_sky130_fd_sc_hd__o2bb2ai_2".
+Reading "LO_sky130_fd_sc_hd__o2bb2ai_4".
+Reading "LO_sky130_fd_sc_hd__o22a_2".
+Reading "LO_sky130_fd_sc_hd__and4b_1".
+Reading "LO_sky130_fd_sc_hd__nand2b_1".
+Reading "LO_sky130_fd_sc_hd__a21boi_4".
+Reading "LO_sky130_fd_sc_hd__o2111a_2".
+Reading "LO_sky130_fd_sc_hd__o31ai_4".
+Reading "LO_sky130_fd_sc_hd__a2bb2oi_2".
+Reading "LO_sky130_fd_sc_hd__a2bb2oi_4".
+Reading "LO_sky130_fd_sc_hd__or3_4".
+Reading "LO_sky130_fd_sc_hd__a22o_4".
+Reading "LO_sky130_fd_sc_hd__a32oi_4".
+Reading "LO_sky130_fd_sc_hd__o311a_1".
+Reading "LO_sky130_fd_sc_hd__a21o_2".
+Reading "LO_sky130_fd_sc_hd__or4b_1".
+Reading "LO_sky130_fd_sc_hd__a2111oi_2".
+Reading "LO_sky130_fd_sc_hd__a21o_4".
+Reading "LO_sky130_fd_sc_hd__a32o_4".
+Reading "LO_sky130_fd_sc_hd__and3b_2".
+Reading "LO_sky130_fd_sc_hd__o32ai_4".
+Reading "LO_sky130_fd_sc_hd__o221ai_2".
+Reading "LO_sky130_fd_sc_hd__a31o_2".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "LO_sky130_fd_bd_sram__openram_dff".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "LO_sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "LO_sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "LO_sky130_fd_bd_sram__openram_sense_amp".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "LO_sky130_fd_bd_sram__openram_write_driver".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "LO_sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "LO_sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "LO_sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "LO_sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "LO_sky130_fd_bd_sram__openram_dp_cell".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "LO_sky130_sram_2kbyte_1rw1r_32x512_8".
+Reading "LO_sky130_fd_sc_hd__inv_16".
+Reading "LO_sky130_fd_sc_hd__o41ai_2".
+Reading "LO_sky130_fd_sc_hd__o211a_4".
+Reading "LO_mgmt_core".
+Reading "mgmt_core_wrapper".
+Reading "gpio_defaults_block_1800".
+Reading "sky130_fd_sc_hd__dfbbp_1".
+Reading "spare_logic_block".
+Reading "sky130_fd_sc_hd__einvp_4".
+Reading "sky130_fd_sc_hd__einvp_8".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hvl__conb_1".
+Reading "mgmt_protect_hv".
+Reading "mprj_logic_high".
+Reading "mprj2_logic_high".
+Reading "mgmt_protect".
+Reading "gpio_defaults_block_0403".
+Reading "gpio_defaults_block".
+Reading "gpio_control_power_routing_right".
+Reading "gpio_control_power_routing_top".
+Reading "gpio_control_power_routing".
+Reading "caravel_power_routing".
+Reading "sky130_fd_io__corner_bus_overlay".
+Reading "sky130_ef_io__corner_pad".
+Reading "sky130_ef_io__com_bus_slice_20um".
+Reading "sky130_ef_io__com_bus_slice_10um".
+Reading "sky130_ef_io__com_bus_slice_5um".
+Reading "sky130_ef_io__com_bus_slice_1um".
+Reading "sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um".
+Reading "sky130_ef_io__hvc_vdda_overlay".
+Reading "sky130_fd_io__com_bus_slice".
+Reading "sky130_fd_io__com_bus_hookup".
+Reading "sky130_fd_io__overlay_vssa_hvc".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180851".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808664".
+Reading "sky130_fd_io__sio_clamp_pcap_4x5".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808680".
+Reading "sky130_fd_io__esd_rcclamp_nfetcap".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808336".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808666".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808665".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808678".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808679".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808677".
+Reading "sky130_fd_pr__via_pol1__example_5595914180839".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808667".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808660".
+Reading "sky130_fd_pr__dfl1__example_55959141808663".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808671".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808672".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808673".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808668".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808670".
+Reading "sky130_fd_pr__dfl1__example_55959141808662".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808661".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808675".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808676".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808674".
+Reading "sky130_fd_pr__via_l1m1__example_559591418084".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808669".
+Reading "sky130_fd_pr__gendlring__example_559591418081".
+Reading "sky130_fd_pr__genrivetdlring__example_559591418082".
+Reading "sky130_fd_pr__padplhp__example_559591418080".
+Reading "sky130_fd_io__pad_esd".
+Reading "sky130_fd_io__com_busses_esd".
+Reading "sky130_fd_io__top_ground_hvc_wpad".
+Reading "sky130_ef_io__vssa_hvc_clamped_pad".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808717".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808716".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808719".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808718".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808720".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180890".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808721".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808243".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808722".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808723".
+Reading "sky130_fd_io__xres_inv_hysv2".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180838".
+Reading "sky130_fd_io__tk_tie_r_out_esd".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808765".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808764".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808767".
+Reading "sky130_fd_io__res250_sub_small".
+Reading "sky130_fd_io__res250only_small".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808289".
+Reading "sky130_fd_pr__via_pol1__example_5595914180833".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808715".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180862".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180863".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808288".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180859".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180864".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808264".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180858".
+Reading "sky130_fd_io__com_res_weak_v2".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180819".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808555".
+Reading "sky130_fd_pr__via_pol1__example_55959141808147".
+Reading "sky130_fd_pr__tpl1__example_55959141808148".
+Reading "sky130_fd_pr__tpl1__example_55959141808149".
+Reading "sky130_fd_pr__tpl1__example_55959141808150".
+Reading "sky130_fd_pr__tpl1__example_55959141808151".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808152".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808153".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808154".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808155".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808156".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808157".
+Reading "sky130_fd_pr__dfl1__example_55959141808158".
+Reading "sky130_fd_io__signal_5_sym_hv_local_5term".
+Reading "sky130_fd_pr__via_pol1__example_55959141808274".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808400".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808128".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808372".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808326".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808290".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808127".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180897".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808551".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808552".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808350".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808260".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808402".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808724".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808259".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808261".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808553".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808725".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808554".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808726".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808727".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808728".
+Reading "sky130_fd_io__gpio_buf_localesdv2".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180848".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180849".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808766".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808370".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808369".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808137".
+Reading "sky130_fd_pr__dfl1sd__example_559591418086".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808371".
+Reading "sky130_fd_pr__via_pol1__example_559591418083".
+Reading "sky130_fd_io__hvsbt_inv_x1".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808385".
+Reading "sky130_fd_pr__dfl1sd__example_559591418088".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808615".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808316".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808616".
+Reading "sky130_fd_pr__via_pol1__example_55959141808612".
+Reading "sky130_fd_io__hvsbt_inv_x4".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808422".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808421".
+Reading "sky130_fd_io__hvsbt_inv_x2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808657".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808659".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808658".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808202".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180811".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180812".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418084".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418086".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808653".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808652".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418081".
+Reading "sky130_fd_io__gpio_pudrvr_strong_axres4v2".
+Reading "sky130_fd_pr__via_m2m3__example_55959141808714".
+Reading "sky130_fd_io__xres_p_em1c_cdns_55959141808753".
+Reading "sky130_fd_pr__dfl1__example_55959141808187".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808754".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808755".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808700".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808559".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808762".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808338".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808337".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808763".
+Reading "sky130_fd_pr__dfl1__example_55959141808729".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808730".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808731".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808732".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808733".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808734".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808735".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808736".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808737".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808738".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808739".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808740".
+Reading "sky130_fd_pr__via_pol1__example_55959141808273".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808741".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808742".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808743".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808744".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808324".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808745".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808746".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808747".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808748".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808749".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808270".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808750".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808751".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808752".
+Reading "sky130_fd_io__xres2v2_rcfilter_lpfv2".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180860".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180861".
+Reading "sky130_fd_io__com_res_weak_bentbigres".
+Reading "sky130_fd_io__com_res_weak".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180857".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808646".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808645".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808647".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808649".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808648".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808650".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808651".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808378".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_xres4v2".
+Reading "sky130_fd_io__top_gpio_pad".
+Reading "sky130_fd_io__com_busses".
+Reading "sky130_fd_io__tap_1".
+Reading "sky130_fd_io__inv_1".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808768".
+Reading "sky130_fd_pr__res_bent_nd__example_55959141808769".
+Reading "sky130_fd_pr__pfet_01v8__example_559591418085".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418087".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418089".
+Reading "sky130_fd_io__hvsbt_nand2".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180827".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808770".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808233".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808771".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808237".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180829".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808772".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808773".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808242".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808774".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808775".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808776".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180835".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808777".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808778".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808779".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808780".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808782".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808781".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808452".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808783".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808449".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808784".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808785".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808786".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808787".
+Reading "sky130_fd_io__xres4v2_in_buf".
+Reading "sky130_fd_io__top_xres4v2".
+Reading "sky130_fd_io__com_bus_slice_m4".
+Reading "sky130_fd_io__overlay_gpiov2_m4".
+Reading "sky130_fd_io__overlay_gpiov2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808558".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808251".
+Reading "sky130_fd_pr__dfm1sd2__example_55959141808561".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808560".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808563".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808562".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808564".
+Reading "sky130_fd_io__amux_switch_1v2b".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180868".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180869".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808565".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180875".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808566".
+Reading "sky130_fd_io__gpiov2_amx_pucsd_inv".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808567".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808122".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808123".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808477".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808568".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180884".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808569".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808100".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180815".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808570".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808571".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808441".
+Reading "sky130_fd_io__gpiov2_amx_inv4".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180823".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808572".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808573".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808106".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808574".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808510".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808575".
+Reading "sky130_fd_io__amx_inv1".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808576".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808504".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808577".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808578".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808579".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808581".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808418".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808580".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808140".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808496".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808497".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808278".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808462".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808582".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808583".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808498".
+Reading "sky130_fd_io__gpiov2_amux_drvr_ls".
+Reading "sky130_fd_io__gpiov2_amux_drvr".
+Reading "sky130_fd_io__xor2_1".
+Reading "sky130_fd_io__nand2_1".
+Reading "sky130_fd_io__nor2_1".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808419".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808420".
+Reading "sky130_fd_io__hvsbt_nor".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180894".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808584".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808455".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808445".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808447".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808248".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808200".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808457".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808450".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808451".
+Reading "sky130_fd_io__gpiov2_amux_nand5".
+Reading "sky130_fd_pr__dfm1sd__example_55959141808258".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808585".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808446".
+Reading "sky130_fd_io__gpiov2_amux_nand4".
+Reading "sky130_fd_io__gpiov2_amux_decoder".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808586".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808587".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808476".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808588".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808475".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808115".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808589".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv2".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808460".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808590".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180816".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808463".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808464".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808465".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808466".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808467".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808468".
+Reading "sky130_fd_io__gpiov2_amux_ctl_ls".
+Reading "sky130_fd_io__gpiov2_amux_ctl_inv_1".
+Reading "sky130_fd_io__gpiov2_amux_ls".
+Reading "sky130_fd_io__gpiov2_amux_ctl_logic".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808178".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808591".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808488".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808592".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808306".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808593".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808594".
+Reading "sky130_fd_io__res75only_small".
+Reading "sky130_fd_io__gpiov2_amux".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808608".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808517".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808533".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808230".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808529".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808518".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808609".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808604".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808610".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180811".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808549".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808190".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808548".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808611".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808191".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808189".
+Reading "sky130_fd_io__gpiov2_in_buf".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808481".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808537".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808600".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808528".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808550".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808607".
+Reading "sky130_fd_io__gpiov2_ipath_hvls".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808601".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180825".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808602".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808603".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808527".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808535".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808540".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808598".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808605".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808596".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808606".
+Reading "sky130_fd_io__gpiov2_vcchib_in_buf".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180812".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808597".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808599".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808546".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808547".
+Reading "sky130_fd_io__gpiov2_ipath_lvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808595".
+Reading "sky130_fd_io__gpiov2_inbuf_lvinv_x1".
+Reading "sky130_fd_io__gpiov2_ibuf_se".
+Reading "sky130_fd_io__gpiov2_buf_localesd".
+Reading "sky130_fd_io__hvsbt_nand2v2".
+Reading "sky130_fd_io__gpiov2_ictl_logic".
+Reading "sky130_fd_io__gpiov2_ipath".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808613".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808614".
+Reading "sky130_fd_io__hvsbt_inv_x8v2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808423".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808280".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808425".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808424".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808426".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808379".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808380".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808382".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808383".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808427".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808428".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808429".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808430".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808102".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808431".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808432".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808434".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808433".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808435".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808440".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180878".
+Reading "sky130_fd_pr__via_pol1__example_55959141808394".
+Reading "sky130_fd_pr__via_pol1__example_55959141808298".
+Reading "sky130_fd_io__com_ctl_ls".
+Reading "sky130_fd_io__hvsbt_inv_x8".
+Reading "sky130_fd_io__com_ctl_hldv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808617".
+Reading "sky130_fd_io__com_ctl_ls_en_1_v2".
+Reading "sky130_fd_io__com_ctl_ls_v2".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808439".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808438".
+Reading "sky130_fd_io__com_ctl_ls_1v2".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180813".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180822".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808618".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808619".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808620".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808621".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808622".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808623".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808116".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808624".
+Reading "sky130_fd_io__com_ctl_lsv2".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180880".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180879".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180882".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180881".
+Reading "sky130_fd_io__gpiov2_ctl_lsbank".
+Reading "sky130_fd_io__gpiov2_ctl".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808375".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808376".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808377".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808381".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808384".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808386".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808387".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808388".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808389".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808390".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808391".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808392".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808393".
+Reading "sky130_fd_pr__via_pol1__example_55959141808373".
+Reading "sky130_fd_pr__via_pol1__example_55959141808272".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808271".
+Reading "sky130_fd_pr__tpl1__example_55959141808374".
+Reading "sky130_fd_io__gpio_dat_ls_1v2".
+Reading "sky130_fd_io__gpio_dat_lsv2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808360".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808403".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808362".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808404".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808405".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808406".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808194".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808346".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808407".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808408".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808409".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808410".
+Reading "sky130_fd_pr__via_pol1__example_55959141808294".
+Reading "sky130_fd_pr__via_pol1__example_55959141808322".
+Reading "sky130_fd_pr__via_pol1__example_55959141808395".
+Reading "sky130_fd_pr__via_pol1__example_55959141808396".
+Reading "sky130_fd_pr__via_pol1__example_55959141808397".
+Reading "sky130_fd_pr__via_pol1__example_55959141808295".
+Reading "sky130_fd_pr__via_pol1__example_55959141808398".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808399".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808325".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808292".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808269".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808401".
+Reading "sky130_fd_io__com_cclat".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808368".
+Reading "sky130_fd_pr__tpl1__example_55959141808625".
+Reading "sky130_fd_io__com_opath_datoev2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808416".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808417".
+Reading "sky130_fd_io__hvsbt_xor".
+Reading "sky130_fd_io__hvsbt_xorv2".
+Reading "sky130_fd_io__com_ctl_ls_octl".
+Reading "sky130_fd_io__gpiov2_octl".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808354".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808626".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808627".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808628".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808629".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808630".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808631".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr2".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808633".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808632".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808634".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808635".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808636".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808637".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808638".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr3".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808327".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808328".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808329".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808330".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808304".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808331".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808134".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808332".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808333".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808334".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808343".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808344".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808345".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808347".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808348".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808639".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808640".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808641".
+Reading "sky130_fd_pr__via_pol1__example_55959141808320".
+Reading "sky130_fd_pr__via_pol1__example_55959141808321".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808323".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808291".
+Reading "sky130_fd_io__com_pdpredrvr_pbiasv2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180888".
+Reading "sky130_fd_io__gpiov2_octl_mux".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808642".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808141".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808184".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808643".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808183".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808139".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808143".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808364".
+Reading "sky130_fd_io__com_pdpredrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808363".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808314".
+Reading "sky130_fd_pr__via_pol1__example_5595914180854".
+Reading "sky130_fd_io__com_pupredrvr_strong_slowv2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808644".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808281".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808282".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808287".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808283".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808284".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808285".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808286".
+Reading "sky130_fd_pr__via_pol1__example_55959141808275".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808276".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808301".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808302".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808303".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808305".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808307".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808308".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808309".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808310".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808311".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808312".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808313".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808315".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808317".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808318".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808319".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808293".
+Reading "sky130_fd_pr__via_pol1__example_55959141808296".
+Reading "sky130_fd_pr__via_pol1__example_55959141808297".
+Reading "sky130_fd_pr__tpl1__example_55959141808299".
+Reading "sky130_fd_pr__tpl1__example_55959141808300".
+Reading "sky130_fd_io__feascom_pupredrvr_nbiasv2".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808144".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_5595914180899".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808142".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808101".
+Reading "sky130_fd_io__gpio_pupredrvr_strongv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808365".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808366".
+Reading "sky130_fd_io__com_pdpredrvr_weakv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808361".
+Reading "sky130_fd_io__feas_com_pupredrvr_weak".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808266".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808267".
+Reading "sky130_fd_io__gpiov2_obpredrvr".
+Reading "sky130_fd_io__gpiov2_octl_dat".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418082".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418083".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpiov2_pddrvr_strong".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808655".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808654".
+Reading "sky130_fd_io__com_pudrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808656".
+Reading "sky130_fd_io__com_pudrvr_weakv2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180850".
+Reading "sky130_fd_io__gpio_pddrvr_weakv2".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418085".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpio_pudrvr_strongv2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_slowv2".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180852".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180853".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180855".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180856".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180832".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418080".
+Reading "sky130_fd_io__gpio_odrvr_subv2".
+Reading "sky130_fd_io__gpio_odrvrv2".
+Reading "sky130_fd_io__gpio_opathv2".
+Reading "sky130_fd_io__top_gpiov2".
+Reading "sky130_ef_io__gpiov2_pad".
+Reading "sky130_ef_io__gpiov2_pad_wrapped".
+Reading "sky130_ef_io__lvc_vccdx_overlay".
+Reading "sky130_fd_io__overlay_vssd_lvc".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808683".
+Reading "sky130_fd_io__gnd2gnd_strap".
+Reading "sky130_fd_io__gnd2gnd_tap".
+Reading "sky130_fd_io__gnd2gnd_diff".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808684".
+Reading "sky130_fd_pr__tpl1__example_55959141808685".
+Reading "sky130_fd_pr__tpl1__example_55959141808686".
+Reading "sky130_fd_io__gnd2gnd_sub_dnwl".
+Reading "sky130_fd_io__gnd2gnd_120x2_lv_isosub".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808687".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808691".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808690".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808702".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808705".
+Reading "sky130_fd_pr__dfl1__example_55959141808682".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808694".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808693".
+Reading "sky130_fd_pr__dfl1__example_55959141808681".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808688".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808696".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808697".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808698".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808699".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808695".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808704".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808703".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808701".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808692".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808689".
+Reading "sky130_fd_io__top_ground_lvc_wpad".
+Reading "sky130_ef_io__vssd_lvc_clamped_pad".
+Reading "sky130_ef_io__hvc_vssio_overlay".
+Reading "sky130_fd_io__overlay_vssio_hvc".
+Reading "sky130_ef_io__vssio_hvc_clamped_pad".
+Reading "sky130_fd_io__overlay_vdda_hvc".
+Reading "sky130_fd_io__hvc_clampv2".
+Reading "sky130_fd_io__top_power_hvc_wpadv2".
+Reading "sky130_ef_io__vdda_hvc_clamped_pad".
+Reading "sky130_fd_io__overlay_vccd_lvc".
+Reading "sky130_fd_io__top_power_lvc_wpad".
+Reading "sky130_ef_io__vccd_lvc_clamped_pad".
+Reading "sky130_ef_io__disconnect_vdda_slice_5um".
+Reading "sky130_ef_io__hvc_vddio_overlay".
+Reading "sky130_fd_io__overlay_vddio_hvc".
+Reading "sky130_ef_io__vddio_hvc_clamped_pad".
+Reading "sky130_ef_io__lvc_vccdy_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped3_pad".
+Reading "sky130_ef_io__vccd_lvc_clamped3_pad".
+Reading "chip_io".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_11$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_12$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_360_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w1_120_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_15$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_29$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_28$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m2_w0_740_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m2_w1_260_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_13$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_14$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_16$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w7_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w7_000_sli_dli_da_p$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_nand2_dec$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_dec$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_nand3_dec$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_740_sactive_dli$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_740_sli_dactive$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w1_120_sli_dli$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m22_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m22_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m7_w1_680_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m7_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m18_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m18_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m3_w1_680_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m3_w1_680_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_dec_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_20$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_and2_dec$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_17$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_and3_dec$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w2_880_sli_dli$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pnand2$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_23$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_22$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_21$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_19$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m1_w0_550_sli_dli$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_7$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_15$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m40_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m40_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_3$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m12_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m12_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m4_w1_260_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m4_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_16$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m1_w0_740_sactive_dactive$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m24_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m24_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m8_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m8_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m3_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m3_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m39_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m39_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m13_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m13_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m5_w1_680_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m5_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_nmos_m2_w1_260_sli_dli_da_p$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pmos_m2_w2_000_sli_dli_da_p$1".
+Reading "KP_sky130_fd_bd_sram__openram_dff$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_2$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_1$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_wordline_driver$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_hierarchical_predecode3x8$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_hierarchical_predecode2x4$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_column_mux_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_precharge_1$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_27$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_26$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_25$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_24$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_column_mux$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pand2$1".
+Reading "KP_sky130_fd_bd_sram__openram_write_driver$1".
+Reading "KP_sky130_fd_bd_sram__openram_sense_amp$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_precharge_0$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_cell_cap_row$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_cell_cap_col$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_cell_dummy$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_cell_replica$1".
+Reading "KP_sky130_fd_bd_sram__openram_dp_cell$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_3$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_10$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pnand2_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_dff_buf_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_18$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_17$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_19$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_4$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pnand3$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_14$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_13$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_12$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_11$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_20$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_9$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_8$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_7$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_6$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinv_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_and2_dec_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_wordline_driver_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_hierarchical_decoder$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_column_mux_array_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_precharge_array_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_column_mux_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_write_mask_and_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_write_driver_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_sense_amp_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_precharge_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_9$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_8$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_row_cap_array_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_row_cap_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_col_cap_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_col_cap_array_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_dummy_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_replica_column_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_replica_column$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_bitcell_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_dff_buf_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pand3$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_1$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_33$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pnand2_1$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pand2_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_dff_buf_array_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_5$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_delay_chain$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pand3_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_2$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pdriver_6$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_34$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_pinvbuf$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_port_address_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_port_address$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_port_data_0$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_port_data$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_replica_bitcell_array$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_wmask_dff$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_cr_3$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_row_addr_dff$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_control_logic_rw$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_col_addr_dff$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_cr_5$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_40$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_contact_39$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_control_logic_r$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_cr_4$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_data_dff$1".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8_bank$1".
+Reading "KP_sky130_fd_sc_hd__decap_6$1".
+Reading "KP_sky130_fd_sc_hd__fill_2$1".
+Reading "KP_sky130_fd_sc_hd__fill_4$1".
+Reading "KP_sky130_fd_sc_hd__decap_6$2".
+Reading "KP_sky130_fd_sc_hd__fill_4$2".
+Reading "KP_sky130_fd_sc_hd__fill_2$2".
+Reading "KP_sky130_fd_sc_hd__decap_6_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__nand2_2$1".
+Reading "KP_sky130_fd_sc_hd__o21ai_2$1".
+Reading "KP_sky130_fd_sc_hd__nor2b_2$1".
+Reading "KP_sky130_fd_sc_hd__or2_2$3".
+Reading "KP_sky130_fd_sc_hd__dlxtn_1$1".
+Reading "KP_sky130_fd_sc_hd__nor2_2$1".
+Reading "KP_sky130_fd_sc_hd__and2_2$1".
+Reading "KP_sky130_fd_sc_hd__mux4_1$2".
+Reading "KP_M1M2_PR_M$3".
+Reading "KP_sky130_fd_sc_hd__decap_3$3".
+Reading "KP_sky130_fd_sc_hd__decap_4$3".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2$3".
+Reading "KP_BlockRAM_1KB_VIA3$1".
+Reading "KP_BlockRAM_1KB_VIA2$1".
+Reading "KP_BlockRAM_1KB_VIA1$1".
+Reading "KP_BlockRAM_1KB_VIA0$1".
+Reading "KP_M3M4_PR$3".
+Reading "KP_sky130_fd_sc_hd__diode_2$3".
+Reading "KP_M2M3_PR$3".
+Reading "KP_sky130_fd_sc_hd__conb_1$2".
+Reading "KP_sky130_fd_sc_hd__decap_6$3".
+Reading "KP_M1M2_PR$3".
+Reading "KP_L1M1_PR$3".
+Reading "KP_sky130_fd_sc_hd__fill_1$3".
+Reading "KP_sky130_fd_sc_hd__fill_4$3".
+Reading "KP_sky130_fd_sc_hd__fill_8$1".
+Reading "KP_sky130_fd_sc_hd__fill_2$3".
+Reading "KP_sky130_fd_sc_hd__decap_8$3".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1$3".
+Reading "KP_sky130_sram_1kbyte_1rw1r_32x256_8$1".
+Reading "KP_sky130_fd_sc_hd__mux2_1$3".
+Reading "KP_sky130_fd_sc_hd__inv_2$3".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_N_term_RAM_IO_gds".
+Reading "KP_M3M4_PR_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1_N_term_RAM_IO_gds".
+Reading "KP_N_term_RAM_IO_VIA4".
+Reading "KP_N_term_RAM_IO_VIA5".
+Reading "KP_N_term_RAM_IO_VIA6".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_N_term_RAM_IO_gds".
+Reading "KP_M1M2_PR_M_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_RAM_IO_gds".
+Reading "KP_L1M1_PR_N_term_RAM_IO_gds".
+Reading "KP_M2M3_PR_N_term_RAM_IO_gds".
+Reading "KP_N_term_RAM_IO_VIA1".
+Reading "KP_N_term_RAM_IO_VIA2".
+Reading "KP_N_term_RAM_IO_VIA3".
+Reading "KP_N_term_RAM_IO_VIA0".
+Reading "KP_M1M2_PR_N_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_N_term_DSP_gds".
+Reading "KP_M1M2_PR_M_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__buf_2_N_term_DSP_gds".
+Reading "KP_N_term_DSP_VIA6".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_N_term_DSP_gds".
+Reading "KP_N_term_DSP_VIA4".
+Reading "KP_N_term_DSP_VIA5".
+Reading "KP_sky130_fd_sc_hd__fill_4_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_N_term_DSP_gds".
+Reading "KP_N_term_DSP_VIA0".
+Reading "KP_N_term_DSP_VIA1".
+Reading "KP_N_term_DSP_VIA2".
+Reading "KP_N_term_DSP_VIA3".
+Reading "KP_M2M3_PR_N_term_DSP_gds".
+Reading "KP_M1M2_PR_N_term_DSP_gds".
+Reading "KP_L1M1_PR_N_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_N_term_single2_gds".
+Reading "KP_M1M2_PR_M_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__buf_2_N_term_single2_gds".
+Reading "KP_N_term_single2_VIA6".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_N_term_single2_gds".
+Reading "KP_N_term_single2_VIA4".
+Reading "KP_N_term_single2_VIA5".
+Reading "KP_sky130_fd_sc_hd__fill_4_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_N_term_single2_gds".
+Reading "KP_N_term_single2_VIA0".
+Reading "KP_N_term_single2_VIA1".
+Reading "KP_N_term_single2_VIA2".
+Reading "KP_N_term_single2_VIA3".
+Reading "KP_M2M3_PR_N_term_single2_gds".
+Reading "KP_M1M2_PR_N_term_single2_gds".
+Reading "KP_L1M1_PR_N_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__buf_2_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_N_term_single_gds".
+Reading "KP_N_term_single_VIA4".
+Reading "KP_N_term_single_VIA5".
+Reading "KP_N_term_single_VIA6".
+Reading "KP_sky130_fd_sc_hd__decap_8_N_term_single_gds".
+Reading "KP_M1M2_PR_M_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_N_term_single_gds".
+Reading "KP_N_term_single_VIA1".
+Reading "KP_N_term_single_VIA2".
+Reading "KP_N_term_single_VIA3".
+Reading "KP_N_term_single_VIA0".
+Reading "KP_L1M1_PR_N_term_single_gds".
+Reading "KP_M1M2_PR_N_term_single_gds".
+Reading "KP_M2M3_PR_N_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s25_1$1".
+Reading "KP_sky130_fd_sc_hd__clkbuf_4$1".
+Reading "KP_M1M2_PR_R$1".
+Reading "KP_M2M3_PR_R$1".
+Reading "KP_sky130_ef_sc_hd__fill_12$1".
+Reading "KP_sky130_fd_sc_hd__clkinv_4$1".
+Reading "KP_RegFile_VIA6$1".
+Reading "KP_RegFile_VIA5$1".
+Reading "KP_RegFile_VIA4$1".
+Reading "KP_sky130_ef_sc_hd__fill_8$1".
+Reading "KP_sky130_fd_sc_hd__buf_2$1".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_1$1".
+Reading "KP_sky130_fd_sc_hd__buf_4$1".
+Reading "KP_sky130_ef_sc_hd__decap_12$1".
+Reading "KP_sky130_fd_sc_hd__decap_8$1".
+Reading "KP_sky130_fd_sc_hd__mux2_4$1".
+Reading "KP_sky130_fd_sc_hd__or3_1$1".
+Reading "KP_sky130_fd_sc_hd__mux4_4$1".
+Reading "KP_sky130_fd_sc_hd__mux2_1$1".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1$1".
+Reading "KP_sky130_fd_sc_hd__buf_12$1".
+Reading "KP_sky130_fd_sc_hd__mux4_1$1".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1$1".
+Reading "KP_M1M2_PR_MR$1".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1$1".
+Reading "KP_sky130_fd_sc_hd__clkinv_8$1".
+Reading "KP_sky130_fd_sc_hd__mux4_2$1".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1$1".
+Reading "KP_sky130_fd_sc_hd__or2_2$1".
+Reading "KP_sky130_fd_sc_hd__clkinv_16$1".
+Reading "KP_sky130_fd_sc_hd__buf_1$1".
+Reading "KP_sky130_fd_sc_hd__decap_3$1".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2$1".
+Reading "KP_sky130_fd_sc_hd__diode_2$1".
+Reading "KP_sky130_fd_sc_hd__inv_2$1".
+Reading "KP_M1M2_PR_M$1".
+Reading "KP_sky130_fd_sc_hd__buf_8$1".
+Reading "KP_sky130_fd_sc_hd__a22o_1$1".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1$1".
+Reading "KP_RegFile_VIA3$1".
+Reading "KP_sky130_fd_sc_hd__decap_4$1".
+Reading "KP_sky130_fd_sc_hd__fill_1$1".
+Reading "KP_RegFile_VIA0$1".
+Reading "KP_RegFile_VIA1$1".
+Reading "KP_M3M4_PR$1".
+Reading "KP_RegFile_VIA2$1".
+Reading "KP_M1M2_PR$1".
+Reading "KP_M2M3_PR$1".
+Reading "KP_L1M1_PR$1".
+Reading "KP_sky130_fd_sc_hd__buf_1_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__decap_6_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_S_term_single2_gds".
+Reading "KP_S_term_single2_VIA4".
+Reading "KP_S_term_single2_VIA5".
+Reading "KP_S_term_single2_VIA6".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_S_term_single2_gds".
+Reading "KP_L1M1_PR_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_S_term_single2_gds".
+Reading "KP_M1M2_PR_M_S_term_single2_gds".
+Reading "KP_S_term_single2_VIA2".
+Reading "KP_S_term_single2_VIA3".
+Reading "KP_M2M3_PR_S_term_single2_gds".
+Reading "KP_S_term_single2_VIA0".
+Reading "KP_S_term_single2_VIA1".
+Reading "KP_M1M2_PR_S_term_single2_gds".
+Reading "KP_sky130_fd_sc_hd__buf_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1_W_IO_gds".
+Reading "KP_M1M2_PR_MR_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__conb_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__inv_2_W_IO_gds".
+Reading "KP_W_IO_VIA6".
+Reading "KP_W_IO_VIA4".
+Reading "KP_W_IO_VIA5".
+Reading "KP_sky130_fd_sc_hd__buf_8_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__mux4_2_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__mux2_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_6_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__diode_2_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_4_W_IO_gds".
+Reading "KP_M1M2_PR_M_W_IO_gds".
+Reading "KP_M3M4_PR_W_IO_gds".
+Reading "KP_L1M1_PR_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_W_IO_gds".
+Reading "KP_M1M2_PR_W_IO_gds".
+Reading "KP_W_IO_VIA0".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_W_IO_gds".
+Reading "KP_M2M3_PR_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_3_W_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_W_IO_gds".
+Reading "KP_W_IO_VIA1".
+Reading "KP_W_IO_VIA2".
+Reading "KP_W_IO_VIA3".
+Reading "KP_sky130_fd_sc_hd__clkinv_8_RAM_IO_gds".
+Reading "KP_M2M3_PR_R".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_RAM_IO_gds".
+Reading "KP_RAM_IO_VIA4".
+Reading "KP_RAM_IO_VIA5".
+Reading "KP_RAM_IO_VIA6".
+Reading "KP_sky130_fd_sc_hd__dfxtp_1".
+Reading "KP_sky130_fd_sc_hd__buf_4_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s25_1_RAM_IO_gds".
+Reading "KP_M1M2_PR_R_RAM_IO_gds".
+Reading "KP_L1M1_PR_R_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__conb_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__mux4_2_RAM_IO_gds".
+Reading "KP_M1M2_PR_MR_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__buf_2_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_16_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__diode_2_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_4_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_3_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_4_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__buf_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_RAM_IO_gds".
+Reading "KP_M1M2_PR_M_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__mux2_1_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_RAM_IO_gds".
+Reading "KP_RAM_IO_VIA1".
+Reading "KP_L1M1_PR_RAM_IO_gds".
+Reading "KP_RAM_IO_VIA2".
+Reading "KP_M2M3_PR_RAM_IO_gds".
+Reading "KP_RAM_IO_VIA3".
+Reading "KP_sky130_fd_sc_hd__fill_1_RAM_IO_gds".
+Reading "KP_RAM_IO_VIA0".
+Reading "KP_M1M2_PR_RAM_IO_gds".
+Reading "KP_M3M4_PR_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_4_S_term_RAM_IO_gds".
+Reading "KP_M1M2_PR_M_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_S_term_RAM_IO_gds".
+Reading "KP_S_term_RAM_IO_VIA4".
+Reading "KP_S_term_RAM_IO_VIA5".
+Reading "KP_S_term_RAM_IO_VIA6".
+Reading "KP_sky130_fd_sc_hd__decap_6_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__diode_2_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_S_term_RAM_IO_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_S_term_RAM_IO_gds".
+Reading "KP_M2M3_PR_S_term_RAM_IO_gds".
+Reading "KP_L1M1_PR_S_term_RAM_IO_gds".
+Reading "KP_M1M2_PR_S_term_RAM_IO_gds".
+Reading "KP_S_term_RAM_IO_VIA0".
+Reading "KP_S_term_RAM_IO_VIA1".
+Reading "KP_S_term_RAM_IO_VIA2".
+Reading "KP_S_term_RAM_IO_VIA3".
+Reading "KP_sky130_fd_sc_hd__o31a_1$1".
+Reading "KP_sky130_fd_sc_hd__and2b_1$1".
+Reading "KP_sky130_fd_sc_hd__a2bb2oi_1$1".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1$2".
+Reading "KP_sky130_fd_sc_hd__clkbuf_4$2".
+Reading "KP_sky130_fd_sc_hd__xor2_1$1".
+Reading "KP_sky130_fd_sc_hd__o22ai_1$1".
+Reading "KP_sky130_fd_sc_hd__a31oi_1$1".
+Reading "KP_sky130_fd_sc_hd__a21oi_1$1".
+Reading "KP_sky130_fd_sc_hd__a22o_1$2".
+Reading "KP_sky130_fd_sc_hd__o221a_2$1".
+Reading "KP_sky130_fd_sc_hd__a22oi_1$1".
+Reading "KP_sky130_fd_sc_hd__mux2_2$1".
+Reading "KP_sky130_fd_sc_hd__o21ai_1$1".
+Reading "KP_sky130_fd_sc_hd__buf_12$2".
+Reading "KP_sky130_fd_sc_hd__a221o_1$1".
+Reading "KP_sky130_fd_sc_hd__o2bb2a_1$1".
+Reading "KP_sky130_fd_sc_hd__a32o_1$1".
+Reading "KP_sky130_fd_sc_hd__a31o_2$1".
+Reading "KP_sky130_fd_sc_hd__and4_1$1".
+Reading "KP_sky130_fd_sc_hd__or3_1$2".
+Reading "KP_sky130_fd_sc_hd__o32a_1$1".
+Reading "KP_DSP_VIA5$1".
+Reading "KP_DSP_VIA4$1".
+Reading "KP_DSP_VIA6$1".
+Reading "KP_sky130_fd_sc_hd__conb_1$1".
+Reading "KP_M1M2_PR_MR$2".
+Reading "KP_sky130_fd_sc_hd__o21a_1$1".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1$2".
+Reading "KP_sky130_fd_sc_hd__buf_2$2".
+Reading "KP_sky130_fd_sc_hd__decap_3$2".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_1$2".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s25_1$2".
+Reading "KP_sky130_fd_sc_hd__nand2_1$1".
+Reading "KP_sky130_fd_sc_hd__mux2_4$2".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2$2".
+Reading "KP_sky130_fd_sc_hd__a2bb2o_1$1".
+Reading "KP_sky130_fd_sc_hd__a21o_1$1".
+Reading "KP_sky130_fd_sc_hd__a21bo_2$1".
+Reading "KP_sky130_fd_sc_hd__and2_1$1".
+Reading "KP_sky130_fd_sc_hd__o21ba_2$1".
+Reading "KP_sky130_fd_sc_hd__o22a_1$1".
+Reading "KP_sky130_fd_sc_hd__or4_1$1".
+Reading "KP_sky130_fd_sc_hd__xnor2_1$1".
+Reading "KP_sky130_fd_sc_hd__or2b_1$1".
+Reading "KP_sky130_fd_sc_hd__nor2_1$1".
+Reading "KP_sky130_fd_sc_hd__or2_2$2".
+Reading "KP_sky130_fd_sc_hd__inv_2$2".
+Reading "KP_sky130_fd_sc_hd__mux2_1$2".
+Reading "KP_sky130_fd_sc_hd__buf_1$2".
+Reading "KP_L1M1_PR_R$1".
+Reading "KP_sky130_fd_sc_hd__clkinv_4$2".
+Reading "KP_sky130_fd_sc_hd__mux4_2$2".
+Reading "KP_M1M2_PR_R$2".
+Reading "KP_sky130_fd_sc_hd__decap_4$2".
+Reading "KP_sky130_fd_sc_hd__buf_8$2".
+Reading "KP_sky130_ef_sc_hd__fill_12$2".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1$2".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1$2".
+Reading "KP_M1M2_PR_M$2".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1$2".
+Reading "KP_sky130_ef_sc_hd__fill_8$2".
+Reading "KP_sky130_ef_sc_hd__decap_12$2".
+Reading "KP_sky130_fd_sc_hd__diode_2$2".
+Reading "KP_sky130_fd_sc_hd__decap_8$2".
+Reading "KP_M3M4_PR$2".
+Reading "KP_DSP_VIA0$1".
+Reading "KP_DSP_VIA2$1".
+Reading "KP_DSP_VIA3$1".
+Reading "KP_M2M3_PR$2".
+Reading "KP_M1M2_PR$2".
+Reading "KP_DSP_VIA1$1".
+Reading "KP_L1M1_PR$2".
+Reading "KP_sky130_fd_sc_hd__fill_1$2".
+Reading "KP_sky130_fd_sc_hd__buf_1_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__decap_6_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_S_term_DSP_gds".
+Reading "KP_S_term_DSP_VIA4".
+Reading "KP_S_term_DSP_VIA5".
+Reading "KP_S_term_DSP_VIA6".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_S_term_DSP_gds".
+Reading "KP_L1M1_PR_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_S_term_DSP_gds".
+Reading "KP_M1M2_PR_M_S_term_DSP_gds".
+Reading "KP_S_term_DSP_VIA2".
+Reading "KP_S_term_DSP_VIA3".
+Reading "KP_M2M3_PR_S_term_DSP_gds".
+Reading "KP_S_term_DSP_VIA0".
+Reading "KP_S_term_DSP_VIA1".
+Reading "KP_M1M2_PR_S_term_DSP_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_16_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_LUT4AB_gds".
+Reading "KP_L1M1_PR_R_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__buf_2_LUT4AB_gds".
+Reading "KP_LUT4AB_VIA4".
+Reading "KP_LUT4AB_VIA5".
+Reading "KP_LUT4AB_VIA6".
+Reading "KP_sky130_fd_sc_hd__clkinv_8_LUT4AB_gds".
+Reading "KP_M1M2_PR_R_LUT4AB_gds".
+Reading "KP_M1M2_PR_MR_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__decap_4_LUT4AB_gds".
+Reading "KP_sky130_ef_sc_hd__fill_12_LUT4AB_gds".
+Reading "KP_sky130_ef_sc_hd__decap_12_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__conb_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__mux2_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__mux2_4_LUT4AB_gds".
+Reading "KP_sky130_ef_sc_hd__fill_8_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__inv_2_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__nor2_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__mux4_2_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__decap_3_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__o22a_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__mux2_2_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_LUT4AB_gds".
+Reading "KP_M3M4_PR_LUT4AB_gds".
+Reading "KP_M1M2_PR_M_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_LUT4AB_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_LUT4AB_gds".
+Reading "KP_M2M3_PR_LUT4AB_gds".
+Reading "KP_M1M2_PR_LUT4AB_gds".
+Reading "KP_LUT4AB_VIA1".
+Reading "KP_LUT4AB_VIA2".
+Reading "KP_LUT4AB_VIA0".
+Reading "KP_sky130_fd_sc_hd__diode_2_LUT4AB_gds".
+Reading "KP_L1M1_PR_LUT4AB_gds".
+Reading "KP_LUT4AB_VIA3".
+Reading "KP_sky130_fd_sc_hd__conb_1_S_term_single_gds".
+Reading "KP_M1M2_PR_M_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__buf_1_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__decap_6_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__buf_8_S_term_single_gds".
+Reading "KP_S_term_single_VIA4".
+Reading "KP_S_term_single_VIA5".
+Reading "KP_S_term_single_VIA6".
+Reading "KP_S_term_single_VIA0".
+Reading "KP_sky130_fd_sc_hd__fill_4_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_2_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_1_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_8_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__clkinv_4_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__decap_8_S_term_single_gds".
+Reading "KP_M2M3_PR_S_term_single_gds".
+Reading "KP_M1M2_PR_S_term_single_gds".
+Reading "KP_S_term_single_VIA1".
+Reading "KP_S_term_single_VIA2".
+Reading "KP_S_term_single_VIA3".
+Reading "KP_L1M1_PR_S_term_single_gds".
+Reading "KP_sky130_fd_sc_hd__fill_4".
+Reading "KP_sky130_fd_sc_hd__fill_2".
+Reading "KP_sky130_fd_sc_hd__decap_6".
+Reading "KP_BlockRAM_1KB".
+Reading "KP_N_term_RAM_IO".
+Reading "KP_eFPGA_top_VIA7".
+Reading "KP_eFPGA_top_VIA23".
+Reading "KP_eFPGA_top_VIA24".
+Reading "KP_eFPGA_top_VIA25".
+Reading "KP_eFPGA_top_VIA6".
+Reading "KP_eFPGA_top_VIA8".
+Reading "KP_eFPGA_top_VIA19".
+Reading "KP_N_term_DSP".
+Reading "KP_eFPGA_top_VIA11".
+Reading "KP_N_term_single2".
+Reading "KP_N_term_single".
+Reading "KP_eFPGA_top_VIA22".
+Reading "KP_eFPGA_top_VIA36".
+Reading "KP_eFPGA_top_VIA20".
+Reading "KP_eFPGA_top_VIA21".
+Reading "KP_sky130_fd_sc_hd__inv_8".
+Reading "KP_sky130_fd_sc_hd__buf_16".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s25_2".
+Reading "KP_RegFile".
+Reading "KP_S_term_single2".
+Reading "KP_sky130_fd_sc_hd__a211o_2".
+Reading "KP_sky130_fd_sc_hd__a221oi_1".
+Reading "KP_sky130_fd_sc_hd__o21ba_2".
+Reading "KP_sky130_fd_sc_hd__or2_4".
+Reading "KP_sky130_fd_sc_hd__or2b_1".
+Reading "KP_sky130_fd_sc_hd__nand4_1".
+Reading "KP_sky130_fd_sc_hd__a32o_1".
+Reading "KP_sky130_fd_sc_hd__o21bai_1".
+Reading "KP_sky130_fd_sc_hd__a2bb2oi_1".
+Reading "KP_sky130_fd_sc_hd__a31oi_1".
+Reading "KP_sky130_fd_sc_hd__a2111o_1".
+Reading "KP_sky130_fd_sc_hd__and4_1".
+Reading "KP_sky130_fd_sc_hd__and3b_1".
+Reading "KP_sky130_fd_sc_hd__a2bb2oi_2".
+Reading "KP_sky130_fd_sc_hd__o22ai_1".
+Reading "KP_sky130_fd_sc_hd__dlxbp_1".
+Reading "KP_sky130_fd_sc_hd__nand2b_1".
+Reading "KP_sky130_fd_sc_hd__a21oi_1".
+Reading "KP_sky130_fd_sc_hd__and4b_1".
+Reading "KP_sky130_fd_sc_hd__and3_1".
+Reading "KP_sky130_fd_sc_hd__o2111a_1".
+Reading "KP_sky130_fd_sc_hd__or3b_2".
+Reading "KP_sky130_fd_sc_hd__a211oi_1".
+Reading "KP_sky130_fd_sc_hd__xnor2_1".
+Reading "KP_sky130_fd_sc_hd__o32a_1".
+Reading "KP_sky130_fd_sc_hd__a211o_1".
+Reading "KP_sky130_fd_sc_hd__o221ai_1".
+Reading "KP_sky130_fd_sc_hd__a31o_2".
+Reading "KP_sky130_fd_sc_hd__xor2_1".
+Reading "KP_sky130_fd_sc_hd__a221o_1".
+Reading "KP_sky130_fd_sc_hd__o211a_2".
+Reading "KP_sky130_fd_sc_hd__and2b_1".
+Reading "KP_sky130_fd_sc_hd__o311a_1".
+Reading "KP_sky130_fd_sc_hd__o31a_1".
+Reading "KP_sky130_fd_sc_hd__nor3_1".
+Reading "KP_sky130_fd_sc_hd__o211ai_1".
+Reading "KP_sky130_fd_sc_hd__and2_1".
+Reading "KP_sky130_fd_sc_hd__nand3b_1".
+Reading "KP_sky130_fd_sc_hd__or4b_2".
+Reading "KP_sky130_fd_sc_hd__nand2_1".
+Reading "KP_sky130_fd_sc_hd__o221a_2".
+Reading "KP_sky130_fd_sc_hd__mux2_2".
+Reading "KP_sky130_fd_sc_hd__nand4b_1".
+Reading "KP_sky130_fd_sc_hd__nand2_2".
+Reading "KP_sky130_fd_sc_hd__or4bb_1".
+Reading "KP_sky130_fd_sc_hd__a2bb2o_1".
+Reading "KP_sky130_fd_sc_hd__o22a_1".
+Reading "KP_sky130_fd_sc_hd__o21a_1".
+Reading "KP_L1M1_PR_R".
+Reading "KP_W_IO".
+Reading "KP_sky130_fd_sc_hd__o21ai_1".
+Reading "KP_sky130_fd_sc_hd__a21o_1".
+Reading "KP_sky130_fd_sc_hd__or4_1".
+Reading "KP_sky130_fd_sc_hd__or3_1".
+Reading "KP_eFPGA_top_VIA35".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s15_1".
+Reading "KP_sky130_fd_sc_hd__a21bo_2".
+Reading "KP_sky130_fd_sc_hd__or2_2".
+Reading "KP_M1M2_PR_R".
+Reading "KP_sky130_fd_sc_hd__mux2_4".
+Reading "KP_sky130_fd_sc_hd__a22o_1".
+Reading "KP_M1M2_PR_MR".
+Reading "KP_sky130_fd_sc_hd__or4_4".
+Reading "KP_sky130_fd_sc_hd__or4_2".
+Reading "KP_eFPGA_top_VIA29".
+Reading "KP_eFPGA_top_VIA30".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s18_2".
+Reading "KP_sky130_fd_sc_hd__or3_4".
+Reading "KP_sky130_fd_sc_hd__or3_2".
+Reading "KP_RAM_IO".
+Reading "KP_S_term_RAM_IO".
+Reading "KP_sky130_fd_sc_hd__buf_12".
+Reading "KP_M1M2_PR_M".
+Reading "KP_sky130_fd_sc_hd__mux2_1".
+Reading "KP_DSP".
+Reading "KP_S_term_DSP".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd2_1".
+Reading "KP_sky130_fd_sc_hd__inv_6".
+Reading "KP_eFPGA_top_VIA10".
+Reading "KP_sky130_fd_sc_hd__diode_2".
+Reading "KP_LUT4AB".
+Reading "KP_S_term_single".
+Reading "KP_sky130_fd_sc_hd__bufbuf_8".
+Reading "KP_sky130_fd_sc_hd__nor2_2".
+Reading "KP_sky130_fd_sc_hd__clkbuf_8".
+Reading "KP_sky130_fd_sc_hd__nor2_1".
+Reading "KP_sky130_fd_sc_hd__buf_4".
+Reading "KP_eFPGA_top_VIA9".
+Reading "KP_eFPGA_top_VIA34".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "KP_eFPGA_top_VIA37".
+Reading "KP_eFPGA_top_VIA38".
+Reading "KP_eFPGA_top_VIA39".
+Reading "KP_sky130_fd_sc_hd__inv_4".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s50_2".
+Reading "KP_sky130_fd_sc_hd__buf_2".
+Reading "KP_sky130_fd_sc_hd__clkbuf_4".
+Reading "KP_sky130_fd_sc_hd__bufbuf_16".
+Reading "KP_sky130_fd_sc_hd__clkbuf_1".
+Reading "KP_sky130_fd_sc_hd__clkbuf_2".
+Reading "KP_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "KP_sky130_fd_sc_hd__buf_6".
+Reading "KP_sky130_fd_sc_hd__mux2_8".
+Reading "KP_sky130_fd_sc_hd__inv_2".
+Reading "KP_sky130_fd_sc_hd__dfxtp_2".
+Reading "KP_sky130_fd_sc_hd__clkinv_4".
+Reading "KP_eFPGA_top_VIA18".
+Reading "KP_eFPGA_top_VIA4".
+Reading "KP_sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "KP_eFPGA_top_VIA32".
+Reading "KP_eFPGA_top_VIA31".
+Reading "KP_eFPGA_top_VIA5".
+Reading "KP_eFPGA_top_VIA15".
+Reading "KP_eFPGA_top_VIA33".
+Reading "KP_eFPGA_top_VIA16".
+Reading "KP_eFPGA_top_VIA17".
+Reading "KP_eFPGA_top_VIA14".
+Reading "KP_eFPGA_top_VIA1".
+Reading "KP_eFPGA_top_VIA3".
+Reading "KP_eFPGA_top_VIA12".
+Reading "KP_eFPGA_top_VIA2".
+Reading "KP_eFPGA_top_VIA13".
+Reading "KP_sky130_fd_sc_hd__conb_1".
+Reading "KP_sky130_fd_sc_hd__buf_1".
+Reading "KP_sky130_fd_sc_hd__buf_8".
+Reading "KP_sky130_fd_sc_hd__clkinv_8".
+Reading "KP_sky130_fd_sc_hd__clkinv_16".
+Reading "KP_sky130_fd_sc_hd__decap_8".
+Reading "KP_eFPGA_top_VIA0".
+Reading "KP_sky130_fd_sc_hd__fill_1".
+Reading "KP_M2M3_PR".
+Reading "KP_sky130_ef_sc_hd__decap_12".
+Reading "KP_M3M4_PR".
+Reading "KP_eFPGA_top_VIA27".
+Reading "KP_L1M1_PR".
+Reading "KP_eFPGA_top_VIA28".
+Reading "KP_sky130_ef_sc_hd__fill_12".
+Reading "KP_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "KP_M1M2_PR".
+Reading "KP_sky130_ef_sc_hd__fill_8".
+Reading "KP_eFPGA_top_VIA26".
+Reading "KP_eFPGA_top".
+Reading "user_project_wrapper".
+Reading "caravel".
+   Generating output for cell caravel_00020005
+Error message output from magic:
+Diagnostic:  caravel_00020005_fill_pattern_1_4 is a forward reference?
+Error:  Cell OE_caravel_00020005_fill_pattern_1_4 is not defined in the output file!
+Done!
+#mv /mnt/shuttles/shuttle/mpw-two/caravel/mag/caravel_00020005.mag ./mag/
+make[1]: Leaving directory `/mnt/shuttles/shuttle/mpw-two/slot-005/eFPGA_v3_caravel'
+Final build completed.
+converting gds file to oasis file
+[INFO] Changing from ./gds/caravel_00020005.gds to ./gds/caravel_00020005.oas
+Done
+-------------------------------------------------------------------------------------------
+{{ STEP 4 }} final gds generated for mpw-two, slot-005 : eFPGA_v3_caravel
+-------------------------------------------------------------------------------------------
+ok[main 00d83e3] final gds oasis
+ 2 files changed, 1 insertion(+)
+ create mode 100644 gds/caravel_00020005.oas
+ create mode 100644 signoff/make_final_oas
+To https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-two/slot-005.git
+   e3c5ff2..00d83e3  HEAD -> main
+-------------------------------------------------------------------------------------------
+{{ STEP 6 }} fom & met density checks mpw-two, slot-005 : eFPGA_v3_caravel
+-------------------------------------------------------------------------------------------
+{{ MET CHECK }} running met density check () for mpw-two, slot-005 : eFPGA_v3_caravel
+li1_ca_density is 0.498195197686893
+m1_ca_density is 0.5727492015579667
+m2_ca_density is 0.6262573537669555
+m3_ca_density is 0.5959006790415609
+m4_ca_density is 0.5327295391910261
+m5_ca_density is 0.5294507162849029
+ok{{ FOM CHECK }} running FOM check (70) for mpw-two, slot-005 : eFPGA_v3_caravel
+fom_density.drc:: sourcing design file=./gds/caravel_00020005.gds topcell=caravel_00020005 ...
+done.
+flattening chip boundary...
+done.
+step size = 70.0
+llx=5.965 lly=6.0 urx=3594.035 ury=5194.0
+x_cnt = 51
+y_cnt = 74
+dbu = 0.001
+bbox_area = 18614907.16
+calculating subtile areas (= 3774)...
+tiles per step = 10
+calculating window step densities (= 2730)...
+{{ CHECK }} 0/2730
+{{ CHECK }} 65/2730
+{{ CHECK }} 130/2730
+{{ CHECK }} 195/2730
+{{ CHECK }} 260/2730
+{{ CHECK }} 325/2730
+{{ CHECK }} 390/2730
+{{ CHECK }} 455/2730
+{{ CHECK }} 520/2730
+fom density below 0.33 : 561/2730 is 0.3298 for tile ((560,2870;1260,3570)), area = 490000
+{{ CHECK }} 585/2730
+fom density below 0.33 : 624/2730 is 0.3274 for tile ((630,2730;1330,3430)), area = 490000
+fom density below 0.33 : 625/2730 is 0.3263 for tile ((630,2800;1330,3500)), area = 490000
+fom density below 0.33 : 626/2730 is 0.3225 for tile ((630,2870;1330,3570)), area = 490000
+fom density below 0.33 : 627/2730 is 0.3234 for tile ((630,2940;1330,3640)), area = 490000
+fom density below 0.33 : 628/2730 is 0.3262 for tile ((630,3010;1330,3710)), area = 490000
+fom density below 0.33 : 629/2730 is 0.3291 for tile ((630,3080;1330,3780)), area = 490000
+fom density below 0.33 : 630/2730 is 0.3300 for tile ((630,3150;1330,3850)), area = 490000
+{{ CHECK }} 650/2730
+fom density below 0.33 : 689/2730 is 0.3255 for tile ((700,2730;1400,3430)), area = 490000
+fom density below 0.33 : 690/2730 is 0.3242 for tile ((700,2800;1400,3500)), area = 490000
+fom density below 0.33 : 691/2730 is 0.3205 for tile ((700,2870;1400,3570)), area = 490000
+fom density below 0.33 : 692/2730 is 0.3214 for tile ((700,2940;1400,3640)), area = 490000
+fom density below 0.33 : 693/2730 is 0.3246 for tile ((700,3010;1400,3710)), area = 490000
+fom density below 0.33 : 694/2730 is 0.3281 for tile ((700,3080;1400,3780)), area = 490000
+fom density below 0.33 : 695/2730 is 0.3289 for tile ((700,3150;1400,3850)), area = 490000
+{{ CHECK }} 715/2730
+fom density below 0.33 : 753/2730 is 0.3296 for tile ((770,2660;1470,3360)), area = 490000
+fom density below 0.33 : 754/2730 is 0.3243 for tile ((770,2730;1470,3430)), area = 490000
+fom density below 0.33 : 755/2730 is 0.3228 for tile ((770,2800;1470,3500)), area = 490000
+fom density below 0.33 : 756/2730 is 0.3194 for tile ((770,2870;1470,3570)), area = 490000
+fom density below 0.33 : 757/2730 is 0.3203 for tile ((770,2940;1470,3640)), area = 490000
+fom density below 0.33 : 758/2730 is 0.3231 for tile ((770,3010;1470,3710)), area = 490000
+fom density below 0.33 : 759/2730 is 0.3268 for tile ((770,3080;1470,3780)), area = 490000
+fom density below 0.33 : 760/2730 is 0.3275 for tile ((770,3150;1470,3850)), area = 490000
+{{ CHECK }} 780/2730
+fom density below 0.33 : 819/2730 is 0.3298 for tile ((840,2730;1540,3430)), area = 490000
+fom density below 0.33 : 820/2730 is 0.3290 for tile ((840,2800;1540,3500)), area = 490000
+fom density below 0.33 : 821/2730 is 0.3253 for tile ((840,2870;1540,3570)), area = 490000
+fom density below 0.33 : 822/2730 is 0.3258 for tile ((840,2940;1540,3640)), area = 490000
+fom density below 0.33 : 823/2730 is 0.3282 for tile ((840,3010;1540,3710)), area = 490000
+{{ CHECK }} 845/2730
+fom density below 0.33 : 886/2730 is 0.3271 for tile ((910,2870;1610,3570)), area = 490000
+fom density below 0.33 : 887/2730 is 0.3275 for tile ((910,2940;1610,3640)), area = 490000
+fom density below 0.33 : 888/2730 is 0.3293 for tile ((910,3010;1610,3710)), area = 490000
+{{ CHECK }} 910/2730
+fom density below 0.33 : 951/2730 is 0.3285 for tile ((980,2870;1680,3570)), area = 490000
+fom density below 0.33 : 952/2730 is 0.3289 for tile ((980,2940;1680,3640)), area = 490000
+{{ CHECK }} 975/2730
+{{ CHECK }} 1040/2730
+{{ CHECK }} 1105/2730
+{{ CHECK }} 1170/2730
+{{ CHECK }} 1235/2730
+{{ CHECK }} 1300/2730
+{{ CHECK }} 1365/2730
+{{ CHECK }} 1430/2730
+{{ CHECK }} 1495/2730
+{{ CHECK }} 1560/2730
+{{ CHECK }} 1625/2730
+{{ CHECK }} 1690/2730
+{{ CHECK }} 1755/2730
+{{ CHECK }} 1820/2730
+{{ CHECK }} 1885/2730
+{{ CHECK }} 1950/2730
+{{ CHECK }} 2015/2730
+{{ CHECK }} 2080/2730
+fom density below 0.33 : 2102/2730 is 0.3300 for tile ((2240,1540;2940,2240)), area = 490000
+fom density below 0.33 : 2103/2730 is 0.3289 for tile ((2240,1610;2940,2310)), area = 490000
+fom density below 0.33 : 2108/2730 is 0.3275 for tile ((2240,1960;2940,2660)), area = 490000
+fom density below 0.33 : 2109/2730 is 0.3279 for tile ((2240,2030;2940,2730)), area = 490000
+fom density below 0.33 : 2126/2730 is 0.3276 for tile ((2240,3220;2940,3920)), area = 490000
+fom density below 0.33 : 2127/2730 is 0.3277 for tile ((2240,3290;2940,3990)), area = 490000
+fom density below 0.33 : 2132/2730 is 0.3290 for tile ((2240,3640;2940,4340)), area = 490000
+fom density below 0.33 : 2133/2730 is 0.3293 for tile ((2240,3710;2940,4410)), area = 490000
+fom density below 0.33 : 2138/2730 is 0.3275 for tile ((2240,4060;2940,4760)), area = 490000
+fom density below 0.33 : 2139/2730 is 0.3296 for tile ((2240,4130;2940,4830)), area = 490000
+{{ CHECK }} 2145/2730
+fom density below 0.33 : 2167/2730 is 0.3273 for tile ((2310,1540;3010,2240)), area = 490000
+fom density below 0.33 : 2168/2730 is 0.3258 for tile ((2310,1610;3010,2310)), area = 490000
+fom density below 0.33 : 2173/2730 is 0.3254 for tile ((2310,1960;3010,2660)), area = 490000
+fom density below 0.33 : 2174/2730 is 0.3251 for tile ((2310,2030;3010,2730)), area = 490000
+fom density below 0.33 : 2179/2730 is 0.3280 for tile ((2310,2380;3010,3080)), area = 490000
+fom density below 0.33 : 2180/2730 is 0.3278 for tile ((2310,2450;3010,3150)), area = 490000
+fom density below 0.33 : 2185/2730 is 0.3285 for tile ((2310,2800;3010,3500)), area = 490000
+fom density below 0.33 : 2186/2730 is 0.3270 for tile ((2310,2870;3010,3570)), area = 490000
+fom density below 0.33 : 2191/2730 is 0.3253 for tile ((2310,3220;3010,3920)), area = 490000
+fom density below 0.33 : 2192/2730 is 0.3248 for tile ((2310,3290;3010,3990)), area = 490000
+fom density below 0.33 : 2197/2730 is 0.3265 for tile ((2310,3640;3010,4340)), area = 490000
+fom density below 0.33 : 2198/2730 is 0.3261 for tile ((2310,3710;3010,4410)), area = 490000
+fom density below 0.33 : 2203/2730 is 0.3256 for tile ((2310,4060;3010,4760)), area = 490000
+fom density below 0.33 : 2204/2730 is 0.3264 for tile ((2310,4130;3010,4830)), area = 490000
+{{ CHECK }} 2210/2730
+{{ CHECK }} 2275/2730
+{{ CHECK }} 2340/2730
+{{ CHECK }} 2405/2730
+{{ CHECK }} 2470/2730
+{{ CHECK }} 2535/2730
+{{ CHECK }} 2600/2730
+{{ CHECK }} 2665/2730
+minimum fom density  = 0.3194
+maximum fom density  = 0.4958
+cfom.pd.1d violations = 57
+finish received: success = true
+ok-------------------------------------------------------------------------------------------
+{{ STEP 7 }} compressing mpw-two, slot-005 : eFPGA_v3_caravel
+-------------------------------------------------------------------------------------------
+gds/caravel_00020005.gds -> gds/caravel_00020005.gds.gz
+gds/user_proj_example.gds -> gds/user_proj_example.gds.gz
+gds/caravel.gds -> gds/caravel.gds.gz
+gds/user_project_wrapper.gds -> gds/user_project_wrapper.gds.gz
+gds/eFPGA_top.gds -> gds/eFPGA_top.gds.gz
+gds/user_id_programming.gds -> gds/user_id_programming.gds.gz
+gds/user_id_prog_zero.gds -> gds/user_id_prog_zero.gds.gz
+gds/caravel_00020005_fill_pattern.gds -> gds/caravel_00020005_fill_pattern.gds.gz
+gds/caravel_00020005.gds.gz -> gds/caravel_00020005.gds.gz.00.split gds/caravel_00020005.gds.gz.01.split gds/caravel_00020005.gds.gz.02.split gds/caravel_00020005.gds.gz.03.split gds/caravel_00020005.gds.gz.04.split
+gds/caravel_00020005_fill_pattern.gds.gz -> gds/caravel_00020005_fill_pattern.gds.gz.00.split gds/caravel_00020005_fill_pattern.gds.gz.01.split gds/caravel_00020005_fill_pattern.gds.gz.02.split gds/caravel_00020005_fill_pattern.gds.gz.03.split
+Files larger than 100 MBytes are compressed!
+Nothing specified, nothing added.
+Maybe you wanted to say 'git add .'?
+fatal: pathspec 'checks/' did not match any files
+fatal: pathspec 'gds/.magicrc' did not match any files
+-------------------------------------------------------------------------------------------
+{{ STEP 8 }} pushing tapeout updates to shuttle-repo for mpw-two, slot-005 : eFPGA_v3_caravel
+-------------------------------------------------------------------------------------------
diff --git a/signoff/tapeout_completed b/signoff/tapeout_completed
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/signoff/tapeout_completed
diff --git a/signoff/versions b/signoff/versions
new file mode 100644
index 0000000..f801cf0
--- /dev/null
+++ b/signoff/versions
@@ -0,0 +1,21 @@
+------------------------------------
+make_ship: Thu Dec 9 16:05:13 UTC 2021
+make_ship: caravel = commit develop
+make_ship: magic = 8.3.234
+make_ship: sky130A tech = version 1.0.250-1-g89f6ff4
+make_ship: open_pdks = 1.0.251
+make_ship: klayout = KLayout 0.27.3
+------------------------------------
+generate_fill: Thu Dec 9 16:06:00 UTC 2021
+generate_fill: caravel = commit develop
+generate_fill: magic = 8.3.234
+generate_fill: sky130A tech = version 1.0.250-1-g89f6ff4
+generate_fill: open_pdks = 1.0.251
+generate_fill: klayout = KLayout 0.27.3
+------------------------------------
+make_final: Thu Dec 9 16:57:05 UTC 2021
+make_final: caravel = commit develop
+make_final: magic = 8.3.234
+make_final: sky130A tech = version 1.0.250-1-g89f6ff4
+make_final: open_pdks = 1.0.251
+make_final: klayout = KLayout 0.27.3
diff --git a/verilog/gl/caravan.v b/verilog/gl/caravan.v
new file mode 100644
index 0000000..bd4d4df
--- /dev/null
+++ b/verilog/gl/caravan.v
@@ -0,0 +1,4306 @@
+/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
+
+module caravan(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vdda1_2, vdda2, vssa1, vssa1_2, vssa2, vccd1, vccd2, vssd1, vssd2, gpio, mprj_io, clock, resetb, flash_csb, flash_clk, flash_io0, flash_io1);
+  wire caravel_clk;
+  wire caravel_clk2;
+  wire caravel_rstn;
+  input clock;
+  wire clock_core;
+  wire debug_in;
+  wire debug_mode;
+  wire debug_oeb;
+  wire debug_out;
+  wire ext_clk_sel;
+  wire ext_reset;
+  output flash_clk;
+  wire flash_clk_core;
+  wire flash_clk_frame;
+  wire flash_clk_ieb;
+  wire flash_clk_ieb_core;
+  wire flash_clk_oeb;
+  wire flash_clk_oeb_core;
+  output flash_csb;
+  wire flash_csb_core;
+  wire flash_csb_frame;
+  wire flash_csb_ieb;
+  wire flash_csb_ieb_core;
+  wire flash_csb_oeb;
+  wire flash_csb_oeb_core;
+  output flash_io0;
+  wire flash_io0_di;
+  wire flash_io0_di_core;
+  wire flash_io0_do;
+  wire flash_io0_do_core;
+  wire flash_io0_ieb;
+  wire flash_io0_ieb_core;
+  wire flash_io0_oeb;
+  wire flash_io0_oeb_core;
+  output flash_io1;
+  wire flash_io1_di;
+  wire flash_io1_di_core;
+  wire flash_io1_do;
+  wire flash_io1_do_core;
+  wire flash_io1_ieb;
+  wire flash_io1_ieb_core;
+  wire flash_io1_oeb;
+  wire flash_io1_oeb_core;
+  wire flash_io2_di_core;
+  wire flash_io2_do_core;
+  wire flash_io2_ieb_core;
+  wire flash_io2_oeb_core;
+  wire flash_io3_di_core;
+  wire flash_io3_do_core;
+  wire flash_io3_ieb_core;
+  wire flash_io3_oeb_core;
+  inout gpio;
+  wire \gpio_clock_1[0] ;
+  wire \gpio_clock_1[10] ;
+  wire \gpio_clock_1[11] ;
+  wire \gpio_clock_1[12] ;
+  wire \gpio_clock_1[13] ;
+  wire \gpio_clock_1[14] ;
+  wire \gpio_clock_1[15] ;
+  wire \gpio_clock_1[16] ;
+  wire \gpio_clock_1[17] ;
+  wire \gpio_clock_1[18] ;
+  wire \gpio_clock_1[1] ;
+  wire \gpio_clock_1[2] ;
+  wire \gpio_clock_1[3] ;
+  wire \gpio_clock_1[4] ;
+  wire \gpio_clock_1[5] ;
+  wire \gpio_clock_1[6] ;
+  wire \gpio_clock_1[7] ;
+  wire \gpio_clock_1[8] ;
+  wire \gpio_clock_1[9] ;
+  wire \gpio_clock_1_shifted[0] ;
+  wire \gpio_clock_1_shifted[10] ;
+  wire \gpio_clock_1_shifted[11] ;
+  wire \gpio_clock_1_shifted[12] ;
+  wire \gpio_clock_1_shifted[13] ;
+  wire \gpio_clock_1_shifted[1] ;
+  wire \gpio_clock_1_shifted[2] ;
+  wire \gpio_clock_1_shifted[3] ;
+  wire \gpio_clock_1_shifted[4] ;
+  wire \gpio_clock_1_shifted[5] ;
+  wire \gpio_clock_1_shifted[6] ;
+  wire \gpio_clock_1_shifted[7] ;
+  wire \gpio_clock_1_shifted[8] ;
+  wire \gpio_clock_1_shifted[9] ;
+  wire \gpio_clock_2[0] ;
+  wire \gpio_clock_2[10] ;
+  wire \gpio_clock_2[11] ;
+  wire \gpio_clock_2[12] ;
+  wire \gpio_clock_2[13] ;
+  wire \gpio_clock_2[14] ;
+  wire \gpio_clock_2[15] ;
+  wire \gpio_clock_2[16] ;
+  wire \gpio_clock_2[17] ;
+  wire \gpio_clock_2[18] ;
+  wire \gpio_clock_2[1] ;
+  wire \gpio_clock_2[2] ;
+  wire \gpio_clock_2[3] ;
+  wire \gpio_clock_2[4] ;
+  wire \gpio_clock_2[5] ;
+  wire \gpio_clock_2[6] ;
+  wire \gpio_clock_2[7] ;
+  wire \gpio_clock_2[8] ;
+  wire \gpio_clock_2[9] ;
+  wire \gpio_clock_2_shifted[0] ;
+  wire \gpio_clock_2_shifted[10] ;
+  wire \gpio_clock_2_shifted[11] ;
+  wire \gpio_clock_2_shifted[12] ;
+  wire \gpio_clock_2_shifted[1] ;
+  wire \gpio_clock_2_shifted[2] ;
+  wire \gpio_clock_2_shifted[3] ;
+  wire \gpio_clock_2_shifted[4] ;
+  wire \gpio_clock_2_shifted[5] ;
+  wire \gpio_clock_2_shifted[6] ;
+  wire \gpio_clock_2_shifted[7] ;
+  wire \gpio_clock_2_shifted[8] ;
+  wire \gpio_clock_2_shifted[9] ;
+  wire \gpio_defaults[0] ;
+  wire \gpio_defaults[100] ;
+  wire \gpio_defaults[101] ;
+  wire \gpio_defaults[102] ;
+  wire \gpio_defaults[103] ;
+  wire \gpio_defaults[104] ;
+  wire \gpio_defaults[105] ;
+  wire \gpio_defaults[106] ;
+  wire \gpio_defaults[107] ;
+  wire \gpio_defaults[108] ;
+  wire \gpio_defaults[109] ;
+  wire \gpio_defaults[10] ;
+  wire \gpio_defaults[110] ;
+  wire \gpio_defaults[111] ;
+  wire \gpio_defaults[112] ;
+  wire \gpio_defaults[113] ;
+  wire \gpio_defaults[114] ;
+  wire \gpio_defaults[115] ;
+  wire \gpio_defaults[116] ;
+  wire \gpio_defaults[117] ;
+  wire \gpio_defaults[118] ;
+  wire \gpio_defaults[119] ;
+  wire \gpio_defaults[11] ;
+  wire \gpio_defaults[120] ;
+  wire \gpio_defaults[121] ;
+  wire \gpio_defaults[122] ;
+  wire \gpio_defaults[123] ;
+  wire \gpio_defaults[124] ;
+  wire \gpio_defaults[125] ;
+  wire \gpio_defaults[126] ;
+  wire \gpio_defaults[127] ;
+  wire \gpio_defaults[128] ;
+  wire \gpio_defaults[129] ;
+  wire \gpio_defaults[12] ;
+  wire \gpio_defaults[130] ;
+  wire \gpio_defaults[131] ;
+  wire \gpio_defaults[132] ;
+  wire \gpio_defaults[133] ;
+  wire \gpio_defaults[134] ;
+  wire \gpio_defaults[135] ;
+  wire \gpio_defaults[136] ;
+  wire \gpio_defaults[137] ;
+  wire \gpio_defaults[138] ;
+  wire \gpio_defaults[139] ;
+  wire \gpio_defaults[13] ;
+  wire \gpio_defaults[140] ;
+  wire \gpio_defaults[141] ;
+  wire \gpio_defaults[142] ;
+  wire \gpio_defaults[143] ;
+  wire \gpio_defaults[144] ;
+  wire \gpio_defaults[145] ;
+  wire \gpio_defaults[146] ;
+  wire \gpio_defaults[147] ;
+  wire \gpio_defaults[148] ;
+  wire \gpio_defaults[149] ;
+  wire \gpio_defaults[14] ;
+  wire \gpio_defaults[150] ;
+  wire \gpio_defaults[151] ;
+  wire \gpio_defaults[152] ;
+  wire \gpio_defaults[153] ;
+  wire \gpio_defaults[154] ;
+  wire \gpio_defaults[155] ;
+  wire \gpio_defaults[156] ;
+  wire \gpio_defaults[157] ;
+  wire \gpio_defaults[158] ;
+  wire \gpio_defaults[159] ;
+  wire \gpio_defaults[15] ;
+  wire \gpio_defaults[160] ;
+  wire \gpio_defaults[161] ;
+  wire \gpio_defaults[162] ;
+  wire \gpio_defaults[163] ;
+  wire \gpio_defaults[164] ;
+  wire \gpio_defaults[165] ;
+  wire \gpio_defaults[166] ;
+  wire \gpio_defaults[167] ;
+  wire \gpio_defaults[168] ;
+  wire \gpio_defaults[169] ;
+  wire \gpio_defaults[16] ;
+  wire \gpio_defaults[170] ;
+  wire \gpio_defaults[171] ;
+  wire \gpio_defaults[172] ;
+  wire \gpio_defaults[173] ;
+  wire \gpio_defaults[174] ;
+  wire \gpio_defaults[175] ;
+  wire \gpio_defaults[176] ;
+  wire \gpio_defaults[177] ;
+  wire \gpio_defaults[178] ;
+  wire \gpio_defaults[179] ;
+  wire \gpio_defaults[17] ;
+  wire \gpio_defaults[180] ;
+  wire \gpio_defaults[181] ;
+  wire \gpio_defaults[182] ;
+  wire \gpio_defaults[183] ;
+  wire \gpio_defaults[184] ;
+  wire \gpio_defaults[185] ;
+  wire \gpio_defaults[186] ;
+  wire \gpio_defaults[187] ;
+  wire \gpio_defaults[188] ;
+  wire \gpio_defaults[189] ;
+  wire \gpio_defaults[18] ;
+  wire \gpio_defaults[190] ;
+  wire \gpio_defaults[191] ;
+  wire \gpio_defaults[192] ;
+  wire \gpio_defaults[193] ;
+  wire \gpio_defaults[194] ;
+  wire \gpio_defaults[195] ;
+  wire \gpio_defaults[196] ;
+  wire \gpio_defaults[197] ;
+  wire \gpio_defaults[198] ;
+  wire \gpio_defaults[199] ;
+  wire \gpio_defaults[19] ;
+  wire \gpio_defaults[1] ;
+  wire \gpio_defaults[200] ;
+  wire \gpio_defaults[201] ;
+  wire \gpio_defaults[202] ;
+  wire \gpio_defaults[203] ;
+  wire \gpio_defaults[204] ;
+  wire \gpio_defaults[205] ;
+  wire \gpio_defaults[206] ;
+  wire \gpio_defaults[207] ;
+  wire \gpio_defaults[208] ;
+  wire \gpio_defaults[209] ;
+  wire \gpio_defaults[20] ;
+  wire \gpio_defaults[210] ;
+  wire \gpio_defaults[211] ;
+  wire \gpio_defaults[212] ;
+  wire \gpio_defaults[213] ;
+  wire \gpio_defaults[214] ;
+  wire \gpio_defaults[215] ;
+  wire \gpio_defaults[216] ;
+  wire \gpio_defaults[217] ;
+  wire \gpio_defaults[218] ;
+  wire \gpio_defaults[219] ;
+  wire \gpio_defaults[21] ;
+  wire \gpio_defaults[220] ;
+  wire \gpio_defaults[221] ;
+  wire \gpio_defaults[222] ;
+  wire \gpio_defaults[223] ;
+  wire \gpio_defaults[224] ;
+  wire \gpio_defaults[225] ;
+  wire \gpio_defaults[226] ;
+  wire \gpio_defaults[227] ;
+  wire \gpio_defaults[228] ;
+  wire \gpio_defaults[229] ;
+  wire \gpio_defaults[22] ;
+  wire \gpio_defaults[230] ;
+  wire \gpio_defaults[231] ;
+  wire \gpio_defaults[232] ;
+  wire \gpio_defaults[233] ;
+  wire \gpio_defaults[234] ;
+  wire \gpio_defaults[235] ;
+  wire \gpio_defaults[236] ;
+  wire \gpio_defaults[237] ;
+  wire \gpio_defaults[238] ;
+  wire \gpio_defaults[239] ;
+  wire \gpio_defaults[23] ;
+  wire \gpio_defaults[240] ;
+  wire \gpio_defaults[241] ;
+  wire \gpio_defaults[242] ;
+  wire \gpio_defaults[243] ;
+  wire \gpio_defaults[244] ;
+  wire \gpio_defaults[245] ;
+  wire \gpio_defaults[246] ;
+  wire \gpio_defaults[247] ;
+  wire \gpio_defaults[248] ;
+  wire \gpio_defaults[249] ;
+  wire \gpio_defaults[24] ;
+  wire \gpio_defaults[250] ;
+  wire \gpio_defaults[251] ;
+  wire \gpio_defaults[252] ;
+  wire \gpio_defaults[253] ;
+  wire \gpio_defaults[254] ;
+  wire \gpio_defaults[255] ;
+  wire \gpio_defaults[256] ;
+  wire \gpio_defaults[257] ;
+  wire \gpio_defaults[258] ;
+  wire \gpio_defaults[259] ;
+  wire \gpio_defaults[25] ;
+  wire \gpio_defaults[260] ;
+  wire \gpio_defaults[261] ;
+  wire \gpio_defaults[262] ;
+  wire \gpio_defaults[263] ;
+  wire \gpio_defaults[264] ;
+  wire \gpio_defaults[265] ;
+  wire \gpio_defaults[266] ;
+  wire \gpio_defaults[267] ;
+  wire \gpio_defaults[268] ;
+  wire \gpio_defaults[269] ;
+  wire \gpio_defaults[26] ;
+  wire \gpio_defaults[270] ;
+  wire \gpio_defaults[271] ;
+  wire \gpio_defaults[272] ;
+  wire \gpio_defaults[273] ;
+  wire \gpio_defaults[274] ;
+  wire \gpio_defaults[275] ;
+  wire \gpio_defaults[276] ;
+  wire \gpio_defaults[277] ;
+  wire \gpio_defaults[278] ;
+  wire \gpio_defaults[279] ;
+  wire \gpio_defaults[27] ;
+  wire \gpio_defaults[280] ;
+  wire \gpio_defaults[281] ;
+  wire \gpio_defaults[282] ;
+  wire \gpio_defaults[283] ;
+  wire \gpio_defaults[284] ;
+  wire \gpio_defaults[285] ;
+  wire \gpio_defaults[286] ;
+  wire \gpio_defaults[287] ;
+  wire \gpio_defaults[288] ;
+  wire \gpio_defaults[289] ;
+  wire \gpio_defaults[28] ;
+  wire \gpio_defaults[290] ;
+  wire \gpio_defaults[291] ;
+  wire \gpio_defaults[292] ;
+  wire \gpio_defaults[293] ;
+  wire \gpio_defaults[294] ;
+  wire \gpio_defaults[295] ;
+  wire \gpio_defaults[296] ;
+  wire \gpio_defaults[297] ;
+  wire \gpio_defaults[298] ;
+  wire \gpio_defaults[299] ;
+  wire \gpio_defaults[29] ;
+  wire \gpio_defaults[2] ;
+  wire \gpio_defaults[300] ;
+  wire \gpio_defaults[301] ;
+  wire \gpio_defaults[302] ;
+  wire \gpio_defaults[303] ;
+  wire \gpio_defaults[304] ;
+  wire \gpio_defaults[305] ;
+  wire \gpio_defaults[306] ;
+  wire \gpio_defaults[307] ;
+  wire \gpio_defaults[308] ;
+  wire \gpio_defaults[309] ;
+  wire \gpio_defaults[30] ;
+  wire \gpio_defaults[310] ;
+  wire \gpio_defaults[311] ;
+  wire \gpio_defaults[312] ;
+  wire \gpio_defaults[313] ;
+  wire \gpio_defaults[314] ;
+  wire \gpio_defaults[315] ;
+  wire \gpio_defaults[316] ;
+  wire \gpio_defaults[317] ;
+  wire \gpio_defaults[318] ;
+  wire \gpio_defaults[319] ;
+  wire \gpio_defaults[31] ;
+  wire \gpio_defaults[320] ;
+  wire \gpio_defaults[321] ;
+  wire \gpio_defaults[322] ;
+  wire \gpio_defaults[323] ;
+  wire \gpio_defaults[324] ;
+  wire \gpio_defaults[325] ;
+  wire \gpio_defaults[326] ;
+  wire \gpio_defaults[327] ;
+  wire \gpio_defaults[328] ;
+  wire \gpio_defaults[329] ;
+  wire \gpio_defaults[32] ;
+  wire \gpio_defaults[330] ;
+  wire \gpio_defaults[331] ;
+  wire \gpio_defaults[332] ;
+  wire \gpio_defaults[333] ;
+  wire \gpio_defaults[334] ;
+  wire \gpio_defaults[335] ;
+  wire \gpio_defaults[336] ;
+  wire \gpio_defaults[337] ;
+  wire \gpio_defaults[338] ;
+  wire \gpio_defaults[339] ;
+  wire \gpio_defaults[33] ;
+  wire \gpio_defaults[340] ;
+  wire \gpio_defaults[341] ;
+  wire \gpio_defaults[342] ;
+  wire \gpio_defaults[343] ;
+  wire \gpio_defaults[344] ;
+  wire \gpio_defaults[345] ;
+  wire \gpio_defaults[346] ;
+  wire \gpio_defaults[347] ;
+  wire \gpio_defaults[348] ;
+  wire \gpio_defaults[349] ;
+  wire \gpio_defaults[34] ;
+  wire \gpio_defaults[350] ;
+  wire \gpio_defaults[35] ;
+  wire \gpio_defaults[36] ;
+  wire \gpio_defaults[37] ;
+  wire \gpio_defaults[38] ;
+  wire \gpio_defaults[39] ;
+  wire \gpio_defaults[3] ;
+  wire \gpio_defaults[40] ;
+  wire \gpio_defaults[41] ;
+  wire \gpio_defaults[42] ;
+  wire \gpio_defaults[43] ;
+  wire \gpio_defaults[44] ;
+  wire \gpio_defaults[45] ;
+  wire \gpio_defaults[46] ;
+  wire \gpio_defaults[47] ;
+  wire \gpio_defaults[48] ;
+  wire \gpio_defaults[49] ;
+  wire \gpio_defaults[4] ;
+  wire \gpio_defaults[50] ;
+  wire \gpio_defaults[51] ;
+  wire \gpio_defaults[52] ;
+  wire \gpio_defaults[53] ;
+  wire \gpio_defaults[54] ;
+  wire \gpio_defaults[55] ;
+  wire \gpio_defaults[56] ;
+  wire \gpio_defaults[57] ;
+  wire \gpio_defaults[58] ;
+  wire \gpio_defaults[59] ;
+  wire \gpio_defaults[5] ;
+  wire \gpio_defaults[60] ;
+  wire \gpio_defaults[61] ;
+  wire \gpio_defaults[62] ;
+  wire \gpio_defaults[63] ;
+  wire \gpio_defaults[64] ;
+  wire \gpio_defaults[65] ;
+  wire \gpio_defaults[66] ;
+  wire \gpio_defaults[67] ;
+  wire \gpio_defaults[68] ;
+  wire \gpio_defaults[69] ;
+  wire \gpio_defaults[6] ;
+  wire \gpio_defaults[70] ;
+  wire \gpio_defaults[71] ;
+  wire \gpio_defaults[72] ;
+  wire \gpio_defaults[73] ;
+  wire \gpio_defaults[74] ;
+  wire \gpio_defaults[75] ;
+  wire \gpio_defaults[76] ;
+  wire \gpio_defaults[77] ;
+  wire \gpio_defaults[78] ;
+  wire \gpio_defaults[79] ;
+  wire \gpio_defaults[7] ;
+  wire \gpio_defaults[80] ;
+  wire \gpio_defaults[81] ;
+  wire \gpio_defaults[82] ;
+  wire \gpio_defaults[83] ;
+  wire \gpio_defaults[84] ;
+  wire \gpio_defaults[85] ;
+  wire \gpio_defaults[86] ;
+  wire \gpio_defaults[87] ;
+  wire \gpio_defaults[88] ;
+  wire \gpio_defaults[89] ;
+  wire \gpio_defaults[8] ;
+  wire \gpio_defaults[90] ;
+  wire \gpio_defaults[91] ;
+  wire \gpio_defaults[92] ;
+  wire \gpio_defaults[93] ;
+  wire \gpio_defaults[94] ;
+  wire \gpio_defaults[95] ;
+  wire \gpio_defaults[96] ;
+  wire \gpio_defaults[97] ;
+  wire \gpio_defaults[98] ;
+  wire \gpio_defaults[99] ;
+  wire \gpio_defaults[9] ;
+  wire gpio_in_core;
+  wire gpio_inenb_core;
+  wire \gpio_load_1[0] ;
+  wire \gpio_load_1[10] ;
+  wire \gpio_load_1[11] ;
+  wire \gpio_load_1[12] ;
+  wire \gpio_load_1[13] ;
+  wire \gpio_load_1[14] ;
+  wire \gpio_load_1[15] ;
+  wire \gpio_load_1[16] ;
+  wire \gpio_load_1[17] ;
+  wire \gpio_load_1[18] ;
+  wire \gpio_load_1[1] ;
+  wire \gpio_load_1[2] ;
+  wire \gpio_load_1[3] ;
+  wire \gpio_load_1[4] ;
+  wire \gpio_load_1[5] ;
+  wire \gpio_load_1[6] ;
+  wire \gpio_load_1[7] ;
+  wire \gpio_load_1[8] ;
+  wire \gpio_load_1[9] ;
+  wire \gpio_load_1_shifted[0] ;
+  wire \gpio_load_1_shifted[10] ;
+  wire \gpio_load_1_shifted[11] ;
+  wire \gpio_load_1_shifted[12] ;
+  wire \gpio_load_1_shifted[13] ;
+  wire \gpio_load_1_shifted[1] ;
+  wire \gpio_load_1_shifted[2] ;
+  wire \gpio_load_1_shifted[3] ;
+  wire \gpio_load_1_shifted[4] ;
+  wire \gpio_load_1_shifted[5] ;
+  wire \gpio_load_1_shifted[6] ;
+  wire \gpio_load_1_shifted[7] ;
+  wire \gpio_load_1_shifted[8] ;
+  wire \gpio_load_1_shifted[9] ;
+  wire \gpio_load_2[0] ;
+  wire \gpio_load_2[10] ;
+  wire \gpio_load_2[11] ;
+  wire \gpio_load_2[12] ;
+  wire \gpio_load_2[13] ;
+  wire \gpio_load_2[14] ;
+  wire \gpio_load_2[15] ;
+  wire \gpio_load_2[16] ;
+  wire \gpio_load_2[17] ;
+  wire \gpio_load_2[18] ;
+  wire \gpio_load_2[1] ;
+  wire \gpio_load_2[2] ;
+  wire \gpio_load_2[3] ;
+  wire \gpio_load_2[4] ;
+  wire \gpio_load_2[5] ;
+  wire \gpio_load_2[6] ;
+  wire \gpio_load_2[7] ;
+  wire \gpio_load_2[8] ;
+  wire \gpio_load_2[9] ;
+  wire \gpio_load_2_shifted[0] ;
+  wire \gpio_load_2_shifted[10] ;
+  wire \gpio_load_2_shifted[11] ;
+  wire \gpio_load_2_shifted[12] ;
+  wire \gpio_load_2_shifted[1] ;
+  wire \gpio_load_2_shifted[2] ;
+  wire \gpio_load_2_shifted[3] ;
+  wire \gpio_load_2_shifted[4] ;
+  wire \gpio_load_2_shifted[5] ;
+  wire \gpio_load_2_shifted[6] ;
+  wire \gpio_load_2_shifted[7] ;
+  wire \gpio_load_2_shifted[8] ;
+  wire \gpio_load_2_shifted[9] ;
+  wire gpio_mode0_core;
+  wire gpio_mode1_core;
+  wire gpio_out_core;
+  wire gpio_outenb_core;
+  wire \gpio_resetn_1[0] ;
+  wire \gpio_resetn_1[10] ;
+  wire \gpio_resetn_1[11] ;
+  wire \gpio_resetn_1[12] ;
+  wire \gpio_resetn_1[13] ;
+  wire \gpio_resetn_1[14] ;
+  wire \gpio_resetn_1[15] ;
+  wire \gpio_resetn_1[16] ;
+  wire \gpio_resetn_1[17] ;
+  wire \gpio_resetn_1[18] ;
+  wire \gpio_resetn_1[1] ;
+  wire \gpio_resetn_1[2] ;
+  wire \gpio_resetn_1[3] ;
+  wire \gpio_resetn_1[4] ;
+  wire \gpio_resetn_1[5] ;
+  wire \gpio_resetn_1[6] ;
+  wire \gpio_resetn_1[7] ;
+  wire \gpio_resetn_1[8] ;
+  wire \gpio_resetn_1[9] ;
+  wire \gpio_resetn_1_shifted[0] ;
+  wire \gpio_resetn_1_shifted[10] ;
+  wire \gpio_resetn_1_shifted[11] ;
+  wire \gpio_resetn_1_shifted[12] ;
+  wire \gpio_resetn_1_shifted[13] ;
+  wire \gpio_resetn_1_shifted[1] ;
+  wire \gpio_resetn_1_shifted[2] ;
+  wire \gpio_resetn_1_shifted[3] ;
+  wire \gpio_resetn_1_shifted[4] ;
+  wire \gpio_resetn_1_shifted[5] ;
+  wire \gpio_resetn_1_shifted[6] ;
+  wire \gpio_resetn_1_shifted[7] ;
+  wire \gpio_resetn_1_shifted[8] ;
+  wire \gpio_resetn_1_shifted[9] ;
+  wire \gpio_resetn_2[0] ;
+  wire \gpio_resetn_2[10] ;
+  wire \gpio_resetn_2[11] ;
+  wire \gpio_resetn_2[12] ;
+  wire \gpio_resetn_2[13] ;
+  wire \gpio_resetn_2[14] ;
+  wire \gpio_resetn_2[15] ;
+  wire \gpio_resetn_2[16] ;
+  wire \gpio_resetn_2[17] ;
+  wire \gpio_resetn_2[18] ;
+  wire \gpio_resetn_2[1] ;
+  wire \gpio_resetn_2[2] ;
+  wire \gpio_resetn_2[3] ;
+  wire \gpio_resetn_2[4] ;
+  wire \gpio_resetn_2[5] ;
+  wire \gpio_resetn_2[6] ;
+  wire \gpio_resetn_2[7] ;
+  wire \gpio_resetn_2[8] ;
+  wire \gpio_resetn_2[9] ;
+  wire \gpio_resetn_2_shifted[0] ;
+  wire \gpio_resetn_2_shifted[10] ;
+  wire \gpio_resetn_2_shifted[11] ;
+  wire \gpio_resetn_2_shifted[12] ;
+  wire \gpio_resetn_2_shifted[1] ;
+  wire \gpio_resetn_2_shifted[2] ;
+  wire \gpio_resetn_2_shifted[3] ;
+  wire \gpio_resetn_2_shifted[4] ;
+  wire \gpio_resetn_2_shifted[5] ;
+  wire \gpio_resetn_2_shifted[6] ;
+  wire \gpio_resetn_2_shifted[7] ;
+  wire \gpio_resetn_2_shifted[8] ;
+  wire \gpio_resetn_2_shifted[9] ;
+  wire \gpio_serial_link_1[0] ;
+  wire \gpio_serial_link_1[10] ;
+  wire \gpio_serial_link_1[11] ;
+  wire \gpio_serial_link_1[12] ;
+  wire \gpio_serial_link_1[13] ;
+  wire \gpio_serial_link_1[1] ;
+  wire \gpio_serial_link_1[2] ;
+  wire \gpio_serial_link_1[3] ;
+  wire \gpio_serial_link_1[4] ;
+  wire \gpio_serial_link_1[5] ;
+  wire \gpio_serial_link_1[6] ;
+  wire \gpio_serial_link_1[7] ;
+  wire \gpio_serial_link_1[8] ;
+  wire \gpio_serial_link_1[9] ;
+  wire \gpio_serial_link_1_shifted[0] ;
+  wire \gpio_serial_link_1_shifted[10] ;
+  wire \gpio_serial_link_1_shifted[11] ;
+  wire \gpio_serial_link_1_shifted[12] ;
+  wire \gpio_serial_link_1_shifted[13] ;
+  wire \gpio_serial_link_1_shifted[1] ;
+  wire \gpio_serial_link_1_shifted[2] ;
+  wire \gpio_serial_link_1_shifted[3] ;
+  wire \gpio_serial_link_1_shifted[4] ;
+  wire \gpio_serial_link_1_shifted[5] ;
+  wire \gpio_serial_link_1_shifted[6] ;
+  wire \gpio_serial_link_1_shifted[7] ;
+  wire \gpio_serial_link_1_shifted[8] ;
+  wire \gpio_serial_link_1_shifted[9] ;
+  wire \gpio_serial_link_2[0] ;
+  wire \gpio_serial_link_2[10] ;
+  wire \gpio_serial_link_2[11] ;
+  wire \gpio_serial_link_2[12] ;
+  wire \gpio_serial_link_2[1] ;
+  wire \gpio_serial_link_2[2] ;
+  wire \gpio_serial_link_2[3] ;
+  wire \gpio_serial_link_2[4] ;
+  wire \gpio_serial_link_2[5] ;
+  wire \gpio_serial_link_2[6] ;
+  wire \gpio_serial_link_2[7] ;
+  wire \gpio_serial_link_2[8] ;
+  wire \gpio_serial_link_2[9] ;
+  wire \gpio_serial_link_2_shifted[0] ;
+  wire \gpio_serial_link_2_shifted[10] ;
+  wire \gpio_serial_link_2_shifted[11] ;
+  wire \gpio_serial_link_2_shifted[12] ;
+  wire \gpio_serial_link_2_shifted[1] ;
+  wire \gpio_serial_link_2_shifted[2] ;
+  wire \gpio_serial_link_2_shifted[3] ;
+  wire \gpio_serial_link_2_shifted[4] ;
+  wire \gpio_serial_link_2_shifted[5] ;
+  wire \gpio_serial_link_2_shifted[6] ;
+  wire \gpio_serial_link_2_shifted[7] ;
+  wire \gpio_serial_link_2_shifted[8] ;
+  wire \gpio_serial_link_2_shifted[9] ;
+  wire hk_ack_i;
+  wire \hk_dat_i[0] ;
+  wire \hk_dat_i[10] ;
+  wire \hk_dat_i[11] ;
+  wire \hk_dat_i[12] ;
+  wire \hk_dat_i[13] ;
+  wire \hk_dat_i[14] ;
+  wire \hk_dat_i[15] ;
+  wire \hk_dat_i[16] ;
+  wire \hk_dat_i[17] ;
+  wire \hk_dat_i[18] ;
+  wire \hk_dat_i[19] ;
+  wire \hk_dat_i[1] ;
+  wire \hk_dat_i[20] ;
+  wire \hk_dat_i[21] ;
+  wire \hk_dat_i[22] ;
+  wire \hk_dat_i[23] ;
+  wire \hk_dat_i[24] ;
+  wire \hk_dat_i[25] ;
+  wire \hk_dat_i[26] ;
+  wire \hk_dat_i[27] ;
+  wire \hk_dat_i[28] ;
+  wire \hk_dat_i[29] ;
+  wire \hk_dat_i[2] ;
+  wire \hk_dat_i[30] ;
+  wire \hk_dat_i[31] ;
+  wire \hk_dat_i[3] ;
+  wire \hk_dat_i[4] ;
+  wire \hk_dat_i[5] ;
+  wire \hk_dat_i[6] ;
+  wire \hk_dat_i[7] ;
+  wire \hk_dat_i[8] ;
+  wire \hk_dat_i[9] ;
+  wire hk_stb_o;
+  wire hk_cyc_o;
+  wire \hkspi_sram_addr[0] ;
+  wire \hkspi_sram_addr[1] ;
+  wire \hkspi_sram_addr[2] ;
+  wire \hkspi_sram_addr[3] ;
+  wire \hkspi_sram_addr[4] ;
+  wire \hkspi_sram_addr[5] ;
+  wire \hkspi_sram_addr[6] ;
+  wire \hkspi_sram_addr[7] ;
+  wire hkspi_sram_clk;
+  wire hkspi_sram_csb;
+  wire \hkspi_sram_data[0] ;
+  wire \hkspi_sram_data[10] ;
+  wire \hkspi_sram_data[11] ;
+  wire \hkspi_sram_data[12] ;
+  wire \hkspi_sram_data[13] ;
+  wire \hkspi_sram_data[14] ;
+  wire \hkspi_sram_data[15] ;
+  wire \hkspi_sram_data[16] ;
+  wire \hkspi_sram_data[17] ;
+  wire \hkspi_sram_data[18] ;
+  wire \hkspi_sram_data[19] ;
+  wire \hkspi_sram_data[1] ;
+  wire \hkspi_sram_data[20] ;
+  wire \hkspi_sram_data[21] ;
+  wire \hkspi_sram_data[22] ;
+  wire \hkspi_sram_data[23] ;
+  wire \hkspi_sram_data[24] ;
+  wire \hkspi_sram_data[25] ;
+  wire \hkspi_sram_data[26] ;
+  wire \hkspi_sram_data[27] ;
+  wire \hkspi_sram_data[28] ;
+  wire \hkspi_sram_data[29] ;
+  wire \hkspi_sram_data[2] ;
+  wire \hkspi_sram_data[30] ;
+  wire \hkspi_sram_data[31] ;
+  wire \hkspi_sram_data[3] ;
+  wire \hkspi_sram_data[4] ;
+  wire \hkspi_sram_data[5] ;
+  wire \hkspi_sram_data[6] ;
+  wire \hkspi_sram_data[7] ;
+  wire \hkspi_sram_data[8] ;
+  wire \hkspi_sram_data[9] ;
+  wire \irq_spi[0] ;
+  wire \irq_spi[1] ;
+  wire \irq_spi[2] ;
+  wire jtag_out;
+  wire jtag_outenb;
+  wire \la_data_in_mprj[0] ;
+  wire \la_data_in_mprj[100] ;
+  wire \la_data_in_mprj[101] ;
+  wire \la_data_in_mprj[102] ;
+  wire \la_data_in_mprj[103] ;
+  wire \la_data_in_mprj[104] ;
+  wire \la_data_in_mprj[105] ;
+  wire \la_data_in_mprj[106] ;
+  wire \la_data_in_mprj[107] ;
+  wire \la_data_in_mprj[108] ;
+  wire \la_data_in_mprj[109] ;
+  wire \la_data_in_mprj[10] ;
+  wire \la_data_in_mprj[110] ;
+  wire \la_data_in_mprj[111] ;
+  wire \la_data_in_mprj[112] ;
+  wire \la_data_in_mprj[113] ;
+  wire \la_data_in_mprj[114] ;
+  wire \la_data_in_mprj[115] ;
+  wire \la_data_in_mprj[116] ;
+  wire \la_data_in_mprj[117] ;
+  wire \la_data_in_mprj[118] ;
+  wire \la_data_in_mprj[119] ;
+  wire \la_data_in_mprj[11] ;
+  wire \la_data_in_mprj[120] ;
+  wire \la_data_in_mprj[121] ;
+  wire \la_data_in_mprj[122] ;
+  wire \la_data_in_mprj[123] ;
+  wire \la_data_in_mprj[124] ;
+  wire \la_data_in_mprj[125] ;
+  wire \la_data_in_mprj[126] ;
+  wire \la_data_in_mprj[127] ;
+  wire \la_data_in_mprj[12] ;
+  wire \la_data_in_mprj[13] ;
+  wire \la_data_in_mprj[14] ;
+  wire \la_data_in_mprj[15] ;
+  wire \la_data_in_mprj[16] ;
+  wire \la_data_in_mprj[17] ;
+  wire \la_data_in_mprj[18] ;
+  wire \la_data_in_mprj[19] ;
+  wire \la_data_in_mprj[1] ;
+  wire \la_data_in_mprj[20] ;
+  wire \la_data_in_mprj[21] ;
+  wire \la_data_in_mprj[22] ;
+  wire \la_data_in_mprj[23] ;
+  wire \la_data_in_mprj[24] ;
+  wire \la_data_in_mprj[25] ;
+  wire \la_data_in_mprj[26] ;
+  wire \la_data_in_mprj[27] ;
+  wire \la_data_in_mprj[28] ;
+  wire \la_data_in_mprj[29] ;
+  wire \la_data_in_mprj[2] ;
+  wire \la_data_in_mprj[30] ;
+  wire \la_data_in_mprj[31] ;
+  wire \la_data_in_mprj[32] ;
+  wire \la_data_in_mprj[33] ;
+  wire \la_data_in_mprj[34] ;
+  wire \la_data_in_mprj[35] ;
+  wire \la_data_in_mprj[36] ;
+  wire \la_data_in_mprj[37] ;
+  wire \la_data_in_mprj[38] ;
+  wire \la_data_in_mprj[39] ;
+  wire \la_data_in_mprj[3] ;
+  wire \la_data_in_mprj[40] ;
+  wire \la_data_in_mprj[41] ;
+  wire \la_data_in_mprj[42] ;
+  wire \la_data_in_mprj[43] ;
+  wire \la_data_in_mprj[44] ;
+  wire \la_data_in_mprj[45] ;
+  wire \la_data_in_mprj[46] ;
+  wire \la_data_in_mprj[47] ;
+  wire \la_data_in_mprj[48] ;
+  wire \la_data_in_mprj[49] ;
+  wire \la_data_in_mprj[4] ;
+  wire \la_data_in_mprj[50] ;
+  wire \la_data_in_mprj[51] ;
+  wire \la_data_in_mprj[52] ;
+  wire \la_data_in_mprj[53] ;
+  wire \la_data_in_mprj[54] ;
+  wire \la_data_in_mprj[55] ;
+  wire \la_data_in_mprj[56] ;
+  wire \la_data_in_mprj[57] ;
+  wire \la_data_in_mprj[58] ;
+  wire \la_data_in_mprj[59] ;
+  wire \la_data_in_mprj[5] ;
+  wire \la_data_in_mprj[60] ;
+  wire \la_data_in_mprj[61] ;
+  wire \la_data_in_mprj[62] ;
+  wire \la_data_in_mprj[63] ;
+  wire \la_data_in_mprj[64] ;
+  wire \la_data_in_mprj[65] ;
+  wire \la_data_in_mprj[66] ;
+  wire \la_data_in_mprj[67] ;
+  wire \la_data_in_mprj[68] ;
+  wire \la_data_in_mprj[69] ;
+  wire \la_data_in_mprj[6] ;
+  wire \la_data_in_mprj[70] ;
+  wire \la_data_in_mprj[71] ;
+  wire \la_data_in_mprj[72] ;
+  wire \la_data_in_mprj[73] ;
+  wire \la_data_in_mprj[74] ;
+  wire \la_data_in_mprj[75] ;
+  wire \la_data_in_mprj[76] ;
+  wire \la_data_in_mprj[77] ;
+  wire \la_data_in_mprj[78] ;
+  wire \la_data_in_mprj[79] ;
+  wire \la_data_in_mprj[7] ;
+  wire \la_data_in_mprj[80] ;
+  wire \la_data_in_mprj[81] ;
+  wire \la_data_in_mprj[82] ;
+  wire \la_data_in_mprj[83] ;
+  wire \la_data_in_mprj[84] ;
+  wire \la_data_in_mprj[85] ;
+  wire \la_data_in_mprj[86] ;
+  wire \la_data_in_mprj[87] ;
+  wire \la_data_in_mprj[88] ;
+  wire \la_data_in_mprj[89] ;
+  wire \la_data_in_mprj[8] ;
+  wire \la_data_in_mprj[90] ;
+  wire \la_data_in_mprj[91] ;
+  wire \la_data_in_mprj[92] ;
+  wire \la_data_in_mprj[93] ;
+  wire \la_data_in_mprj[94] ;
+  wire \la_data_in_mprj[95] ;
+  wire \la_data_in_mprj[96] ;
+  wire \la_data_in_mprj[97] ;
+  wire \la_data_in_mprj[98] ;
+  wire \la_data_in_mprj[99] ;
+  wire \la_data_in_mprj[9] ;
+  wire \la_data_in_user[0] ;
+  wire \la_data_in_user[100] ;
+  wire \la_data_in_user[101] ;
+  wire \la_data_in_user[102] ;
+  wire \la_data_in_user[103] ;
+  wire \la_data_in_user[104] ;
+  wire \la_data_in_user[105] ;
+  wire \la_data_in_user[106] ;
+  wire \la_data_in_user[107] ;
+  wire \la_data_in_user[108] ;
+  wire \la_data_in_user[109] ;
+  wire \la_data_in_user[10] ;
+  wire \la_data_in_user[110] ;
+  wire \la_data_in_user[111] ;
+  wire \la_data_in_user[112] ;
+  wire \la_data_in_user[113] ;
+  wire \la_data_in_user[114] ;
+  wire \la_data_in_user[115] ;
+  wire \la_data_in_user[116] ;
+  wire \la_data_in_user[117] ;
+  wire \la_data_in_user[118] ;
+  wire \la_data_in_user[119] ;
+  wire \la_data_in_user[11] ;
+  wire \la_data_in_user[120] ;
+  wire \la_data_in_user[121] ;
+  wire \la_data_in_user[122] ;
+  wire \la_data_in_user[123] ;
+  wire \la_data_in_user[124] ;
+  wire \la_data_in_user[125] ;
+  wire \la_data_in_user[126] ;
+  wire \la_data_in_user[127] ;
+  wire \la_data_in_user[12] ;
+  wire \la_data_in_user[13] ;
+  wire \la_data_in_user[14] ;
+  wire \la_data_in_user[15] ;
+  wire \la_data_in_user[16] ;
+  wire \la_data_in_user[17] ;
+  wire \la_data_in_user[18] ;
+  wire \la_data_in_user[19] ;
+  wire \la_data_in_user[1] ;
+  wire \la_data_in_user[20] ;
+  wire \la_data_in_user[21] ;
+  wire \la_data_in_user[22] ;
+  wire \la_data_in_user[23] ;
+  wire \la_data_in_user[24] ;
+  wire \la_data_in_user[25] ;
+  wire \la_data_in_user[26] ;
+  wire \la_data_in_user[27] ;
+  wire \la_data_in_user[28] ;
+  wire \la_data_in_user[29] ;
+  wire \la_data_in_user[2] ;
+  wire \la_data_in_user[30] ;
+  wire \la_data_in_user[31] ;
+  wire \la_data_in_user[32] ;
+  wire \la_data_in_user[33] ;
+  wire \la_data_in_user[34] ;
+  wire \la_data_in_user[35] ;
+  wire \la_data_in_user[36] ;
+  wire \la_data_in_user[37] ;
+  wire \la_data_in_user[38] ;
+  wire \la_data_in_user[39] ;
+  wire \la_data_in_user[3] ;
+  wire \la_data_in_user[40] ;
+  wire \la_data_in_user[41] ;
+  wire \la_data_in_user[42] ;
+  wire \la_data_in_user[43] ;
+  wire \la_data_in_user[44] ;
+  wire \la_data_in_user[45] ;
+  wire \la_data_in_user[46] ;
+  wire \la_data_in_user[47] ;
+  wire \la_data_in_user[48] ;
+  wire \la_data_in_user[49] ;
+  wire \la_data_in_user[4] ;
+  wire \la_data_in_user[50] ;
+  wire \la_data_in_user[51] ;
+  wire \la_data_in_user[52] ;
+  wire \la_data_in_user[53] ;
+  wire \la_data_in_user[54] ;
+  wire \la_data_in_user[55] ;
+  wire \la_data_in_user[56] ;
+  wire \la_data_in_user[57] ;
+  wire \la_data_in_user[58] ;
+  wire \la_data_in_user[59] ;
+  wire \la_data_in_user[5] ;
+  wire \la_data_in_user[60] ;
+  wire \la_data_in_user[61] ;
+  wire \la_data_in_user[62] ;
+  wire \la_data_in_user[63] ;
+  wire \la_data_in_user[64] ;
+  wire \la_data_in_user[65] ;
+  wire \la_data_in_user[66] ;
+  wire \la_data_in_user[67] ;
+  wire \la_data_in_user[68] ;
+  wire \la_data_in_user[69] ;
+  wire \la_data_in_user[6] ;
+  wire \la_data_in_user[70] ;
+  wire \la_data_in_user[71] ;
+  wire \la_data_in_user[72] ;
+  wire \la_data_in_user[73] ;
+  wire \la_data_in_user[74] ;
+  wire \la_data_in_user[75] ;
+  wire \la_data_in_user[76] ;
+  wire \la_data_in_user[77] ;
+  wire \la_data_in_user[78] ;
+  wire \la_data_in_user[79] ;
+  wire \la_data_in_user[7] ;
+  wire \la_data_in_user[80] ;
+  wire \la_data_in_user[81] ;
+  wire \la_data_in_user[82] ;
+  wire \la_data_in_user[83] ;
+  wire \la_data_in_user[84] ;
+  wire \la_data_in_user[85] ;
+  wire \la_data_in_user[86] ;
+  wire \la_data_in_user[87] ;
+  wire \la_data_in_user[88] ;
+  wire \la_data_in_user[89] ;
+  wire \la_data_in_user[8] ;
+  wire \la_data_in_user[90] ;
+  wire \la_data_in_user[91] ;
+  wire \la_data_in_user[92] ;
+  wire \la_data_in_user[93] ;
+  wire \la_data_in_user[94] ;
+  wire \la_data_in_user[95] ;
+  wire \la_data_in_user[96] ;
+  wire \la_data_in_user[97] ;
+  wire \la_data_in_user[98] ;
+  wire \la_data_in_user[99] ;
+  wire \la_data_in_user[9] ;
+  wire \la_data_out_mprj[0] ;
+  wire \la_data_out_mprj[100] ;
+  wire \la_data_out_mprj[101] ;
+  wire \la_data_out_mprj[102] ;
+  wire \la_data_out_mprj[103] ;
+  wire \la_data_out_mprj[104] ;
+  wire \la_data_out_mprj[105] ;
+  wire \la_data_out_mprj[106] ;
+  wire \la_data_out_mprj[107] ;
+  wire \la_data_out_mprj[108] ;
+  wire \la_data_out_mprj[109] ;
+  wire \la_data_out_mprj[10] ;
+  wire \la_data_out_mprj[110] ;
+  wire \la_data_out_mprj[111] ;
+  wire \la_data_out_mprj[112] ;
+  wire \la_data_out_mprj[113] ;
+  wire \la_data_out_mprj[114] ;
+  wire \la_data_out_mprj[115] ;
+  wire \la_data_out_mprj[116] ;
+  wire \la_data_out_mprj[117] ;
+  wire \la_data_out_mprj[118] ;
+  wire \la_data_out_mprj[119] ;
+  wire \la_data_out_mprj[11] ;
+  wire \la_data_out_mprj[120] ;
+  wire \la_data_out_mprj[121] ;
+  wire \la_data_out_mprj[122] ;
+  wire \la_data_out_mprj[123] ;
+  wire \la_data_out_mprj[124] ;
+  wire \la_data_out_mprj[125] ;
+  wire \la_data_out_mprj[126] ;
+  wire \la_data_out_mprj[127] ;
+  wire \la_data_out_mprj[12] ;
+  wire \la_data_out_mprj[13] ;
+  wire \la_data_out_mprj[14] ;
+  wire \la_data_out_mprj[15] ;
+  wire \la_data_out_mprj[16] ;
+  wire \la_data_out_mprj[17] ;
+  wire \la_data_out_mprj[18] ;
+  wire \la_data_out_mprj[19] ;
+  wire \la_data_out_mprj[1] ;
+  wire \la_data_out_mprj[20] ;
+  wire \la_data_out_mprj[21] ;
+  wire \la_data_out_mprj[22] ;
+  wire \la_data_out_mprj[23] ;
+  wire \la_data_out_mprj[24] ;
+  wire \la_data_out_mprj[25] ;
+  wire \la_data_out_mprj[26] ;
+  wire \la_data_out_mprj[27] ;
+  wire \la_data_out_mprj[28] ;
+  wire \la_data_out_mprj[29] ;
+  wire \la_data_out_mprj[2] ;
+  wire \la_data_out_mprj[30] ;
+  wire \la_data_out_mprj[31] ;
+  wire \la_data_out_mprj[32] ;
+  wire \la_data_out_mprj[33] ;
+  wire \la_data_out_mprj[34] ;
+  wire \la_data_out_mprj[35] ;
+  wire \la_data_out_mprj[36] ;
+  wire \la_data_out_mprj[37] ;
+  wire \la_data_out_mprj[38] ;
+  wire \la_data_out_mprj[39] ;
+  wire \la_data_out_mprj[3] ;
+  wire \la_data_out_mprj[40] ;
+  wire \la_data_out_mprj[41] ;
+  wire \la_data_out_mprj[42] ;
+  wire \la_data_out_mprj[43] ;
+  wire \la_data_out_mprj[44] ;
+  wire \la_data_out_mprj[45] ;
+  wire \la_data_out_mprj[46] ;
+  wire \la_data_out_mprj[47] ;
+  wire \la_data_out_mprj[48] ;
+  wire \la_data_out_mprj[49] ;
+  wire \la_data_out_mprj[4] ;
+  wire \la_data_out_mprj[50] ;
+  wire \la_data_out_mprj[51] ;
+  wire \la_data_out_mprj[52] ;
+  wire \la_data_out_mprj[53] ;
+  wire \la_data_out_mprj[54] ;
+  wire \la_data_out_mprj[55] ;
+  wire \la_data_out_mprj[56] ;
+  wire \la_data_out_mprj[57] ;
+  wire \la_data_out_mprj[58] ;
+  wire \la_data_out_mprj[59] ;
+  wire \la_data_out_mprj[5] ;
+  wire \la_data_out_mprj[60] ;
+  wire \la_data_out_mprj[61] ;
+  wire \la_data_out_mprj[62] ;
+  wire \la_data_out_mprj[63] ;
+  wire \la_data_out_mprj[64] ;
+  wire \la_data_out_mprj[65] ;
+  wire \la_data_out_mprj[66] ;
+  wire \la_data_out_mprj[67] ;
+  wire \la_data_out_mprj[68] ;
+  wire \la_data_out_mprj[69] ;
+  wire \la_data_out_mprj[6] ;
+  wire \la_data_out_mprj[70] ;
+  wire \la_data_out_mprj[71] ;
+  wire \la_data_out_mprj[72] ;
+  wire \la_data_out_mprj[73] ;
+  wire \la_data_out_mprj[74] ;
+  wire \la_data_out_mprj[75] ;
+  wire \la_data_out_mprj[76] ;
+  wire \la_data_out_mprj[77] ;
+  wire \la_data_out_mprj[78] ;
+  wire \la_data_out_mprj[79] ;
+  wire \la_data_out_mprj[7] ;
+  wire \la_data_out_mprj[80] ;
+  wire \la_data_out_mprj[81] ;
+  wire \la_data_out_mprj[82] ;
+  wire \la_data_out_mprj[83] ;
+  wire \la_data_out_mprj[84] ;
+  wire \la_data_out_mprj[85] ;
+  wire \la_data_out_mprj[86] ;
+  wire \la_data_out_mprj[87] ;
+  wire \la_data_out_mprj[88] ;
+  wire \la_data_out_mprj[89] ;
+  wire \la_data_out_mprj[8] ;
+  wire \la_data_out_mprj[90] ;
+  wire \la_data_out_mprj[91] ;
+  wire \la_data_out_mprj[92] ;
+  wire \la_data_out_mprj[93] ;
+  wire \la_data_out_mprj[94] ;
+  wire \la_data_out_mprj[95] ;
+  wire \la_data_out_mprj[96] ;
+  wire \la_data_out_mprj[97] ;
+  wire \la_data_out_mprj[98] ;
+  wire \la_data_out_mprj[99] ;
+  wire \la_data_out_mprj[9] ;
+  wire \la_data_out_user[0] ;
+  wire \la_data_out_user[100] ;
+  wire \la_data_out_user[101] ;
+  wire \la_data_out_user[102] ;
+  wire \la_data_out_user[103] ;
+  wire \la_data_out_user[104] ;
+  wire \la_data_out_user[105] ;
+  wire \la_data_out_user[106] ;
+  wire \la_data_out_user[107] ;
+  wire \la_data_out_user[108] ;
+  wire \la_data_out_user[109] ;
+  wire \la_data_out_user[10] ;
+  wire \la_data_out_user[110] ;
+  wire \la_data_out_user[111] ;
+  wire \la_data_out_user[112] ;
+  wire \la_data_out_user[113] ;
+  wire \la_data_out_user[114] ;
+  wire \la_data_out_user[115] ;
+  wire \la_data_out_user[116] ;
+  wire \la_data_out_user[117] ;
+  wire \la_data_out_user[118] ;
+  wire \la_data_out_user[119] ;
+  wire \la_data_out_user[11] ;
+  wire \la_data_out_user[120] ;
+  wire \la_data_out_user[121] ;
+  wire \la_data_out_user[122] ;
+  wire \la_data_out_user[123] ;
+  wire \la_data_out_user[124] ;
+  wire \la_data_out_user[125] ;
+  wire \la_data_out_user[126] ;
+  wire \la_data_out_user[127] ;
+  wire \la_data_out_user[12] ;
+  wire \la_data_out_user[13] ;
+  wire \la_data_out_user[14] ;
+  wire \la_data_out_user[15] ;
+  wire \la_data_out_user[16] ;
+  wire \la_data_out_user[17] ;
+  wire \la_data_out_user[18] ;
+  wire \la_data_out_user[19] ;
+  wire \la_data_out_user[1] ;
+  wire \la_data_out_user[20] ;
+  wire \la_data_out_user[21] ;
+  wire \la_data_out_user[22] ;
+  wire \la_data_out_user[23] ;
+  wire \la_data_out_user[24] ;
+  wire \la_data_out_user[25] ;
+  wire \la_data_out_user[26] ;
+  wire \la_data_out_user[27] ;
+  wire \la_data_out_user[28] ;
+  wire \la_data_out_user[29] ;
+  wire \la_data_out_user[2] ;
+  wire \la_data_out_user[30] ;
+  wire \la_data_out_user[31] ;
+  wire \la_data_out_user[32] ;
+  wire \la_data_out_user[33] ;
+  wire \la_data_out_user[34] ;
+  wire \la_data_out_user[35] ;
+  wire \la_data_out_user[36] ;
+  wire \la_data_out_user[37] ;
+  wire \la_data_out_user[38] ;
+  wire \la_data_out_user[39] ;
+  wire \la_data_out_user[3] ;
+  wire \la_data_out_user[40] ;
+  wire \la_data_out_user[41] ;
+  wire \la_data_out_user[42] ;
+  wire \la_data_out_user[43] ;
+  wire \la_data_out_user[44] ;
+  wire \la_data_out_user[45] ;
+  wire \la_data_out_user[46] ;
+  wire \la_data_out_user[47] ;
+  wire \la_data_out_user[48] ;
+  wire \la_data_out_user[49] ;
+  wire \la_data_out_user[4] ;
+  wire \la_data_out_user[50] ;
+  wire \la_data_out_user[51] ;
+  wire \la_data_out_user[52] ;
+  wire \la_data_out_user[53] ;
+  wire \la_data_out_user[54] ;
+  wire \la_data_out_user[55] ;
+  wire \la_data_out_user[56] ;
+  wire \la_data_out_user[57] ;
+  wire \la_data_out_user[58] ;
+  wire \la_data_out_user[59] ;
+  wire \la_data_out_user[5] ;
+  wire \la_data_out_user[60] ;
+  wire \la_data_out_user[61] ;
+  wire \la_data_out_user[62] ;
+  wire \la_data_out_user[63] ;
+  wire \la_data_out_user[64] ;
+  wire \la_data_out_user[65] ;
+  wire \la_data_out_user[66] ;
+  wire \la_data_out_user[67] ;
+  wire \la_data_out_user[68] ;
+  wire \la_data_out_user[69] ;
+  wire \la_data_out_user[6] ;
+  wire \la_data_out_user[70] ;
+  wire \la_data_out_user[71] ;
+  wire \la_data_out_user[72] ;
+  wire \la_data_out_user[73] ;
+  wire \la_data_out_user[74] ;
+  wire \la_data_out_user[75] ;
+  wire \la_data_out_user[76] ;
+  wire \la_data_out_user[77] ;
+  wire \la_data_out_user[78] ;
+  wire \la_data_out_user[79] ;
+  wire \la_data_out_user[7] ;
+  wire \la_data_out_user[80] ;
+  wire \la_data_out_user[81] ;
+  wire \la_data_out_user[82] ;
+  wire \la_data_out_user[83] ;
+  wire \la_data_out_user[84] ;
+  wire \la_data_out_user[85] ;
+  wire \la_data_out_user[86] ;
+  wire \la_data_out_user[87] ;
+  wire \la_data_out_user[88] ;
+  wire \la_data_out_user[89] ;
+  wire \la_data_out_user[8] ;
+  wire \la_data_out_user[90] ;
+  wire \la_data_out_user[91] ;
+  wire \la_data_out_user[92] ;
+  wire \la_data_out_user[93] ;
+  wire \la_data_out_user[94] ;
+  wire \la_data_out_user[95] ;
+  wire \la_data_out_user[96] ;
+  wire \la_data_out_user[97] ;
+  wire \la_data_out_user[98] ;
+  wire \la_data_out_user[99] ;
+  wire \la_data_out_user[9] ;
+  wire \la_iena_mprj[0] ;
+  wire \la_iena_mprj[100] ;
+  wire \la_iena_mprj[101] ;
+  wire \la_iena_mprj[102] ;
+  wire \la_iena_mprj[103] ;
+  wire \la_iena_mprj[104] ;
+  wire \la_iena_mprj[105] ;
+  wire \la_iena_mprj[106] ;
+  wire \la_iena_mprj[107] ;
+  wire \la_iena_mprj[108] ;
+  wire \la_iena_mprj[109] ;
+  wire \la_iena_mprj[10] ;
+  wire \la_iena_mprj[110] ;
+  wire \la_iena_mprj[111] ;
+  wire \la_iena_mprj[112] ;
+  wire \la_iena_mprj[113] ;
+  wire \la_iena_mprj[114] ;
+  wire \la_iena_mprj[115] ;
+  wire \la_iena_mprj[116] ;
+  wire \la_iena_mprj[117] ;
+  wire \la_iena_mprj[118] ;
+  wire \la_iena_mprj[119] ;
+  wire \la_iena_mprj[11] ;
+  wire \la_iena_mprj[120] ;
+  wire \la_iena_mprj[121] ;
+  wire \la_iena_mprj[122] ;
+  wire \la_iena_mprj[123] ;
+  wire \la_iena_mprj[124] ;
+  wire \la_iena_mprj[125] ;
+  wire \la_iena_mprj[126] ;
+  wire \la_iena_mprj[127] ;
+  wire \la_iena_mprj[12] ;
+  wire \la_iena_mprj[13] ;
+  wire \la_iena_mprj[14] ;
+  wire \la_iena_mprj[15] ;
+  wire \la_iena_mprj[16] ;
+  wire \la_iena_mprj[17] ;
+  wire \la_iena_mprj[18] ;
+  wire \la_iena_mprj[19] ;
+  wire \la_iena_mprj[1] ;
+  wire \la_iena_mprj[20] ;
+  wire \la_iena_mprj[21] ;
+  wire \la_iena_mprj[22] ;
+  wire \la_iena_mprj[23] ;
+  wire \la_iena_mprj[24] ;
+  wire \la_iena_mprj[25] ;
+  wire \la_iena_mprj[26] ;
+  wire \la_iena_mprj[27] ;
+  wire \la_iena_mprj[28] ;
+  wire \la_iena_mprj[29] ;
+  wire \la_iena_mprj[2] ;
+  wire \la_iena_mprj[30] ;
+  wire \la_iena_mprj[31] ;
+  wire \la_iena_mprj[32] ;
+  wire \la_iena_mprj[33] ;
+  wire \la_iena_mprj[34] ;
+  wire \la_iena_mprj[35] ;
+  wire \la_iena_mprj[36] ;
+  wire \la_iena_mprj[37] ;
+  wire \la_iena_mprj[38] ;
+  wire \la_iena_mprj[39] ;
+  wire \la_iena_mprj[3] ;
+  wire \la_iena_mprj[40] ;
+  wire \la_iena_mprj[41] ;
+  wire \la_iena_mprj[42] ;
+  wire \la_iena_mprj[43] ;
+  wire \la_iena_mprj[44] ;
+  wire \la_iena_mprj[45] ;
+  wire \la_iena_mprj[46] ;
+  wire \la_iena_mprj[47] ;
+  wire \la_iena_mprj[48] ;
+  wire \la_iena_mprj[49] ;
+  wire \la_iena_mprj[4] ;
+  wire \la_iena_mprj[50] ;
+  wire \la_iena_mprj[51] ;
+  wire \la_iena_mprj[52] ;
+  wire \la_iena_mprj[53] ;
+  wire \la_iena_mprj[54] ;
+  wire \la_iena_mprj[55] ;
+  wire \la_iena_mprj[56] ;
+  wire \la_iena_mprj[57] ;
+  wire \la_iena_mprj[58] ;
+  wire \la_iena_mprj[59] ;
+  wire \la_iena_mprj[5] ;
+  wire \la_iena_mprj[60] ;
+  wire \la_iena_mprj[61] ;
+  wire \la_iena_mprj[62] ;
+  wire \la_iena_mprj[63] ;
+  wire \la_iena_mprj[64] ;
+  wire \la_iena_mprj[65] ;
+  wire \la_iena_mprj[66] ;
+  wire \la_iena_mprj[67] ;
+  wire \la_iena_mprj[68] ;
+  wire \la_iena_mprj[69] ;
+  wire \la_iena_mprj[6] ;
+  wire \la_iena_mprj[70] ;
+  wire \la_iena_mprj[71] ;
+  wire \la_iena_mprj[72] ;
+  wire \la_iena_mprj[73] ;
+  wire \la_iena_mprj[74] ;
+  wire \la_iena_mprj[75] ;
+  wire \la_iena_mprj[76] ;
+  wire \la_iena_mprj[77] ;
+  wire \la_iena_mprj[78] ;
+  wire \la_iena_mprj[79] ;
+  wire \la_iena_mprj[7] ;
+  wire \la_iena_mprj[80] ;
+  wire \la_iena_mprj[81] ;
+  wire \la_iena_mprj[82] ;
+  wire \la_iena_mprj[83] ;
+  wire \la_iena_mprj[84] ;
+  wire \la_iena_mprj[85] ;
+  wire \la_iena_mprj[86] ;
+  wire \la_iena_mprj[87] ;
+  wire \la_iena_mprj[88] ;
+  wire \la_iena_mprj[89] ;
+  wire \la_iena_mprj[8] ;
+  wire \la_iena_mprj[90] ;
+  wire \la_iena_mprj[91] ;
+  wire \la_iena_mprj[92] ;
+  wire \la_iena_mprj[93] ;
+  wire \la_iena_mprj[94] ;
+  wire \la_iena_mprj[95] ;
+  wire \la_iena_mprj[96] ;
+  wire \la_iena_mprj[97] ;
+  wire \la_iena_mprj[98] ;
+  wire \la_iena_mprj[99] ;
+  wire \la_iena_mprj[9] ;
+  wire \la_oenb_mprj[0] ;
+  wire \la_oenb_mprj[100] ;
+  wire \la_oenb_mprj[101] ;
+  wire \la_oenb_mprj[102] ;
+  wire \la_oenb_mprj[103] ;
+  wire \la_oenb_mprj[104] ;
+  wire \la_oenb_mprj[105] ;
+  wire \la_oenb_mprj[106] ;
+  wire \la_oenb_mprj[107] ;
+  wire \la_oenb_mprj[108] ;
+  wire \la_oenb_mprj[109] ;
+  wire \la_oenb_mprj[10] ;
+  wire \la_oenb_mprj[110] ;
+  wire \la_oenb_mprj[111] ;
+  wire \la_oenb_mprj[112] ;
+  wire \la_oenb_mprj[113] ;
+  wire \la_oenb_mprj[114] ;
+  wire \la_oenb_mprj[115] ;
+  wire \la_oenb_mprj[116] ;
+  wire \la_oenb_mprj[117] ;
+  wire \la_oenb_mprj[118] ;
+  wire \la_oenb_mprj[119] ;
+  wire \la_oenb_mprj[11] ;
+  wire \la_oenb_mprj[120] ;
+  wire \la_oenb_mprj[121] ;
+  wire \la_oenb_mprj[122] ;
+  wire \la_oenb_mprj[123] ;
+  wire \la_oenb_mprj[124] ;
+  wire \la_oenb_mprj[125] ;
+  wire \la_oenb_mprj[126] ;
+  wire \la_oenb_mprj[127] ;
+  wire \la_oenb_mprj[12] ;
+  wire \la_oenb_mprj[13] ;
+  wire \la_oenb_mprj[14] ;
+  wire \la_oenb_mprj[15] ;
+  wire \la_oenb_mprj[16] ;
+  wire \la_oenb_mprj[17] ;
+  wire \la_oenb_mprj[18] ;
+  wire \la_oenb_mprj[19] ;
+  wire \la_oenb_mprj[1] ;
+  wire \la_oenb_mprj[20] ;
+  wire \la_oenb_mprj[21] ;
+  wire \la_oenb_mprj[22] ;
+  wire \la_oenb_mprj[23] ;
+  wire \la_oenb_mprj[24] ;
+  wire \la_oenb_mprj[25] ;
+  wire \la_oenb_mprj[26] ;
+  wire \la_oenb_mprj[27] ;
+  wire \la_oenb_mprj[28] ;
+  wire \la_oenb_mprj[29] ;
+  wire \la_oenb_mprj[2] ;
+  wire \la_oenb_mprj[30] ;
+  wire \la_oenb_mprj[31] ;
+  wire \la_oenb_mprj[32] ;
+  wire \la_oenb_mprj[33] ;
+  wire \la_oenb_mprj[34] ;
+  wire \la_oenb_mprj[35] ;
+  wire \la_oenb_mprj[36] ;
+  wire \la_oenb_mprj[37] ;
+  wire \la_oenb_mprj[38] ;
+  wire \la_oenb_mprj[39] ;
+  wire \la_oenb_mprj[3] ;
+  wire \la_oenb_mprj[40] ;
+  wire \la_oenb_mprj[41] ;
+  wire \la_oenb_mprj[42] ;
+  wire \la_oenb_mprj[43] ;
+  wire \la_oenb_mprj[44] ;
+  wire \la_oenb_mprj[45] ;
+  wire \la_oenb_mprj[46] ;
+  wire \la_oenb_mprj[47] ;
+  wire \la_oenb_mprj[48] ;
+  wire \la_oenb_mprj[49] ;
+  wire \la_oenb_mprj[4] ;
+  wire \la_oenb_mprj[50] ;
+  wire \la_oenb_mprj[51] ;
+  wire \la_oenb_mprj[52] ;
+  wire \la_oenb_mprj[53] ;
+  wire \la_oenb_mprj[54] ;
+  wire \la_oenb_mprj[55] ;
+  wire \la_oenb_mprj[56] ;
+  wire \la_oenb_mprj[57] ;
+  wire \la_oenb_mprj[58] ;
+  wire \la_oenb_mprj[59] ;
+  wire \la_oenb_mprj[5] ;
+  wire \la_oenb_mprj[60] ;
+  wire \la_oenb_mprj[61] ;
+  wire \la_oenb_mprj[62] ;
+  wire \la_oenb_mprj[63] ;
+  wire \la_oenb_mprj[64] ;
+  wire \la_oenb_mprj[65] ;
+  wire \la_oenb_mprj[66] ;
+  wire \la_oenb_mprj[67] ;
+  wire \la_oenb_mprj[68] ;
+  wire \la_oenb_mprj[69] ;
+  wire \la_oenb_mprj[6] ;
+  wire \la_oenb_mprj[70] ;
+  wire \la_oenb_mprj[71] ;
+  wire \la_oenb_mprj[72] ;
+  wire \la_oenb_mprj[73] ;
+  wire \la_oenb_mprj[74] ;
+  wire \la_oenb_mprj[75] ;
+  wire \la_oenb_mprj[76] ;
+  wire \la_oenb_mprj[77] ;
+  wire \la_oenb_mprj[78] ;
+  wire \la_oenb_mprj[79] ;
+  wire \la_oenb_mprj[7] ;
+  wire \la_oenb_mprj[80] ;
+  wire \la_oenb_mprj[81] ;
+  wire \la_oenb_mprj[82] ;
+  wire \la_oenb_mprj[83] ;
+  wire \la_oenb_mprj[84] ;
+  wire \la_oenb_mprj[85] ;
+  wire \la_oenb_mprj[86] ;
+  wire \la_oenb_mprj[87] ;
+  wire \la_oenb_mprj[88] ;
+  wire \la_oenb_mprj[89] ;
+  wire \la_oenb_mprj[8] ;
+  wire \la_oenb_mprj[90] ;
+  wire \la_oenb_mprj[91] ;
+  wire \la_oenb_mprj[92] ;
+  wire \la_oenb_mprj[93] ;
+  wire \la_oenb_mprj[94] ;
+  wire \la_oenb_mprj[95] ;
+  wire \la_oenb_mprj[96] ;
+  wire \la_oenb_mprj[97] ;
+  wire \la_oenb_mprj[98] ;
+  wire \la_oenb_mprj[99] ;
+  wire \la_oenb_mprj[9] ;
+  wire \la_oenb_user[0] ;
+  wire \la_oenb_user[100] ;
+  wire \la_oenb_user[101] ;
+  wire \la_oenb_user[102] ;
+  wire \la_oenb_user[103] ;
+  wire \la_oenb_user[104] ;
+  wire \la_oenb_user[105] ;
+  wire \la_oenb_user[106] ;
+  wire \la_oenb_user[107] ;
+  wire \la_oenb_user[108] ;
+  wire \la_oenb_user[109] ;
+  wire \la_oenb_user[10] ;
+  wire \la_oenb_user[110] ;
+  wire \la_oenb_user[111] ;
+  wire \la_oenb_user[112] ;
+  wire \la_oenb_user[113] ;
+  wire \la_oenb_user[114] ;
+  wire \la_oenb_user[115] ;
+  wire \la_oenb_user[116] ;
+  wire \la_oenb_user[117] ;
+  wire \la_oenb_user[118] ;
+  wire \la_oenb_user[119] ;
+  wire \la_oenb_user[11] ;
+  wire \la_oenb_user[120] ;
+  wire \la_oenb_user[121] ;
+  wire \la_oenb_user[122] ;
+  wire \la_oenb_user[123] ;
+  wire \la_oenb_user[124] ;
+  wire \la_oenb_user[125] ;
+  wire \la_oenb_user[126] ;
+  wire \la_oenb_user[127] ;
+  wire \la_oenb_user[12] ;
+  wire \la_oenb_user[13] ;
+  wire \la_oenb_user[14] ;
+  wire \la_oenb_user[15] ;
+  wire \la_oenb_user[16] ;
+  wire \la_oenb_user[17] ;
+  wire \la_oenb_user[18] ;
+  wire \la_oenb_user[19] ;
+  wire \la_oenb_user[1] ;
+  wire \la_oenb_user[20] ;
+  wire \la_oenb_user[21] ;
+  wire \la_oenb_user[22] ;
+  wire \la_oenb_user[23] ;
+  wire \la_oenb_user[24] ;
+  wire \la_oenb_user[25] ;
+  wire \la_oenb_user[26] ;
+  wire \la_oenb_user[27] ;
+  wire \la_oenb_user[28] ;
+  wire \la_oenb_user[29] ;
+  wire \la_oenb_user[2] ;
+  wire \la_oenb_user[30] ;
+  wire \la_oenb_user[31] ;
+  wire \la_oenb_user[32] ;
+  wire \la_oenb_user[33] ;
+  wire \la_oenb_user[34] ;
+  wire \la_oenb_user[35] ;
+  wire \la_oenb_user[36] ;
+  wire \la_oenb_user[37] ;
+  wire \la_oenb_user[38] ;
+  wire \la_oenb_user[39] ;
+  wire \la_oenb_user[3] ;
+  wire \la_oenb_user[40] ;
+  wire \la_oenb_user[41] ;
+  wire \la_oenb_user[42] ;
+  wire \la_oenb_user[43] ;
+  wire \la_oenb_user[44] ;
+  wire \la_oenb_user[45] ;
+  wire \la_oenb_user[46] ;
+  wire \la_oenb_user[47] ;
+  wire \la_oenb_user[48] ;
+  wire \la_oenb_user[49] ;
+  wire \la_oenb_user[4] ;
+  wire \la_oenb_user[50] ;
+  wire \la_oenb_user[51] ;
+  wire \la_oenb_user[52] ;
+  wire \la_oenb_user[53] ;
+  wire \la_oenb_user[54] ;
+  wire \la_oenb_user[55] ;
+  wire \la_oenb_user[56] ;
+  wire \la_oenb_user[57] ;
+  wire \la_oenb_user[58] ;
+  wire \la_oenb_user[59] ;
+  wire \la_oenb_user[5] ;
+  wire \la_oenb_user[60] ;
+  wire \la_oenb_user[61] ;
+  wire \la_oenb_user[62] ;
+  wire \la_oenb_user[63] ;
+  wire \la_oenb_user[64] ;
+  wire \la_oenb_user[65] ;
+  wire \la_oenb_user[66] ;
+  wire \la_oenb_user[67] ;
+  wire \la_oenb_user[68] ;
+  wire \la_oenb_user[69] ;
+  wire \la_oenb_user[6] ;
+  wire \la_oenb_user[70] ;
+  wire \la_oenb_user[71] ;
+  wire \la_oenb_user[72] ;
+  wire \la_oenb_user[73] ;
+  wire \la_oenb_user[74] ;
+  wire \la_oenb_user[75] ;
+  wire \la_oenb_user[76] ;
+  wire \la_oenb_user[77] ;
+  wire \la_oenb_user[78] ;
+  wire \la_oenb_user[79] ;
+  wire \la_oenb_user[7] ;
+  wire \la_oenb_user[80] ;
+  wire \la_oenb_user[81] ;
+  wire \la_oenb_user[82] ;
+  wire \la_oenb_user[83] ;
+  wire \la_oenb_user[84] ;
+  wire \la_oenb_user[85] ;
+  wire \la_oenb_user[86] ;
+  wire \la_oenb_user[87] ;
+  wire \la_oenb_user[88] ;
+  wire \la_oenb_user[89] ;
+  wire \la_oenb_user[8] ;
+  wire \la_oenb_user[90] ;
+  wire \la_oenb_user[91] ;
+  wire \la_oenb_user[92] ;
+  wire \la_oenb_user[93] ;
+  wire \la_oenb_user[94] ;
+  wire \la_oenb_user[95] ;
+  wire \la_oenb_user[96] ;
+  wire \la_oenb_user[97] ;
+  wire \la_oenb_user[98] ;
+  wire \la_oenb_user[99] ;
+  wire \la_oenb_user[9] ;
+  wire \mask_rev[0] ;
+  wire \mask_rev[10] ;
+  wire \mask_rev[11] ;
+  wire \mask_rev[12] ;
+  wire \mask_rev[13] ;
+  wire \mask_rev[14] ;
+  wire \mask_rev[15] ;
+  wire \mask_rev[16] ;
+  wire \mask_rev[17] ;
+  wire \mask_rev[18] ;
+  wire \mask_rev[19] ;
+  wire \mask_rev[1] ;
+  wire \mask_rev[20] ;
+  wire \mask_rev[21] ;
+  wire \mask_rev[22] ;
+  wire \mask_rev[23] ;
+  wire \mask_rev[24] ;
+  wire \mask_rev[25] ;
+  wire \mask_rev[26] ;
+  wire \mask_rev[27] ;
+  wire \mask_rev[28] ;
+  wire \mask_rev[29] ;
+  wire \mask_rev[2] ;
+  wire \mask_rev[30] ;
+  wire \mask_rev[31] ;
+  wire \mask_rev[3] ;
+  wire \mask_rev[4] ;
+  wire \mask_rev[5] ;
+  wire \mask_rev[6] ;
+  wire \mask_rev[7] ;
+  wire \mask_rev[8] ;
+  wire \mask_rev[9] ;
+  wire \mgmt_io_in[0] ;
+  wire \mgmt_io_in[10] ;
+  wire \mgmt_io_in[11] ;
+  wire \mgmt_io_in[12] ;
+  wire \mgmt_io_in[13] ;
+  wire \mgmt_io_in[14] ;
+  wire \mgmt_io_in[15] ;
+  wire \mgmt_io_in[16] ;
+  wire \mgmt_io_in[17] ;
+  wire \mgmt_io_in[18] ;
+  wire \mgmt_io_in[19] ;
+  wire \mgmt_io_in[1] ;
+  wire \mgmt_io_in[20] ;
+  wire \mgmt_io_in[21] ;
+  wire \mgmt_io_in[22] ;
+  wire \mgmt_io_in[23] ;
+  wire \mgmt_io_in[24] ;
+  wire \mgmt_io_in[25] ;
+  wire \mgmt_io_in[26] ;
+  wire \mgmt_io_in[27] ;
+  wire \mgmt_io_in[28] ;
+  wire \mgmt_io_in[29] ;
+  wire \mgmt_io_in[2] ;
+  wire \mgmt_io_in[30] ;
+  wire \mgmt_io_in[31] ;
+  wire \mgmt_io_in[32] ;
+  wire \mgmt_io_in[33] ;
+  wire \mgmt_io_in[34] ;
+  wire \mgmt_io_in[35] ;
+  wire \mgmt_io_in[36] ;
+  wire \mgmt_io_in[37] ;
+  wire \mgmt_io_in[3] ;
+  wire \mgmt_io_in[4] ;
+  wire \mgmt_io_in[5] ;
+  wire \mgmt_io_in[6] ;
+  wire \mgmt_io_in[7] ;
+  wire \mgmt_io_in[8] ;
+  wire \mgmt_io_in[9] ;
+  wire \mgmt_io_nc[0] ;
+  wire \mgmt_io_nc[10] ;
+  wire \mgmt_io_nc[11] ;
+  wire \mgmt_io_nc[12] ;
+  wire \mgmt_io_nc[13] ;
+  wire \mgmt_io_nc[14] ;
+  wire \mgmt_io_nc[15] ;
+  wire \mgmt_io_nc[16] ;
+  wire \mgmt_io_nc[17] ;
+  wire \mgmt_io_nc[18] ;
+  wire \mgmt_io_nc[19] ;
+  wire \mgmt_io_nc[1] ;
+  wire \mgmt_io_nc[20] ;
+  wire \mgmt_io_nc[21] ;
+  wire \mgmt_io_nc[22] ;
+  wire \mgmt_io_nc[23] ;
+  wire \mgmt_io_nc[24] ;
+  wire \mgmt_io_nc[25] ;
+  wire \mgmt_io_nc[26] ;
+  wire \mgmt_io_nc[27] ;
+  wire \mgmt_io_nc[28] ;
+  wire \mgmt_io_nc[29] ;
+  wire \mgmt_io_nc[2] ;
+  wire \mgmt_io_nc[30] ;
+  wire \mgmt_io_nc[31] ;
+  wire \mgmt_io_nc[32] ;
+  wire \mgmt_io_nc[33] ;
+  wire \mgmt_io_nc[34] ;
+  wire \mgmt_io_nc[35] ;
+  wire \mgmt_io_nc[36] ;
+  wire \mgmt_io_nc[37] ;
+  wire \mgmt_io_nc[3] ;
+  wire \mgmt_io_nc[4] ;
+  wire \mgmt_io_nc[5] ;
+  wire \mgmt_io_nc[6] ;
+  wire \mgmt_io_nc[7] ;
+  wire \mgmt_io_nc[8] ;
+  wire \mgmt_io_nc[9] ;
+  wire \mgmt_io_oeb[0] ;
+  wire \mgmt_io_oeb[1] ;
+  wire \mgmt_io_oeb[2] ;
+  wire \mgmt_io_oeb[3] ;
+  wire \mgmt_io_oeb[4] ;
+  wire \mgmt_io_out[0] ;
+  wire \mgmt_io_out[1] ;
+  wire \mgmt_io_out[2] ;
+  wire \mgmt_io_out[3] ;
+  wire \mgmt_io_out[4] ;
+  wire mprj2_vcc_pwrgood;
+  wire mprj2_vdd_pwrgood;
+  wire mprj_ack_i_core;
+  wire mprj_ack_i_user;
+  wire \mprj_adr_o_core[0] ;
+  wire \mprj_adr_o_core[10] ;
+  wire \mprj_adr_o_core[11] ;
+  wire \mprj_adr_o_core[12] ;
+  wire \mprj_adr_o_core[13] ;
+  wire \mprj_adr_o_core[14] ;
+  wire \mprj_adr_o_core[15] ;
+  wire \mprj_adr_o_core[16] ;
+  wire \mprj_adr_o_core[17] ;
+  wire \mprj_adr_o_core[18] ;
+  wire \mprj_adr_o_core[19] ;
+  wire \mprj_adr_o_core[1] ;
+  wire \mprj_adr_o_core[20] ;
+  wire \mprj_adr_o_core[21] ;
+  wire \mprj_adr_o_core[22] ;
+  wire \mprj_adr_o_core[23] ;
+  wire \mprj_adr_o_core[24] ;
+  wire \mprj_adr_o_core[25] ;
+  wire \mprj_adr_o_core[26] ;
+  wire \mprj_adr_o_core[27] ;
+  wire \mprj_adr_o_core[28] ;
+  wire \mprj_adr_o_core[29] ;
+  wire \mprj_adr_o_core[2] ;
+  wire \mprj_adr_o_core[30] ;
+  wire \mprj_adr_o_core[31] ;
+  wire \mprj_adr_o_core[3] ;
+  wire \mprj_adr_o_core[4] ;
+  wire \mprj_adr_o_core[5] ;
+  wire \mprj_adr_o_core[6] ;
+  wire \mprj_adr_o_core[7] ;
+  wire \mprj_adr_o_core[8] ;
+  wire \mprj_adr_o_core[9] ;
+  wire \mprj_adr_o_user[0] ;
+  wire \mprj_adr_o_user[10] ;
+  wire \mprj_adr_o_user[11] ;
+  wire \mprj_adr_o_user[12] ;
+  wire \mprj_adr_o_user[13] ;
+  wire \mprj_adr_o_user[14] ;
+  wire \mprj_adr_o_user[15] ;
+  wire \mprj_adr_o_user[16] ;
+  wire \mprj_adr_o_user[17] ;
+  wire \mprj_adr_o_user[18] ;
+  wire \mprj_adr_o_user[19] ;
+  wire \mprj_adr_o_user[1] ;
+  wire \mprj_adr_o_user[20] ;
+  wire \mprj_adr_o_user[21] ;
+  wire \mprj_adr_o_user[22] ;
+  wire \mprj_adr_o_user[23] ;
+  wire \mprj_adr_o_user[24] ;
+  wire \mprj_adr_o_user[25] ;
+  wire \mprj_adr_o_user[26] ;
+  wire \mprj_adr_o_user[27] ;
+  wire \mprj_adr_o_user[28] ;
+  wire \mprj_adr_o_user[29] ;
+  wire \mprj_adr_o_user[2] ;
+  wire \mprj_adr_o_user[30] ;
+  wire \mprj_adr_o_user[31] ;
+  wire \mprj_adr_o_user[3] ;
+  wire \mprj_adr_o_user[4] ;
+  wire \mprj_adr_o_user[5] ;
+  wire \mprj_adr_o_user[6] ;
+  wire \mprj_adr_o_user[7] ;
+  wire \mprj_adr_o_user[8] ;
+  wire \mprj_adr_o_user[9] ;
+  wire mprj_clock;
+  wire mprj_clock2;
+  wire mprj_cyc_o_core;
+  wire mprj_cyc_o_user;
+  wire \mprj_dat_i_core[0] ;
+  wire \mprj_dat_i_core[10] ;
+  wire \mprj_dat_i_core[11] ;
+  wire \mprj_dat_i_core[12] ;
+  wire \mprj_dat_i_core[13] ;
+  wire \mprj_dat_i_core[14] ;
+  wire \mprj_dat_i_core[15] ;
+  wire \mprj_dat_i_core[16] ;
+  wire \mprj_dat_i_core[17] ;
+  wire \mprj_dat_i_core[18] ;
+  wire \mprj_dat_i_core[19] ;
+  wire \mprj_dat_i_core[1] ;
+  wire \mprj_dat_i_core[20] ;
+  wire \mprj_dat_i_core[21] ;
+  wire \mprj_dat_i_core[22] ;
+  wire \mprj_dat_i_core[23] ;
+  wire \mprj_dat_i_core[24] ;
+  wire \mprj_dat_i_core[25] ;
+  wire \mprj_dat_i_core[26] ;
+  wire \mprj_dat_i_core[27] ;
+  wire \mprj_dat_i_core[28] ;
+  wire \mprj_dat_i_core[29] ;
+  wire \mprj_dat_i_core[2] ;
+  wire \mprj_dat_i_core[30] ;
+  wire \mprj_dat_i_core[31] ;
+  wire \mprj_dat_i_core[3] ;
+  wire \mprj_dat_i_core[4] ;
+  wire \mprj_dat_i_core[5] ;
+  wire \mprj_dat_i_core[6] ;
+  wire \mprj_dat_i_core[7] ;
+  wire \mprj_dat_i_core[8] ;
+  wire \mprj_dat_i_core[9] ;
+  wire \mprj_dat_i_user[0] ;
+  wire \mprj_dat_i_user[10] ;
+  wire \mprj_dat_i_user[11] ;
+  wire \mprj_dat_i_user[12] ;
+  wire \mprj_dat_i_user[13] ;
+  wire \mprj_dat_i_user[14] ;
+  wire \mprj_dat_i_user[15] ;
+  wire \mprj_dat_i_user[16] ;
+  wire \mprj_dat_i_user[17] ;
+  wire \mprj_dat_i_user[18] ;
+  wire \mprj_dat_i_user[19] ;
+  wire \mprj_dat_i_user[1] ;
+  wire \mprj_dat_i_user[20] ;
+  wire \mprj_dat_i_user[21] ;
+  wire \mprj_dat_i_user[22] ;
+  wire \mprj_dat_i_user[23] ;
+  wire \mprj_dat_i_user[24] ;
+  wire \mprj_dat_i_user[25] ;
+  wire \mprj_dat_i_user[26] ;
+  wire \mprj_dat_i_user[27] ;
+  wire \mprj_dat_i_user[28] ;
+  wire \mprj_dat_i_user[29] ;
+  wire \mprj_dat_i_user[2] ;
+  wire \mprj_dat_i_user[30] ;
+  wire \mprj_dat_i_user[31] ;
+  wire \mprj_dat_i_user[3] ;
+  wire \mprj_dat_i_user[4] ;
+  wire \mprj_dat_i_user[5] ;
+  wire \mprj_dat_i_user[6] ;
+  wire \mprj_dat_i_user[7] ;
+  wire \mprj_dat_i_user[8] ;
+  wire \mprj_dat_i_user[9] ;
+  wire \mprj_dat_o_core[0] ;
+  wire \mprj_dat_o_core[10] ;
+  wire \mprj_dat_o_core[11] ;
+  wire \mprj_dat_o_core[12] ;
+  wire \mprj_dat_o_core[13] ;
+  wire \mprj_dat_o_core[14] ;
+  wire \mprj_dat_o_core[15] ;
+  wire \mprj_dat_o_core[16] ;
+  wire \mprj_dat_o_core[17] ;
+  wire \mprj_dat_o_core[18] ;
+  wire \mprj_dat_o_core[19] ;
+  wire \mprj_dat_o_core[1] ;
+  wire \mprj_dat_o_core[20] ;
+  wire \mprj_dat_o_core[21] ;
+  wire \mprj_dat_o_core[22] ;
+  wire \mprj_dat_o_core[23] ;
+  wire \mprj_dat_o_core[24] ;
+  wire \mprj_dat_o_core[25] ;
+  wire \mprj_dat_o_core[26] ;
+  wire \mprj_dat_o_core[27] ;
+  wire \mprj_dat_o_core[28] ;
+  wire \mprj_dat_o_core[29] ;
+  wire \mprj_dat_o_core[2] ;
+  wire \mprj_dat_o_core[30] ;
+  wire \mprj_dat_o_core[31] ;
+  wire \mprj_dat_o_core[3] ;
+  wire \mprj_dat_o_core[4] ;
+  wire \mprj_dat_o_core[5] ;
+  wire \mprj_dat_o_core[6] ;
+  wire \mprj_dat_o_core[7] ;
+  wire \mprj_dat_o_core[8] ;
+  wire \mprj_dat_o_core[9] ;
+  wire \mprj_dat_o_user[0] ;
+  wire \mprj_dat_o_user[10] ;
+  wire \mprj_dat_o_user[11] ;
+  wire \mprj_dat_o_user[12] ;
+  wire \mprj_dat_o_user[13] ;
+  wire \mprj_dat_o_user[14] ;
+  wire \mprj_dat_o_user[15] ;
+  wire \mprj_dat_o_user[16] ;
+  wire \mprj_dat_o_user[17] ;
+  wire \mprj_dat_o_user[18] ;
+  wire \mprj_dat_o_user[19] ;
+  wire \mprj_dat_o_user[1] ;
+  wire \mprj_dat_o_user[20] ;
+  wire \mprj_dat_o_user[21] ;
+  wire \mprj_dat_o_user[22] ;
+  wire \mprj_dat_o_user[23] ;
+  wire \mprj_dat_o_user[24] ;
+  wire \mprj_dat_o_user[25] ;
+  wire \mprj_dat_o_user[26] ;
+  wire \mprj_dat_o_user[27] ;
+  wire \mprj_dat_o_user[28] ;
+  wire \mprj_dat_o_user[29] ;
+  wire \mprj_dat_o_user[2] ;
+  wire \mprj_dat_o_user[30] ;
+  wire \mprj_dat_o_user[31] ;
+  wire \mprj_dat_o_user[3] ;
+  wire \mprj_dat_o_user[4] ;
+  wire \mprj_dat_o_user[5] ;
+  wire \mprj_dat_o_user[6] ;
+  wire \mprj_dat_o_user[7] ;
+  wire \mprj_dat_o_user[8] ;
+  wire \mprj_dat_o_user[9] ;
+  wire mprj_iena_wb;
+  inout [37:0] mprj_io;
+  wire \mprj_io_analog_en[0] ;
+  wire \mprj_io_analog_en[10] ;
+  wire \mprj_io_analog_en[11] ;
+  wire \mprj_io_analog_en[12] ;
+  wire \mprj_io_analog_en[13] ;
+  wire \mprj_io_analog_en[14] ;
+  wire \mprj_io_analog_en[15] ;
+  wire \mprj_io_analog_en[16] ;
+  wire \mprj_io_analog_en[17] ;
+  wire \mprj_io_analog_en[18] ;
+  wire \mprj_io_analog_en[19] ;
+  wire \mprj_io_analog_en[1] ;
+  wire \mprj_io_analog_en[20] ;
+  wire \mprj_io_analog_en[21] ;
+  wire \mprj_io_analog_en[22] ;
+  wire \mprj_io_analog_en[23] ;
+  wire \mprj_io_analog_en[24] ;
+  wire \mprj_io_analog_en[25] ;
+  wire \mprj_io_analog_en[26] ;
+  wire \mprj_io_analog_en[2] ;
+  wire \mprj_io_analog_en[3] ;
+  wire \mprj_io_analog_en[4] ;
+  wire \mprj_io_analog_en[5] ;
+  wire \mprj_io_analog_en[6] ;
+  wire \mprj_io_analog_en[7] ;
+  wire \mprj_io_analog_en[8] ;
+  wire \mprj_io_analog_en[9] ;
+  wire \mprj_io_analog_pol[0] ;
+  wire \mprj_io_analog_pol[10] ;
+  wire \mprj_io_analog_pol[11] ;
+  wire \mprj_io_analog_pol[12] ;
+  wire \mprj_io_analog_pol[13] ;
+  wire \mprj_io_analog_pol[14] ;
+  wire \mprj_io_analog_pol[15] ;
+  wire \mprj_io_analog_pol[16] ;
+  wire \mprj_io_analog_pol[17] ;
+  wire \mprj_io_analog_pol[18] ;
+  wire \mprj_io_analog_pol[19] ;
+  wire \mprj_io_analog_pol[1] ;
+  wire \mprj_io_analog_pol[20] ;
+  wire \mprj_io_analog_pol[21] ;
+  wire \mprj_io_analog_pol[22] ;
+  wire \mprj_io_analog_pol[23] ;
+  wire \mprj_io_analog_pol[24] ;
+  wire \mprj_io_analog_pol[25] ;
+  wire \mprj_io_analog_pol[26] ;
+  wire \mprj_io_analog_pol[2] ;
+  wire \mprj_io_analog_pol[3] ;
+  wire \mprj_io_analog_pol[4] ;
+  wire \mprj_io_analog_pol[5] ;
+  wire \mprj_io_analog_pol[6] ;
+  wire \mprj_io_analog_pol[7] ;
+  wire \mprj_io_analog_pol[8] ;
+  wire \mprj_io_analog_pol[9] ;
+  wire \mprj_io_analog_sel[0] ;
+  wire \mprj_io_analog_sel[10] ;
+  wire \mprj_io_analog_sel[11] ;
+  wire \mprj_io_analog_sel[12] ;
+  wire \mprj_io_analog_sel[13] ;
+  wire \mprj_io_analog_sel[14] ;
+  wire \mprj_io_analog_sel[15] ;
+  wire \mprj_io_analog_sel[16] ;
+  wire \mprj_io_analog_sel[17] ;
+  wire \mprj_io_analog_sel[18] ;
+  wire \mprj_io_analog_sel[19] ;
+  wire \mprj_io_analog_sel[1] ;
+  wire \mprj_io_analog_sel[20] ;
+  wire \mprj_io_analog_sel[21] ;
+  wire \mprj_io_analog_sel[22] ;
+  wire \mprj_io_analog_sel[23] ;
+  wire \mprj_io_analog_sel[24] ;
+  wire \mprj_io_analog_sel[25] ;
+  wire \mprj_io_analog_sel[26] ;
+  wire \mprj_io_analog_sel[2] ;
+  wire \mprj_io_analog_sel[3] ;
+  wire \mprj_io_analog_sel[4] ;
+  wire \mprj_io_analog_sel[5] ;
+  wire \mprj_io_analog_sel[6] ;
+  wire \mprj_io_analog_sel[7] ;
+  wire \mprj_io_analog_sel[8] ;
+  wire \mprj_io_analog_sel[9] ;
+  wire \mprj_io_dm[0] ;
+  wire \mprj_io_dm[10] ;
+  wire \mprj_io_dm[11] ;
+  wire \mprj_io_dm[12] ;
+  wire \mprj_io_dm[13] ;
+  wire \mprj_io_dm[14] ;
+  wire \mprj_io_dm[15] ;
+  wire \mprj_io_dm[16] ;
+  wire \mprj_io_dm[17] ;
+  wire \mprj_io_dm[18] ;
+  wire \mprj_io_dm[19] ;
+  wire \mprj_io_dm[1] ;
+  wire \mprj_io_dm[20] ;
+  wire \mprj_io_dm[21] ;
+  wire \mprj_io_dm[22] ;
+  wire \mprj_io_dm[23] ;
+  wire \mprj_io_dm[24] ;
+  wire \mprj_io_dm[25] ;
+  wire \mprj_io_dm[26] ;
+  wire \mprj_io_dm[27] ;
+  wire \mprj_io_dm[28] ;
+  wire \mprj_io_dm[29] ;
+  wire \mprj_io_dm[2] ;
+  wire \mprj_io_dm[30] ;
+  wire \mprj_io_dm[31] ;
+  wire \mprj_io_dm[32] ;
+  wire \mprj_io_dm[33] ;
+  wire \mprj_io_dm[34] ;
+  wire \mprj_io_dm[35] ;
+  wire \mprj_io_dm[36] ;
+  wire \mprj_io_dm[37] ;
+  wire \mprj_io_dm[38] ;
+  wire \mprj_io_dm[39] ;
+  wire \mprj_io_dm[3] ;
+  wire \mprj_io_dm[40] ;
+  wire \mprj_io_dm[41] ;
+  wire \mprj_io_dm[42] ;
+  wire \mprj_io_dm[43] ;
+  wire \mprj_io_dm[44] ;
+  wire \mprj_io_dm[45] ;
+  wire \mprj_io_dm[46] ;
+  wire \mprj_io_dm[47] ;
+  wire \mprj_io_dm[48] ;
+  wire \mprj_io_dm[49] ;
+  wire \mprj_io_dm[4] ;
+  wire \mprj_io_dm[50] ;
+  wire \mprj_io_dm[51] ;
+  wire \mprj_io_dm[52] ;
+  wire \mprj_io_dm[53] ;
+  wire \mprj_io_dm[54] ;
+  wire \mprj_io_dm[55] ;
+  wire \mprj_io_dm[56] ;
+  wire \mprj_io_dm[57] ;
+  wire \mprj_io_dm[58] ;
+  wire \mprj_io_dm[59] ;
+  wire \mprj_io_dm[5] ;
+  wire \mprj_io_dm[60] ;
+  wire \mprj_io_dm[61] ;
+  wire \mprj_io_dm[62] ;
+  wire \mprj_io_dm[63] ;
+  wire \mprj_io_dm[64] ;
+  wire \mprj_io_dm[65] ;
+  wire \mprj_io_dm[66] ;
+  wire \mprj_io_dm[67] ;
+  wire \mprj_io_dm[68] ;
+  wire \mprj_io_dm[69] ;
+  wire \mprj_io_dm[6] ;
+  wire \mprj_io_dm[70] ;
+  wire \mprj_io_dm[71] ;
+  wire \mprj_io_dm[72] ;
+  wire \mprj_io_dm[73] ;
+  wire \mprj_io_dm[74] ;
+  wire \mprj_io_dm[75] ;
+  wire \mprj_io_dm[76] ;
+  wire \mprj_io_dm[77] ;
+  wire \mprj_io_dm[78] ;
+  wire \mprj_io_dm[79] ;
+  wire \mprj_io_dm[7] ;
+  wire \mprj_io_dm[80] ;
+  wire \mprj_io_dm[8] ;
+  wire \mprj_io_dm[9] ;
+  wire \mprj_io_holdover[0] ;
+  wire \mprj_io_holdover[10] ;
+  wire \mprj_io_holdover[11] ;
+  wire \mprj_io_holdover[12] ;
+  wire \mprj_io_holdover[13] ;
+  wire \mprj_io_holdover[14] ;
+  wire \mprj_io_holdover[15] ;
+  wire \mprj_io_holdover[16] ;
+  wire \mprj_io_holdover[17] ;
+  wire \mprj_io_holdover[18] ;
+  wire \mprj_io_holdover[19] ;
+  wire \mprj_io_holdover[1] ;
+  wire \mprj_io_holdover[20] ;
+  wire \mprj_io_holdover[21] ;
+  wire \mprj_io_holdover[22] ;
+  wire \mprj_io_holdover[23] ;
+  wire \mprj_io_holdover[24] ;
+  wire \mprj_io_holdover[25] ;
+  wire \mprj_io_holdover[26] ;
+  wire \mprj_io_holdover[2] ;
+  wire \mprj_io_holdover[3] ;
+  wire \mprj_io_holdover[4] ;
+  wire \mprj_io_holdover[5] ;
+  wire \mprj_io_holdover[6] ;
+  wire \mprj_io_holdover[7] ;
+  wire \mprj_io_holdover[8] ;
+  wire \mprj_io_holdover[9] ;
+  wire \mprj_io_ib_mode_sel[0] ;
+  wire \mprj_io_ib_mode_sel[10] ;
+  wire \mprj_io_ib_mode_sel[11] ;
+  wire \mprj_io_ib_mode_sel[12] ;
+  wire \mprj_io_ib_mode_sel[13] ;
+  wire \mprj_io_ib_mode_sel[14] ;
+  wire \mprj_io_ib_mode_sel[15] ;
+  wire \mprj_io_ib_mode_sel[16] ;
+  wire \mprj_io_ib_mode_sel[17] ;
+  wire \mprj_io_ib_mode_sel[18] ;
+  wire \mprj_io_ib_mode_sel[19] ;
+  wire \mprj_io_ib_mode_sel[1] ;
+  wire \mprj_io_ib_mode_sel[20] ;
+  wire \mprj_io_ib_mode_sel[21] ;
+  wire \mprj_io_ib_mode_sel[22] ;
+  wire \mprj_io_ib_mode_sel[23] ;
+  wire \mprj_io_ib_mode_sel[24] ;
+  wire \mprj_io_ib_mode_sel[25] ;
+  wire \mprj_io_ib_mode_sel[26] ;
+  wire \mprj_io_ib_mode_sel[2] ;
+  wire \mprj_io_ib_mode_sel[3] ;
+  wire \mprj_io_ib_mode_sel[4] ;
+  wire \mprj_io_ib_mode_sel[5] ;
+  wire \mprj_io_ib_mode_sel[6] ;
+  wire \mprj_io_ib_mode_sel[7] ;
+  wire \mprj_io_ib_mode_sel[8] ;
+  wire \mprj_io_ib_mode_sel[9] ;
+  wire \mprj_io_in[0] ;
+  wire \mprj_io_in[10] ;
+  wire \mprj_io_in[11] ;
+  wire \mprj_io_in[12] ;
+  wire \mprj_io_in[13] ;
+  wire \mprj_io_in[14] ;
+  wire \mprj_io_in[15] ;
+  wire \mprj_io_in[16] ;
+  wire \mprj_io_in[17] ;
+  wire \mprj_io_in[18] ;
+  wire \mprj_io_in[19] ;
+  wire \mprj_io_in[1] ;
+  wire \mprj_io_in[20] ;
+  wire \mprj_io_in[21] ;
+  wire \mprj_io_in[22] ;
+  wire \mprj_io_in[23] ;
+  wire \mprj_io_in[24] ;
+  wire \mprj_io_in[25] ;
+  wire \mprj_io_in[26] ;
+  wire \mprj_io_in[2] ;
+  wire \mprj_io_in[3] ;
+  wire \mprj_io_in[4] ;
+  wire \mprj_io_in[5] ;
+  wire \mprj_io_in[6] ;
+  wire \mprj_io_in[7] ;
+  wire \mprj_io_in[8] ;
+  wire \mprj_io_in[9] ;
+  wire \mprj_io_in_3v3[0] ;
+  wire \mprj_io_in_3v3[10] ;
+  wire \mprj_io_in_3v3[11] ;
+  wire \mprj_io_in_3v3[12] ;
+  wire \mprj_io_in_3v3[13] ;
+  wire \mprj_io_in_3v3[14] ;
+  wire \mprj_io_in_3v3[15] ;
+  wire \mprj_io_in_3v3[16] ;
+  wire \mprj_io_in_3v3[17] ;
+  wire \mprj_io_in_3v3[18] ;
+  wire \mprj_io_in_3v3[19] ;
+  wire \mprj_io_in_3v3[1] ;
+  wire \mprj_io_in_3v3[20] ;
+  wire \mprj_io_in_3v3[21] ;
+  wire \mprj_io_in_3v3[22] ;
+  wire \mprj_io_in_3v3[23] ;
+  wire \mprj_io_in_3v3[24] ;
+  wire \mprj_io_in_3v3[25] ;
+  wire \mprj_io_in_3v3[26] ;
+  wire \mprj_io_in_3v3[2] ;
+  wire \mprj_io_in_3v3[3] ;
+  wire \mprj_io_in_3v3[4] ;
+  wire \mprj_io_in_3v3[5] ;
+  wire \mprj_io_in_3v3[6] ;
+  wire \mprj_io_in_3v3[7] ;
+  wire \mprj_io_in_3v3[8] ;
+  wire \mprj_io_in_3v3[9] ;
+  wire \mprj_io_inp_dis[0] ;
+  wire \mprj_io_inp_dis[10] ;
+  wire \mprj_io_inp_dis[11] ;
+  wire \mprj_io_inp_dis[12] ;
+  wire \mprj_io_inp_dis[13] ;
+  wire \mprj_io_inp_dis[14] ;
+  wire \mprj_io_inp_dis[15] ;
+  wire \mprj_io_inp_dis[16] ;
+  wire \mprj_io_inp_dis[17] ;
+  wire \mprj_io_inp_dis[18] ;
+  wire \mprj_io_inp_dis[19] ;
+  wire \mprj_io_inp_dis[1] ;
+  wire \mprj_io_inp_dis[20] ;
+  wire \mprj_io_inp_dis[21] ;
+  wire \mprj_io_inp_dis[22] ;
+  wire \mprj_io_inp_dis[23] ;
+  wire \mprj_io_inp_dis[24] ;
+  wire \mprj_io_inp_dis[25] ;
+  wire \mprj_io_inp_dis[26] ;
+  wire \mprj_io_inp_dis[2] ;
+  wire \mprj_io_inp_dis[3] ;
+  wire \mprj_io_inp_dis[4] ;
+  wire \mprj_io_inp_dis[5] ;
+  wire \mprj_io_inp_dis[6] ;
+  wire \mprj_io_inp_dis[7] ;
+  wire \mprj_io_inp_dis[8] ;
+  wire \mprj_io_inp_dis[9] ;
+  wire mprj_io_loader_clock;
+  wire mprj_io_loader_data_1;
+  wire mprj_io_loader_data_2;
+  wire mprj_io_loader_resetn;
+  wire mprj_io_loader_strobe;
+  wire \mprj_io_oeb[0] ;
+  wire \mprj_io_oeb[10] ;
+  wire \mprj_io_oeb[11] ;
+  wire \mprj_io_oeb[12] ;
+  wire \mprj_io_oeb[13] ;
+  wire \mprj_io_oeb[14] ;
+  wire \mprj_io_oeb[15] ;
+  wire \mprj_io_oeb[16] ;
+  wire \mprj_io_oeb[17] ;
+  wire \mprj_io_oeb[18] ;
+  wire \mprj_io_oeb[19] ;
+  wire \mprj_io_oeb[1] ;
+  wire \mprj_io_oeb[20] ;
+  wire \mprj_io_oeb[21] ;
+  wire \mprj_io_oeb[22] ;
+  wire \mprj_io_oeb[23] ;
+  wire \mprj_io_oeb[24] ;
+  wire \mprj_io_oeb[25] ;
+  wire \mprj_io_oeb[26] ;
+  wire \mprj_io_oeb[2] ;
+  wire \mprj_io_oeb[3] ;
+  wire \mprj_io_oeb[4] ;
+  wire \mprj_io_oeb[5] ;
+  wire \mprj_io_oeb[6] ;
+  wire \mprj_io_oeb[7] ;
+  wire \mprj_io_oeb[8] ;
+  wire \mprj_io_oeb[9] ;
+  wire \mprj_io_out[0] ;
+  wire \mprj_io_out[10] ;
+  wire \mprj_io_out[11] ;
+  wire \mprj_io_out[12] ;
+  wire \mprj_io_out[13] ;
+  wire \mprj_io_out[14] ;
+  wire \mprj_io_out[15] ;
+  wire \mprj_io_out[16] ;
+  wire \mprj_io_out[17] ;
+  wire \mprj_io_out[18] ;
+  wire \mprj_io_out[19] ;
+  wire \mprj_io_out[1] ;
+  wire \mprj_io_out[20] ;
+  wire \mprj_io_out[21] ;
+  wire \mprj_io_out[22] ;
+  wire \mprj_io_out[23] ;
+  wire \mprj_io_out[24] ;
+  wire \mprj_io_out[25] ;
+  wire \mprj_io_out[26] ;
+  wire \mprj_io_out[2] ;
+  wire \mprj_io_out[3] ;
+  wire \mprj_io_out[4] ;
+  wire \mprj_io_out[5] ;
+  wire \mprj_io_out[6] ;
+  wire \mprj_io_out[7] ;
+  wire \mprj_io_out[8] ;
+  wire \mprj_io_out[9] ;
+  wire \mprj_io_slow_sel[0] ;
+  wire \mprj_io_slow_sel[10] ;
+  wire \mprj_io_slow_sel[11] ;
+  wire \mprj_io_slow_sel[12] ;
+  wire \mprj_io_slow_sel[13] ;
+  wire \mprj_io_slow_sel[14] ;
+  wire \mprj_io_slow_sel[15] ;
+  wire \mprj_io_slow_sel[16] ;
+  wire \mprj_io_slow_sel[17] ;
+  wire \mprj_io_slow_sel[18] ;
+  wire \mprj_io_slow_sel[19] ;
+  wire \mprj_io_slow_sel[1] ;
+  wire \mprj_io_slow_sel[20] ;
+  wire \mprj_io_slow_sel[21] ;
+  wire \mprj_io_slow_sel[22] ;
+  wire \mprj_io_slow_sel[23] ;
+  wire \mprj_io_slow_sel[24] ;
+  wire \mprj_io_slow_sel[25] ;
+  wire \mprj_io_slow_sel[26] ;
+  wire \mprj_io_slow_sel[2] ;
+  wire \mprj_io_slow_sel[3] ;
+  wire \mprj_io_slow_sel[4] ;
+  wire \mprj_io_slow_sel[5] ;
+  wire \mprj_io_slow_sel[6] ;
+  wire \mprj_io_slow_sel[7] ;
+  wire \mprj_io_slow_sel[8] ;
+  wire \mprj_io_slow_sel[9] ;
+  wire \mprj_io_vtrip_sel[0] ;
+  wire \mprj_io_vtrip_sel[10] ;
+  wire \mprj_io_vtrip_sel[11] ;
+  wire \mprj_io_vtrip_sel[12] ;
+  wire \mprj_io_vtrip_sel[13] ;
+  wire \mprj_io_vtrip_sel[14] ;
+  wire \mprj_io_vtrip_sel[15] ;
+  wire \mprj_io_vtrip_sel[16] ;
+  wire \mprj_io_vtrip_sel[17] ;
+  wire \mprj_io_vtrip_sel[18] ;
+  wire \mprj_io_vtrip_sel[19] ;
+  wire \mprj_io_vtrip_sel[1] ;
+  wire \mprj_io_vtrip_sel[20] ;
+  wire \mprj_io_vtrip_sel[21] ;
+  wire \mprj_io_vtrip_sel[22] ;
+  wire \mprj_io_vtrip_sel[23] ;
+  wire \mprj_io_vtrip_sel[24] ;
+  wire \mprj_io_vtrip_sel[25] ;
+  wire \mprj_io_vtrip_sel[26] ;
+  wire \mprj_io_vtrip_sel[2] ;
+  wire \mprj_io_vtrip_sel[3] ;
+  wire \mprj_io_vtrip_sel[4] ;
+  wire \mprj_io_vtrip_sel[5] ;
+  wire \mprj_io_vtrip_sel[6] ;
+  wire \mprj_io_vtrip_sel[7] ;
+  wire \mprj_io_vtrip_sel[8] ;
+  wire \mprj_io_vtrip_sel[9] ;
+  wire mprj_reset;
+  wire \mprj_sel_o_core[0] ;
+  wire \mprj_sel_o_core[1] ;
+  wire \mprj_sel_o_core[2] ;
+  wire \mprj_sel_o_core[3] ;
+  wire \mprj_sel_o_user[0] ;
+  wire \mprj_sel_o_user[1] ;
+  wire \mprj_sel_o_user[2] ;
+  wire \mprj_sel_o_user[3] ;
+  wire mprj_stb_o_core;
+  wire mprj_stb_o_user;
+  wire mprj_vcc_pwrgood;
+  wire mprj_vdd_pwrgood;
+  wire mprj_we_o_core;
+  wire mprj_we_o_user;
+  wire \one_loop1[0] ;
+  wire \one_loop1[10] ;
+  wire \one_loop1[11] ;
+  wire \one_loop1[1] ;
+  wire \one_loop1[2] ;
+  wire \one_loop1[3] ;
+  wire \one_loop1[4] ;
+  wire \one_loop1[5] ;
+  wire \one_loop1[6] ;
+  wire \one_loop1[7] ;
+  wire \one_loop1[8] ;
+  wire \one_loop1[9] ;
+  wire \one_loop2[0] ;
+  wire \one_loop2[1] ;
+  wire \one_loop2[2] ;
+  wire \one_loop2[3] ;
+  wire \one_loop2[4] ;
+  wire \one_loop2[5] ;
+  wire \one_loop2[6] ;
+  wire \one_loop2[7] ;
+  wire \one_loop2[8] ;
+  wire \one_loop2[9] ;
+  wire pll_clk;
+  wire pll_clk90;
+  wire por_l;
+  wire porb_h;
+  wire porb_l;
+  wire \pwr_ctrl_nc[0] ;
+  wire \pwr_ctrl_nc[1] ;
+  wire \pwr_ctrl_nc[2] ;
+  wire \pwr_ctrl_nc[3] ;
+  wire qspi_enabled;
+  input resetb;
+  wire rstb_h;
+  wire rstb_l;
+  wire sdo_out;
+  wire sdo_outenb;
+  wire ser_rx;
+  wire ser_tx;
+  wire spi_csb;
+  wire spi_enabled;
+  wire \spi_pll90_sel[0] ;
+  wire \spi_pll90_sel[1] ;
+  wire \spi_pll90_sel[2] ;
+  wire spi_pll_dco_ena;
+  wire \spi_pll_div[0] ;
+  wire \spi_pll_div[1] ;
+  wire \spi_pll_div[2] ;
+  wire \spi_pll_div[3] ;
+  wire \spi_pll_div[4] ;
+  wire spi_pll_ena;
+  wire \spi_pll_sel[0] ;
+  wire \spi_pll_sel[1] ;
+  wire \spi_pll_sel[2] ;
+  wire \spi_pll_trim[0] ;
+  wire \spi_pll_trim[10] ;
+  wire \spi_pll_trim[11] ;
+  wire \spi_pll_trim[12] ;
+  wire \spi_pll_trim[13] ;
+  wire \spi_pll_trim[14] ;
+  wire \spi_pll_trim[15] ;
+  wire \spi_pll_trim[16] ;
+  wire \spi_pll_trim[17] ;
+  wire \spi_pll_trim[18] ;
+  wire \spi_pll_trim[19] ;
+  wire \spi_pll_trim[1] ;
+  wire \spi_pll_trim[20] ;
+  wire \spi_pll_trim[21] ;
+  wire \spi_pll_trim[22] ;
+  wire \spi_pll_trim[23] ;
+  wire \spi_pll_trim[24] ;
+  wire \spi_pll_trim[25] ;
+  wire \spi_pll_trim[2] ;
+  wire \spi_pll_trim[3] ;
+  wire \spi_pll_trim[4] ;
+  wire \spi_pll_trim[5] ;
+  wire \spi_pll_trim[6] ;
+  wire \spi_pll_trim[7] ;
+  wire \spi_pll_trim[8] ;
+  wire \spi_pll_trim[9] ;
+  wire \spi_ro_config_core[0] ;
+  wire \spi_ro_config_core[1] ;
+  wire \spi_ro_config_core[2] ;
+  wire \spi_ro_config_core[3] ;
+  wire \spi_ro_config_core[4] ;
+  wire \spi_ro_config_core[5] ;
+  wire \spi_ro_config_core[6] ;
+  wire \spi_ro_config_core[7] ;
+  wire spi_sck;
+  wire spi_sdi;
+  wire spi_sdo;
+  wire spi_sdoenb;
+  wire trap;
+  wire uart_enabled;
+  wire \user_analog[0] ;
+  wire \user_analog[10] ;
+  wire \user_analog[1] ;
+  wire \user_analog[2] ;
+  wire \user_analog[3] ;
+  wire \user_analog[4] ;
+  wire \user_analog[5] ;
+  wire \user_analog[6] ;
+  wire \user_analog[7] ;
+  wire \user_analog[8] ;
+  wire \user_analog[9] ;
+  wire \user_clamp_high[0] ;
+  wire \user_clamp_high[1] ;
+  wire \user_clamp_high[2] ;
+  wire \user_clamp_low[0] ;
+  wire \user_clamp_low[1] ;
+  wire \user_clamp_low[2] ;
+  wire \user_gpio_analog[0] ;
+  wire \user_gpio_analog[10] ;
+  wire \user_gpio_analog[11] ;
+  wire \user_gpio_analog[12] ;
+  wire \user_gpio_analog[13] ;
+  wire \user_gpio_analog[14] ;
+  wire \user_gpio_analog[15] ;
+  wire \user_gpio_analog[16] ;
+  wire \user_gpio_analog[17] ;
+  wire \user_gpio_analog[1] ;
+  wire \user_gpio_analog[2] ;
+  wire \user_gpio_analog[3] ;
+  wire \user_gpio_analog[4] ;
+  wire \user_gpio_analog[5] ;
+  wire \user_gpio_analog[6] ;
+  wire \user_gpio_analog[7] ;
+  wire \user_gpio_analog[8] ;
+  wire \user_gpio_analog[9] ;
+  wire \user_gpio_noesd[0] ;
+  wire \user_gpio_noesd[10] ;
+  wire \user_gpio_noesd[11] ;
+  wire \user_gpio_noesd[12] ;
+  wire \user_gpio_noesd[13] ;
+  wire \user_gpio_noesd[14] ;
+  wire \user_gpio_noesd[15] ;
+  wire \user_gpio_noesd[16] ;
+  wire \user_gpio_noesd[17] ;
+  wire \user_gpio_noesd[1] ;
+  wire \user_gpio_noesd[2] ;
+  wire \user_gpio_noesd[3] ;
+  wire \user_gpio_noesd[4] ;
+  wire \user_gpio_noesd[5] ;
+  wire \user_gpio_noesd[6] ;
+  wire \user_gpio_noesd[7] ;
+  wire \user_gpio_noesd[8] ;
+  wire \user_gpio_noesd[9] ;
+  wire \user_io_in[0] ;
+  wire \user_io_in[10] ;
+  wire \user_io_in[11] ;
+  wire \user_io_in[12] ;
+  wire \user_io_in[13] ;
+  wire \user_io_in[14] ;
+  wire \user_io_in[15] ;
+  wire \user_io_in[16] ;
+  wire \user_io_in[17] ;
+  wire \user_io_in[18] ;
+  wire \user_io_in[19] ;
+  wire \user_io_in[1] ;
+  wire \user_io_in[20] ;
+  wire \user_io_in[21] ;
+  wire \user_io_in[22] ;
+  wire \user_io_in[23] ;
+  wire \user_io_in[24] ;
+  wire \user_io_in[25] ;
+  wire \user_io_in[26] ;
+  wire \user_io_in[2] ;
+  wire \user_io_in[3] ;
+  wire \user_io_in[4] ;
+  wire \user_io_in[5] ;
+  wire \user_io_in[6] ;
+  wire \user_io_in[7] ;
+  wire \user_io_in[8] ;
+  wire \user_io_in[9] ;
+  wire \user_io_in_3v3[0] ;
+  wire \user_io_in_3v3[10] ;
+  wire \user_io_in_3v3[11] ;
+  wire \user_io_in_3v3[12] ;
+  wire \user_io_in_3v3[13] ;
+  wire \user_io_in_3v3[14] ;
+  wire \user_io_in_3v3[15] ;
+  wire \user_io_in_3v3[16] ;
+  wire \user_io_in_3v3[17] ;
+  wire \user_io_in_3v3[18] ;
+  wire \user_io_in_3v3[19] ;
+  wire \user_io_in_3v3[1] ;
+  wire \user_io_in_3v3[20] ;
+  wire \user_io_in_3v3[21] ;
+  wire \user_io_in_3v3[22] ;
+  wire \user_io_in_3v3[23] ;
+  wire \user_io_in_3v3[24] ;
+  wire \user_io_in_3v3[25] ;
+  wire \user_io_in_3v3[26] ;
+  wire \user_io_in_3v3[2] ;
+  wire \user_io_in_3v3[3] ;
+  wire \user_io_in_3v3[4] ;
+  wire \user_io_in_3v3[5] ;
+  wire \user_io_in_3v3[6] ;
+  wire \user_io_in_3v3[7] ;
+  wire \user_io_in_3v3[8] ;
+  wire \user_io_in_3v3[9] ;
+  wire \user_io_oeb[0] ;
+  wire \user_io_oeb[10] ;
+  wire \user_io_oeb[11] ;
+  wire \user_io_oeb[12] ;
+  wire \user_io_oeb[13] ;
+  wire \user_io_oeb[14] ;
+  wire \user_io_oeb[15] ;
+  wire \user_io_oeb[16] ;
+  wire \user_io_oeb[17] ;
+  wire \user_io_oeb[18] ;
+  wire \user_io_oeb[19] ;
+  wire \user_io_oeb[1] ;
+  wire \user_io_oeb[20] ;
+  wire \user_io_oeb[21] ;
+  wire \user_io_oeb[22] ;
+  wire \user_io_oeb[23] ;
+  wire \user_io_oeb[24] ;
+  wire \user_io_oeb[25] ;
+  wire \user_io_oeb[26] ;
+  wire \user_io_oeb[2] ;
+  wire \user_io_oeb[3] ;
+  wire \user_io_oeb[4] ;
+  wire \user_io_oeb[5] ;
+  wire \user_io_oeb[6] ;
+  wire \user_io_oeb[7] ;
+  wire \user_io_oeb[8] ;
+  wire \user_io_oeb[9] ;
+  wire \user_io_out[0] ;
+  wire \user_io_out[10] ;
+  wire \user_io_out[11] ;
+  wire \user_io_out[12] ;
+  wire \user_io_out[13] ;
+  wire \user_io_out[14] ;
+  wire \user_io_out[15] ;
+  wire \user_io_out[16] ;
+  wire \user_io_out[17] ;
+  wire \user_io_out[18] ;
+  wire \user_io_out[19] ;
+  wire \user_io_out[1] ;
+  wire \user_io_out[20] ;
+  wire \user_io_out[21] ;
+  wire \user_io_out[22] ;
+  wire \user_io_out[23] ;
+  wire \user_io_out[24] ;
+  wire \user_io_out[25] ;
+  wire \user_io_out[26] ;
+  wire \user_io_out[2] ;
+  wire \user_io_out[3] ;
+  wire \user_io_out[4] ;
+  wire \user_io_out[5] ;
+  wire \user_io_out[6] ;
+  wire \user_io_out[7] ;
+  wire \user_io_out[8] ;
+  wire \user_io_out[9] ;
+  wire \user_irq[0] ;
+  wire \user_irq[1] ;
+  wire \user_irq[2] ;
+  wire \user_irq_core[0] ;
+  wire \user_irq_core[1] ;
+  wire \user_irq_core[2] ;
+  wire \user_irq_ena[0] ;
+  wire \user_irq_ena[1] ;
+  wire \user_irq_ena[2] ;
+  inout vccd;
+  inout vccd1;
+  wire vccd1_core;
+  inout vccd2;
+  wire vccd2_core;
+  wire vccd_core;
+  inout vdda;
+  inout vdda1;
+  inout vdda1_2;
+  wire vdda1_core;
+  inout vdda2;
+  wire vdda2_core;
+  wire vdda_core;
+  inout vddio;
+  inout vddio_2;
+  wire vddio_core;
+  inout vssa;
+  inout vssa1;
+  inout vssa1_2;
+  wire vssa1_core;
+  inout vssa2;
+  wire vssa2_core;
+  wire vssa_core;
+  inout vssd;
+  inout vssd1;
+  wire vssd1_core;
+  inout vssd2;
+  wire vssd2_core;
+  wire vssd_core;
+  inout vssio;
+  inout vssio_2;
+  wire vssio_core;
+  caravel_clocking \clocking  (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .core_clk(caravel_clk),
+    .ext_clk(clock_core),
+    .ext_clk_sel(ext_clk_sel),
+    .ext_reset(ext_reset),
+    .pll_clk(pll_clk),
+    .pll_clk90(pll_clk90),
+    .resetb(rstb_l),
+    .resetb_sync(caravel_rstn),
+    .sel({ \spi_pll_sel[2] , \spi_pll_sel[1] , \spi_pll_sel[0]  }),
+    .sel2({ \spi_pll90_sel[2] , \spi_pll90_sel[1] , \spi_pll90_sel[0]  }),
+    .user_clk(caravel_clk2)
+  );
+  gpio_defaults_block_1803 gpio_defaults_block_0 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0]  })
+  );
+  gpio_defaults_block_1803 gpio_defaults_block_1 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_10 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_11 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_12 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_13 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_14 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182]  })
+  );
+  gpio_defaults_block_0403 gpio_defaults_block_2 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26]  })
+  );
+  gpio_defaults_block_0403 gpio_defaults_block_3 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39]  })
+  );
+  gpio_defaults_block_0403 gpio_defaults_block_4 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_26 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_27 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_28 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_29 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_30 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_31 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_32 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_33 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_34 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_35 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_36 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_37 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_5 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_6 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_7 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_8 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_9 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117]  })
+  );
+  gpio_control_block \gpio_control_bidir_1[0]  (
+    .gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0]  }),
+    .mgmt_gpio_in(\mgmt_io_in[0] ),
+    .mgmt_gpio_oeb(jtag_outenb),
+    .mgmt_gpio_out(jtag_out),
+    .one(),
+    .pad_gpio_ana_en(\mprj_io_analog_en[0] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[0] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[0] ),
+    .pad_gpio_dm({ \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[0] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[0] ),
+    .pad_gpio_in(\mprj_io_in[0] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[0] ),
+    .pad_gpio_out(\mprj_io_out[0] ),
+    .pad_gpio_outenb(\mprj_io_oeb[0] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[0] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[0] ),
+    .resetn(\gpio_resetn_1_shifted[0] ),
+    .resetn_out(\gpio_resetn_1[0] ),
+    .serial_clock(\gpio_clock_1_shifted[0] ),
+    .serial_clock_out(\gpio_clock_1[0] ),
+    .serial_data_in(\gpio_serial_link_1_shifted[0] ),
+    .serial_data_out(\gpio_serial_link_1[0] ),
+    .serial_load(\gpio_load_1_shifted[0] ),
+    .serial_load_out(\gpio_load_1[0] ),
+    .user_gpio_in(\user_io_in[0] ),
+    .user_gpio_oeb(\user_io_oeb[0] ),
+    .user_gpio_out(\user_io_out[0] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_1[1]  (
+    .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13]  }),
+    .mgmt_gpio_in(\mgmt_io_in[1] ),
+    .mgmt_gpio_oeb(sdo_outenb),
+    .mgmt_gpio_out(sdo_out),
+    .one(),
+    .pad_gpio_ana_en(\mprj_io_analog_en[1] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[1] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[1] ),
+    .pad_gpio_dm({ \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[1] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[1] ),
+    .pad_gpio_in(\mprj_io_in[1] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[1] ),
+    .pad_gpio_out(\mprj_io_out[1] ),
+    .pad_gpio_outenb(\mprj_io_oeb[1] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[1] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[1] ),
+    .resetn(\gpio_resetn_1[0] ),
+    .resetn_out(\gpio_resetn_1[1] ),
+    .serial_clock(\gpio_clock_1[0] ),
+    .serial_clock_out(\gpio_clock_1[1] ),
+    .serial_data_in(\gpio_serial_link_1[0] ),
+    .serial_data_out(\gpio_serial_link_1[1] ),
+    .serial_load(\gpio_load_1[0] ),
+    .serial_load_out(\gpio_load_1[1] ),
+    .user_gpio_in(\user_io_in[1] ),
+    .user_gpio_oeb(\user_io_oeb[1] ),
+    .user_gpio_out(\user_io_out[1] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_2[0]  (
+    .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312]  }),
+    .mgmt_gpio_in(\mgmt_io_in[35] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[2] ),
+    .mgmt_gpio_out(\mgmt_io_out[2] ),
+    .one(),
+    .pad_gpio_ana_en(\mprj_io_analog_en[24] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[24] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[24] ),
+    .pad_gpio_dm({ \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[24] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[24] ),
+    .pad_gpio_in(\mprj_io_in[24] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[24] ),
+    .pad_gpio_out(\mprj_io_out[24] ),
+    .pad_gpio_outenb(\mprj_io_oeb[24] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[24] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[24] ),
+    .resetn(\gpio_resetn_2[11] ),
+    .resetn_out(\gpio_resetn_2[10] ),
+    .serial_clock(\gpio_clock_2[11] ),
+    .serial_clock_out(\gpio_clock_2[10] ),
+    .serial_data_in(\gpio_serial_link_2[11] ),
+    .serial_data_out(\gpio_serial_link_2[10] ),
+    .serial_load(\gpio_load_2[11] ),
+    .serial_load_out(\gpio_load_2[10] ),
+    .user_gpio_in(\user_io_in[24] ),
+    .user_gpio_oeb(\user_io_oeb[24] ),
+    .user_gpio_out(\user_io_out[24] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_2[1]  (
+    .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325]  }),
+    .mgmt_gpio_in(\mgmt_io_in[36] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[3] ),
+    .mgmt_gpio_out(\mgmt_io_out[3] ),
+    .one(),
+    .pad_gpio_ana_en(\mprj_io_analog_en[25] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[25] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[25] ),
+    .pad_gpio_dm({ \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[25] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[25] ),
+    .pad_gpio_in(\mprj_io_in[25] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[25] ),
+    .pad_gpio_out(\mprj_io_out[25] ),
+    .pad_gpio_outenb(\mprj_io_oeb[25] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[25] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[25] ),
+    .resetn(\gpio_resetn_2[12] ),
+    .resetn_out(\gpio_resetn_2[11] ),
+    .serial_clock(\gpio_clock_2[12] ),
+    .serial_clock_out(\gpio_clock_2[11] ),
+    .serial_data_in(\gpio_serial_link_2[12] ),
+    .serial_data_out(\gpio_serial_link_2[11] ),
+    .serial_load(\gpio_load_2[12] ),
+    .serial_load_out(\gpio_load_2[11] ),
+    .user_gpio_in(\user_io_in[25] ),
+    .user_gpio_oeb(\user_io_oeb[25] ),
+    .user_gpio_out(\user_io_out[25] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_2[2]  (
+    .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338]  }),
+    .mgmt_gpio_in(\mgmt_io_in[37] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[4] ),
+    .mgmt_gpio_out(\mgmt_io_out[4] ),
+    .one(),
+    .pad_gpio_ana_en(\mprj_io_analog_en[26] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[26] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[26] ),
+    .pad_gpio_dm({ \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[26] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[26] ),
+    .pad_gpio_in(\mprj_io_in[26] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[26] ),
+    .pad_gpio_out(\mprj_io_out[26] ),
+    .pad_gpio_outenb(\mprj_io_oeb[26] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[26] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[26] ),
+    .resetn(\gpio_resetn_2_shifted[12] ),
+    .resetn_out(\gpio_resetn_2[12] ),
+    .serial_clock(\gpio_clock_2_shifted[12] ),
+    .serial_clock_out(\gpio_clock_2[12] ),
+    .serial_data_in(\gpio_serial_link_2_shifted[12] ),
+    .serial_data_out(\gpio_serial_link_2[12] ),
+    .serial_load(\gpio_load_2_shifted[12] ),
+    .serial_load_out(\gpio_load_2[12] ),
+    .user_gpio_in(\user_io_in[26] ),
+    .user_gpio_oeb(\user_io_oeb[26] ),
+    .user_gpio_out(\user_io_out[26] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[0]  (
+    .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104]  }),
+    .mgmt_gpio_in(\mgmt_io_in[8] ),
+    .mgmt_gpio_oeb(\one_loop1[6] ),
+    .mgmt_gpio_out(\mgmt_io_in[8] ),
+    .one(\one_loop1[6] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[8] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[8] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[8] ),
+    .pad_gpio_dm({ \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[8] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[8] ),
+    .pad_gpio_in(\mprj_io_in[8] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[8] ),
+    .pad_gpio_out(\mprj_io_out[8] ),
+    .pad_gpio_outenb(\mprj_io_oeb[8] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[8] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[8] ),
+    .resetn(\gpio_resetn_1[7] ),
+    .resetn_out(\gpio_resetn_1[8] ),
+    .serial_clock(\gpio_clock_1[7] ),
+    .serial_clock_out(\gpio_clock_1[8] ),
+    .serial_data_in(\gpio_serial_link_1[7] ),
+    .serial_data_out(\gpio_serial_link_1[8] ),
+    .serial_load(\gpio_load_1[7] ),
+    .serial_load_out(\gpio_load_1[8] ),
+    .user_gpio_in(\user_io_in[8] ),
+    .user_gpio_oeb(\user_io_oeb[8] ),
+    .user_gpio_out(\user_io_out[8] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[1]  (
+    .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117]  }),
+    .mgmt_gpio_in(\mgmt_io_in[9] ),
+    .mgmt_gpio_oeb(\one_loop1[7] ),
+    .mgmt_gpio_out(\mgmt_io_in[9] ),
+    .one(\one_loop1[7] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[9] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[9] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[9] ),
+    .pad_gpio_dm({ \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[9] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[9] ),
+    .pad_gpio_in(\mprj_io_in[9] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[9] ),
+    .pad_gpio_out(\mprj_io_out[9] ),
+    .pad_gpio_outenb(\mprj_io_oeb[9] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[9] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[9] ),
+    .resetn(\gpio_resetn_1[8] ),
+    .resetn_out(\gpio_resetn_1[9] ),
+    .serial_clock(\gpio_clock_1[8] ),
+    .serial_clock_out(\gpio_clock_1[9] ),
+    .serial_data_in(\gpio_serial_link_1[8] ),
+    .serial_data_out(\gpio_serial_link_1[9] ),
+    .serial_load(\gpio_load_1[8] ),
+    .serial_load_out(\gpio_load_1[9] ),
+    .user_gpio_in(\user_io_in[9] ),
+    .user_gpio_oeb(\user_io_oeb[9] ),
+    .user_gpio_out(\user_io_out[9] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[2]  (
+    .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130]  }),
+    .mgmt_gpio_in(\mgmt_io_in[10] ),
+    .mgmt_gpio_oeb(\one_loop1[8] ),
+    .mgmt_gpio_out(\mgmt_io_in[10] ),
+    .one(\one_loop1[8] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[10] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[10] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[10] ),
+    .pad_gpio_dm({ \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[10] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[10] ),
+    .pad_gpio_in(\mprj_io_in[10] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[10] ),
+    .pad_gpio_out(\mprj_io_out[10] ),
+    .pad_gpio_outenb(\mprj_io_oeb[10] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[10] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[10] ),
+    .resetn(\gpio_resetn_1[9] ),
+    .resetn_out(\gpio_resetn_1[10] ),
+    .serial_clock(\gpio_clock_1[9] ),
+    .serial_clock_out(\gpio_clock_1[10] ),
+    .serial_data_in(\gpio_serial_link_1[9] ),
+    .serial_data_out(\gpio_serial_link_1[10] ),
+    .serial_load(\gpio_load_1[9] ),
+    .serial_load_out(\gpio_load_1[10] ),
+    .user_gpio_in(\user_io_in[10] ),
+    .user_gpio_oeb(\user_io_oeb[10] ),
+    .user_gpio_out(\user_io_out[10] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[3]  (
+    .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143]  }),
+    .mgmt_gpio_in(\mgmt_io_in[11] ),
+    .mgmt_gpio_oeb(\one_loop1[9] ),
+    .mgmt_gpio_out(\mgmt_io_in[11] ),
+    .one(\one_loop1[9] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[11] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[11] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[11] ),
+    .pad_gpio_dm({ \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[11] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[11] ),
+    .pad_gpio_in(\mprj_io_in[11] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[11] ),
+    .pad_gpio_out(\mprj_io_out[11] ),
+    .pad_gpio_outenb(\mprj_io_oeb[11] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[11] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[11] ),
+    .resetn(\gpio_resetn_1[10] ),
+    .resetn_out(\gpio_resetn_1[11] ),
+    .serial_clock(\gpio_clock_1[10] ),
+    .serial_clock_out(\gpio_clock_1[11] ),
+    .serial_data_in(\gpio_serial_link_1[10] ),
+    .serial_data_out(\gpio_serial_link_1[11] ),
+    .serial_load(\gpio_load_1[10] ),
+    .serial_load_out(\gpio_load_1[11] ),
+    .user_gpio_in(\user_io_in[11] ),
+    .user_gpio_oeb(\user_io_oeb[11] ),
+    .user_gpio_out(\user_io_out[11] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[4]  (
+    .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156]  }),
+    .mgmt_gpio_in(\mgmt_io_in[12] ),
+    .mgmt_gpio_oeb(\one_loop1[10] ),
+    .mgmt_gpio_out(\mgmt_io_in[12] ),
+    .one(\one_loop1[10] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[12] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[12] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[12] ),
+    .pad_gpio_dm({ \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[12] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[12] ),
+    .pad_gpio_in(\mprj_io_in[12] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[12] ),
+    .pad_gpio_out(\mprj_io_out[12] ),
+    .pad_gpio_outenb(\mprj_io_oeb[12] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[12] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[12] ),
+    .resetn(\gpio_resetn_1[11] ),
+    .resetn_out(\gpio_resetn_1[12] ),
+    .serial_clock(\gpio_clock_1[11] ),
+    .serial_clock_out(\gpio_clock_1[12] ),
+    .serial_data_in(\gpio_serial_link_1[11] ),
+    .serial_data_out(\gpio_serial_link_1[12] ),
+    .serial_load(\gpio_load_1[11] ),
+    .serial_load_out(\gpio_load_1[12] ),
+    .user_gpio_in(\user_io_in[12] ),
+    .user_gpio_oeb(\user_io_oeb[12] ),
+    .user_gpio_out(\user_io_out[12] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[5]  (
+    .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169]  }),
+    .mgmt_gpio_in(\mgmt_io_in[13] ),
+    .mgmt_gpio_oeb(\one_loop1[11] ),
+    .mgmt_gpio_out(\mgmt_io_in[13] ),
+    .one(\one_loop1[11] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[13] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[13] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[13] ),
+    .pad_gpio_dm({ \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[13] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[13] ),
+    .pad_gpio_in(\mprj_io_in[13] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[13] ),
+    .pad_gpio_out(\mprj_io_out[13] ),
+    .pad_gpio_outenb(\mprj_io_oeb[13] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[13] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[13] ),
+    .resetn(\gpio_resetn_1[12] ),
+    .resetn_out(\gpio_resetn_1[13] ),
+    .serial_clock(\gpio_clock_1[12] ),
+    .serial_clock_out(\gpio_clock_1[13] ),
+    .serial_data_in(\gpio_serial_link_1[12] ),
+    .serial_data_out(\gpio_serial_link_1[13] ),
+    .serial_load(\gpio_load_1[12] ),
+    .serial_load_out(\gpio_load_1[13] ),
+    .user_gpio_in(\user_io_in[13] ),
+    .user_gpio_oeb(\user_io_oeb[13] ),
+    .user_gpio_out(\user_io_out[13] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[0]  (
+    .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26]  }),
+    .mgmt_gpio_in(\mgmt_io_in[2] ),
+    .mgmt_gpio_oeb(\one_loop1[0] ),
+    .mgmt_gpio_out(\mgmt_io_in[2] ),
+    .one(\one_loop1[0] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[2] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[2] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[2] ),
+    .pad_gpio_dm({ \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[2] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[2] ),
+    .pad_gpio_in(\mprj_io_in[2] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[2] ),
+    .pad_gpio_out(\mprj_io_out[2] ),
+    .pad_gpio_outenb(\mprj_io_oeb[2] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[2] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[2] ),
+    .resetn(\gpio_resetn_1[1] ),
+    .resetn_out(\gpio_resetn_1[2] ),
+    .serial_clock(\gpio_clock_1[1] ),
+    .serial_clock_out(\gpio_clock_1[2] ),
+    .serial_data_in(\gpio_serial_link_1[1] ),
+    .serial_data_out(\gpio_serial_link_1[2] ),
+    .serial_load(\gpio_load_1[1] ),
+    .serial_load_out(\gpio_load_1[2] ),
+    .user_gpio_in(\user_io_in[2] ),
+    .user_gpio_oeb(\user_io_oeb[2] ),
+    .user_gpio_out(\user_io_out[2] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[1]  (
+    .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39]  }),
+    .mgmt_gpio_in(\mgmt_io_in[3] ),
+    .mgmt_gpio_oeb(\one_loop1[1] ),
+    .mgmt_gpio_out(\mgmt_io_in[3] ),
+    .one(\one_loop1[1] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[3] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[3] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[3] ),
+    .pad_gpio_dm({ \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[3] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[3] ),
+    .pad_gpio_in(\mprj_io_in[3] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[3] ),
+    .pad_gpio_out(\mprj_io_out[3] ),
+    .pad_gpio_outenb(\mprj_io_oeb[3] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[3] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[3] ),
+    .resetn(\gpio_resetn_1[2] ),
+    .resetn_out(\gpio_resetn_1[3] ),
+    .serial_clock(\gpio_clock_1[2] ),
+    .serial_clock_out(\gpio_clock_1[3] ),
+    .serial_data_in(\gpio_serial_link_1[2] ),
+    .serial_data_out(\gpio_serial_link_1[3] ),
+    .serial_load(\gpio_load_1[2] ),
+    .serial_load_out(\gpio_load_1[3] ),
+    .user_gpio_in(\user_io_in[3] ),
+    .user_gpio_oeb(\user_io_oeb[3] ),
+    .user_gpio_out(\user_io_out[3] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[2]  (
+    .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52]  }),
+    .mgmt_gpio_in(\mgmt_io_in[4] ),
+    .mgmt_gpio_oeb(\one_loop1[2] ),
+    .mgmt_gpio_out(\mgmt_io_in[4] ),
+    .one(\one_loop1[2] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[4] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[4] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[4] ),
+    .pad_gpio_dm({ \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[4] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[4] ),
+    .pad_gpio_in(\mprj_io_in[4] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[4] ),
+    .pad_gpio_out(\mprj_io_out[4] ),
+    .pad_gpio_outenb(\mprj_io_oeb[4] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[4] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[4] ),
+    .resetn(\gpio_resetn_1[3] ),
+    .resetn_out(\gpio_resetn_1[4] ),
+    .serial_clock(\gpio_clock_1[3] ),
+    .serial_clock_out(\gpio_clock_1[4] ),
+    .serial_data_in(\gpio_serial_link_1[3] ),
+    .serial_data_out(\gpio_serial_link_1[4] ),
+    .serial_load(\gpio_load_1[3] ),
+    .serial_load_out(\gpio_load_1[4] ),
+    .user_gpio_in(\user_io_in[4] ),
+    .user_gpio_oeb(\user_io_oeb[4] ),
+    .user_gpio_out(\user_io_out[4] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[3]  (
+    .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65]  }),
+    .mgmt_gpio_in(\mgmt_io_in[5] ),
+    .mgmt_gpio_oeb(\one_loop1[3] ),
+    .mgmt_gpio_out(\mgmt_io_in[5] ),
+    .one(\one_loop1[3] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[5] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[5] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[5] ),
+    .pad_gpio_dm({ \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[5] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[5] ),
+    .pad_gpio_in(\mprj_io_in[5] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[5] ),
+    .pad_gpio_out(\mprj_io_out[5] ),
+    .pad_gpio_outenb(\mprj_io_oeb[5] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[5] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[5] ),
+    .resetn(\gpio_resetn_1[4] ),
+    .resetn_out(\gpio_resetn_1[5] ),
+    .serial_clock(\gpio_clock_1[4] ),
+    .serial_clock_out(\gpio_clock_1[5] ),
+    .serial_data_in(\gpio_serial_link_1[4] ),
+    .serial_data_out(\gpio_serial_link_1[5] ),
+    .serial_load(\gpio_load_1[4] ),
+    .serial_load_out(\gpio_load_1[5] ),
+    .user_gpio_in(\user_io_in[5] ),
+    .user_gpio_oeb(\user_io_oeb[5] ),
+    .user_gpio_out(\user_io_out[5] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[4]  (
+    .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78]  }),
+    .mgmt_gpio_in(\mgmt_io_in[6] ),
+    .mgmt_gpio_oeb(\one_loop1[4] ),
+    .mgmt_gpio_out(\mgmt_io_in[6] ),
+    .one(\one_loop1[4] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[6] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[6] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[6] ),
+    .pad_gpio_dm({ \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[6] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[6] ),
+    .pad_gpio_in(\mprj_io_in[6] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[6] ),
+    .pad_gpio_out(\mprj_io_out[6] ),
+    .pad_gpio_outenb(\mprj_io_oeb[6] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[6] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[6] ),
+    .resetn(\gpio_resetn_1[5] ),
+    .resetn_out(\gpio_resetn_1[6] ),
+    .serial_clock(\gpio_clock_1[5] ),
+    .serial_clock_out(\gpio_clock_1[6] ),
+    .serial_data_in(\gpio_serial_link_1[5] ),
+    .serial_data_out(\gpio_serial_link_1[6] ),
+    .serial_load(\gpio_load_1[5] ),
+    .serial_load_out(\gpio_load_1[6] ),
+    .user_gpio_in(\user_io_in[6] ),
+    .user_gpio_oeb(\user_io_oeb[6] ),
+    .user_gpio_out(\user_io_out[6] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[5]  (
+    .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91]  }),
+    .mgmt_gpio_in(\mgmt_io_in[7] ),
+    .mgmt_gpio_oeb(\one_loop1[5] ),
+    .mgmt_gpio_out(\mgmt_io_in[7] ),
+    .one(\one_loop1[5] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[7] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[7] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[7] ),
+    .pad_gpio_dm({ \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[7] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[7] ),
+    .pad_gpio_in(\mprj_io_in[7] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[7] ),
+    .pad_gpio_out(\mprj_io_out[7] ),
+    .pad_gpio_outenb(\mprj_io_oeb[7] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[7] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[7] ),
+    .resetn(\gpio_resetn_1[6] ),
+    .resetn_out(\gpio_resetn_1[7] ),
+    .serial_clock(\gpio_clock_1[6] ),
+    .serial_clock_out(\gpio_clock_1[7] ),
+    .serial_data_in(\gpio_serial_link_1[6] ),
+    .serial_data_out(\gpio_serial_link_1[7] ),
+    .serial_load(\gpio_load_1[6] ),
+    .serial_load_out(\gpio_load_1[7] ),
+    .user_gpio_in(\user_io_in[7] ),
+    .user_gpio_oeb(\user_io_oeb[7] ),
+    .user_gpio_out(\user_io_out[7] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[0]  (
+    .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182]  }),
+    .mgmt_gpio_in(\mgmt_io_in[25] ),
+    .mgmt_gpio_oeb(\one_loop2[0] ),
+    .mgmt_gpio_out(\mgmt_io_in[25] ),
+    .one(\one_loop2[0] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[14] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[14] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[14] ),
+    .pad_gpio_dm({ \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[14] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[14] ),
+    .pad_gpio_in(\mprj_io_in[14] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[14] ),
+    .pad_gpio_out(\mprj_io_out[14] ),
+    .pad_gpio_outenb(\mprj_io_oeb[14] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[14] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[14] ),
+    .resetn(\gpio_resetn_2[1] ),
+    .resetn_out(\gpio_resetn_2[0] ),
+    .serial_clock(\gpio_clock_2[1] ),
+    .serial_clock_out(\gpio_clock_2[0] ),
+    .serial_data_in(\gpio_serial_link_2[1] ),
+    .serial_data_out(\gpio_serial_link_2[0] ),
+    .serial_load(\gpio_load_2[1] ),
+    .serial_load_out(\gpio_load_2[0] ),
+    .user_gpio_in(\user_io_in[14] ),
+    .user_gpio_oeb(\user_io_oeb[14] ),
+    .user_gpio_out(\user_io_out[14] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[1]  (
+    .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195]  }),
+    .mgmt_gpio_in(\mgmt_io_in[26] ),
+    .mgmt_gpio_oeb(\one_loop2[1] ),
+    .mgmt_gpio_out(\mgmt_io_in[26] ),
+    .one(\one_loop2[1] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[15] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[15] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[15] ),
+    .pad_gpio_dm({ \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[15] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[15] ),
+    .pad_gpio_in(\mprj_io_in[15] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[15] ),
+    .pad_gpio_out(\mprj_io_out[15] ),
+    .pad_gpio_outenb(\mprj_io_oeb[15] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[15] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[15] ),
+    .resetn(\gpio_resetn_2[2] ),
+    .resetn_out(\gpio_resetn_2[1] ),
+    .serial_clock(\gpio_clock_2[2] ),
+    .serial_clock_out(\gpio_clock_2[1] ),
+    .serial_data_in(\gpio_serial_link_2[2] ),
+    .serial_data_out(\gpio_serial_link_2[1] ),
+    .serial_load(\gpio_load_2[2] ),
+    .serial_load_out(\gpio_load_2[1] ),
+    .user_gpio_in(\user_io_in[15] ),
+    .user_gpio_oeb(\user_io_oeb[15] ),
+    .user_gpio_out(\user_io_out[15] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[2]  (
+    .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208]  }),
+    .mgmt_gpio_in(\mgmt_io_in[27] ),
+    .mgmt_gpio_oeb(\one_loop2[2] ),
+    .mgmt_gpio_out(\mgmt_io_in[27] ),
+    .one(\one_loop2[2] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[16] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[16] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[16] ),
+    .pad_gpio_dm({ \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[16] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[16] ),
+    .pad_gpio_in(\mprj_io_in[16] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[16] ),
+    .pad_gpio_out(\mprj_io_out[16] ),
+    .pad_gpio_outenb(\mprj_io_oeb[16] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[16] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[16] ),
+    .resetn(\gpio_resetn_2[3] ),
+    .resetn_out(\gpio_resetn_2[2] ),
+    .serial_clock(\gpio_clock_2[3] ),
+    .serial_clock_out(\gpio_clock_2[2] ),
+    .serial_data_in(\gpio_serial_link_2[3] ),
+    .serial_data_out(\gpio_serial_link_2[2] ),
+    .serial_load(\gpio_load_2[3] ),
+    .serial_load_out(\gpio_load_2[2] ),
+    .user_gpio_in(\user_io_in[16] ),
+    .user_gpio_oeb(\user_io_oeb[16] ),
+    .user_gpio_out(\user_io_out[16] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[3]  (
+    .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221]  }),
+    .mgmt_gpio_in(\mgmt_io_in[28] ),
+    .mgmt_gpio_oeb(\one_loop2[3] ),
+    .mgmt_gpio_out(\mgmt_io_in[28] ),
+    .one(\one_loop2[3] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[17] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[17] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[17] ),
+    .pad_gpio_dm({ \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[17] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[17] ),
+    .pad_gpio_in(\mprj_io_in[17] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[17] ),
+    .pad_gpio_out(\mprj_io_out[17] ),
+    .pad_gpio_outenb(\mprj_io_oeb[17] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[17] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[17] ),
+    .resetn(\gpio_resetn_2[4] ),
+    .resetn_out(\gpio_resetn_2[3] ),
+    .serial_clock(\gpio_clock_2[4] ),
+    .serial_clock_out(\gpio_clock_2[3] ),
+    .serial_data_in(\gpio_serial_link_2[4] ),
+    .serial_data_out(\gpio_serial_link_2[3] ),
+    .serial_load(\gpio_load_2[4] ),
+    .serial_load_out(\gpio_load_2[3] ),
+    .user_gpio_in(\user_io_in[17] ),
+    .user_gpio_oeb(\user_io_oeb[17] ),
+    .user_gpio_out(\user_io_out[17] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[4]  (
+    .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234]  }),
+    .mgmt_gpio_in(\mgmt_io_in[29] ),
+    .mgmt_gpio_oeb(\one_loop2[4] ),
+    .mgmt_gpio_out(\mgmt_io_in[29] ),
+    .one(\one_loop2[4] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[18] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[18] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[18] ),
+    .pad_gpio_dm({ \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[18] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[18] ),
+    .pad_gpio_in(\mprj_io_in[18] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[18] ),
+    .pad_gpio_out(\mprj_io_out[18] ),
+    .pad_gpio_outenb(\mprj_io_oeb[18] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[18] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[18] ),
+    .resetn(\gpio_resetn_2[5] ),
+    .resetn_out(\gpio_resetn_2[4] ),
+    .serial_clock(\gpio_clock_2[5] ),
+    .serial_clock_out(\gpio_clock_2[4] ),
+    .serial_data_in(\gpio_serial_link_2[5] ),
+    .serial_data_out(\gpio_serial_link_2[4] ),
+    .serial_load(\gpio_load_2[5] ),
+    .serial_load_out(\gpio_load_2[4] ),
+    .user_gpio_in(\user_io_in[18] ),
+    .user_gpio_oeb(\user_io_oeb[18] ),
+    .user_gpio_out(\user_io_out[18] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[5]  (
+    .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247]  }),
+    .mgmt_gpio_in(\mgmt_io_in[30] ),
+    .mgmt_gpio_oeb(\one_loop2[5] ),
+    .mgmt_gpio_out(\mgmt_io_in[30] ),
+    .one(\one_loop2[5] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[19] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[19] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[19] ),
+    .pad_gpio_dm({ \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[19] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[19] ),
+    .pad_gpio_in(\mprj_io_in[19] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[19] ),
+    .pad_gpio_out(\mprj_io_out[19] ),
+    .pad_gpio_outenb(\mprj_io_oeb[19] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[19] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[19] ),
+    .resetn(\gpio_resetn_2[6] ),
+    .resetn_out(\gpio_resetn_2[5] ),
+    .serial_clock(\gpio_clock_2[6] ),
+    .serial_clock_out(\gpio_clock_2[5] ),
+    .serial_data_in(\gpio_serial_link_2[6] ),
+    .serial_data_out(\gpio_serial_link_2[5] ),
+    .serial_load(\gpio_load_2[6] ),
+    .serial_load_out(\gpio_load_2[5] ),
+    .user_gpio_in(\user_io_in[19] ),
+    .user_gpio_oeb(\user_io_oeb[19] ),
+    .user_gpio_out(\user_io_out[19] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[6]  (
+    .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260]  }),
+    .mgmt_gpio_in(\mgmt_io_in[31] ),
+    .mgmt_gpio_oeb(\one_loop2[6] ),
+    .mgmt_gpio_out(\mgmt_io_in[31] ),
+    .one(\one_loop2[6] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[20] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[20] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[20] ),
+    .pad_gpio_dm({ \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[20] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[20] ),
+    .pad_gpio_in(\mprj_io_in[20] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[20] ),
+    .pad_gpio_out(\mprj_io_out[20] ),
+    .pad_gpio_outenb(\mprj_io_oeb[20] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[20] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[20] ),
+    .resetn(\gpio_resetn_2[7] ),
+    .resetn_out(\gpio_resetn_2[6] ),
+    .serial_clock(\gpio_clock_2[7] ),
+    .serial_clock_out(\gpio_clock_2[6] ),
+    .serial_data_in(\gpio_serial_link_2[7] ),
+    .serial_data_out(\gpio_serial_link_2[6] ),
+    .serial_load(\gpio_load_2[7] ),
+    .serial_load_out(\gpio_load_2[6] ),
+    .user_gpio_in(\user_io_in[20] ),
+    .user_gpio_oeb(\user_io_oeb[20] ),
+    .user_gpio_out(\user_io_out[20] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[7]  (
+    .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273]  }),
+    .mgmt_gpio_in(\mgmt_io_in[32] ),
+    .mgmt_gpio_oeb(\one_loop2[7] ),
+    .mgmt_gpio_out(\mgmt_io_in[32] ),
+    .one(\one_loop2[7] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[21] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[21] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[21] ),
+    .pad_gpio_dm({ \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[21] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[21] ),
+    .pad_gpio_in(\mprj_io_in[21] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[21] ),
+    .pad_gpio_out(\mprj_io_out[21] ),
+    .pad_gpio_outenb(\mprj_io_oeb[21] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[21] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[21] ),
+    .resetn(\gpio_resetn_2[8] ),
+    .resetn_out(\gpio_resetn_2[7] ),
+    .serial_clock(\gpio_clock_2[8] ),
+    .serial_clock_out(\gpio_clock_2[7] ),
+    .serial_data_in(\gpio_serial_link_2[8] ),
+    .serial_data_out(\gpio_serial_link_2[7] ),
+    .serial_load(\gpio_load_2[8] ),
+    .serial_load_out(\gpio_load_2[7] ),
+    .user_gpio_in(\user_io_in[21] ),
+    .user_gpio_oeb(\user_io_oeb[21] ),
+    .user_gpio_out(\user_io_out[21] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[8]  (
+    .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286]  }),
+    .mgmt_gpio_in(\mgmt_io_in[33] ),
+    .mgmt_gpio_oeb(\one_loop2[8] ),
+    .mgmt_gpio_out(\mgmt_io_in[33] ),
+    .one(\one_loop2[8] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[22] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[22] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[22] ),
+    .pad_gpio_dm({ \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[22] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[22] ),
+    .pad_gpio_in(\mprj_io_in[22] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[22] ),
+    .pad_gpio_out(\mprj_io_out[22] ),
+    .pad_gpio_outenb(\mprj_io_oeb[22] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[22] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[22] ),
+    .resetn(\gpio_resetn_2[9] ),
+    .resetn_out(\gpio_resetn_2[8] ),
+    .serial_clock(\gpio_clock_2[9] ),
+    .serial_clock_out(\gpio_clock_2[8] ),
+    .serial_data_in(\gpio_serial_link_2[9] ),
+    .serial_data_out(\gpio_serial_link_2[8] ),
+    .serial_load(\gpio_load_2[9] ),
+    .serial_load_out(\gpio_load_2[8] ),
+    .user_gpio_in(\user_io_in[22] ),
+    .user_gpio_oeb(\user_io_oeb[22] ),
+    .user_gpio_out(\user_io_out[22] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[9]  (
+    .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299]  }),
+    .mgmt_gpio_in(\mgmt_io_in[34] ),
+    .mgmt_gpio_oeb(\one_loop2[9] ),
+    .mgmt_gpio_out(\mgmt_io_in[34] ),
+    .one(\one_loop2[9] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[23] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[23] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[23] ),
+    .pad_gpio_dm({ \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[23] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[23] ),
+    .pad_gpio_in(\mprj_io_in[23] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[23] ),
+    .pad_gpio_out(\mprj_io_out[23] ),
+    .pad_gpio_outenb(\mprj_io_oeb[23] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[23] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[23] ),
+    .resetn(\gpio_resetn_2[10] ),
+    .resetn_out(\gpio_resetn_2[9] ),
+    .serial_clock(\gpio_clock_2[10] ),
+    .serial_clock_out(\gpio_clock_2[9] ),
+    .serial_data_in(\gpio_serial_link_2[10] ),
+    .serial_data_out(\gpio_serial_link_2[9] ),
+    .serial_load(\gpio_load_2[10] ),
+    .serial_load_out(\gpio_load_2[9] ),
+    .user_gpio_in(\user_io_in[23] ),
+    .user_gpio_oeb(\user_io_oeb[23] ),
+    .user_gpio_out(\user_io_out[23] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  housekeeping housekeeping (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .debug_in(debug_in),
+    .debug_mode(debug_mode),
+    .debug_oeb(debug_oeb),
+    .debug_out(debug_out),
+    .irq({ \irq_spi[2] , \irq_spi[1] , \irq_spi[0]  }),
+    .mask_rev_in({ \mask_rev[31] , \mask_rev[30] , \mask_rev[29] , \mask_rev[28] , \mask_rev[27] , \mask_rev[26] , \mask_rev[25] , \mask_rev[24] , \mask_rev[23] , \mask_rev[22] , \mask_rev[21] , \mask_rev[20] , \mask_rev[19] , \mask_rev[18] , \mask_rev[17] , \mask_rev[16] , \mask_rev[15] , \mask_rev[14] , \mask_rev[13] , \mask_rev[12] , \mask_rev[11] , \mask_rev[10] , \mask_rev[9] , \mask_rev[8] , \mask_rev[7] , \mask_rev[6] , \mask_rev[5] , \mask_rev[4] , \mask_rev[3] , \mask_rev[2] , \mask_rev[1] , \mask_rev[0]  }),
+    .mgmt_gpio_in({ \mgmt_io_in[37] , \mgmt_io_in[36] , \mgmt_io_in[35] , \mgmt_io_in[34] , \mgmt_io_in[33] , \mgmt_io_in[32] , \mgmt_io_in[31] , \mgmt_io_in[30] , \mgmt_io_in[29] , \mgmt_io_in[28] , \mgmt_io_in[27] , \mgmt_io_in[26] , \mgmt_io_in[25] , \mgmt_io_in[24] , \mgmt_io_in[23] , \mgmt_io_in[22] , \mgmt_io_in[21] , \mgmt_io_in[20] , \mgmt_io_in[19] , \mgmt_io_in[18] , \mgmt_io_in[17] , \mgmt_io_in[16] , \mgmt_io_in[15] , \mgmt_io_in[14] , \mgmt_io_in[13] , \mgmt_io_in[12] , \mgmt_io_in[11] , \mgmt_io_in[10] , \mgmt_io_in[9] , \mgmt_io_in[8] , \mgmt_io_in[7] , \mgmt_io_in[6] , \mgmt_io_in[5] , \mgmt_io_in[4] , \mgmt_io_in[3] , \mgmt_io_in[2] , \mgmt_io_in[1] , \mgmt_io_in[0]  }),
+    .mgmt_gpio_oeb({ \mgmt_io_oeb[4] , \mgmt_io_oeb[3] , \mgmt_io_oeb[2] , \mgmt_io_nc[32] , \mgmt_io_nc[31] , \mgmt_io_nc[30] , \mgmt_io_nc[29] , \mgmt_io_nc[28] , \mgmt_io_nc[27] , \mgmt_io_nc[26] , \mgmt_io_nc[25] , \mgmt_io_nc[24] , \mgmt_io_nc[23] , \mgmt_io_nc[22] , \mgmt_io_nc[21] , \mgmt_io_nc[20] , \mgmt_io_nc[19] , \mgmt_io_nc[18] , \mgmt_io_nc[17] , \mgmt_io_nc[16] , \mgmt_io_nc[15] , \mgmt_io_nc[14] , \mgmt_io_nc[13] , \mgmt_io_nc[12] , \mgmt_io_nc[11] , \mgmt_io_nc[10] , \mgmt_io_nc[9] , \mgmt_io_nc[8] , \mgmt_io_nc[7] , \mgmt_io_nc[6] , \mgmt_io_nc[5] , \mgmt_io_nc[4] , \mgmt_io_nc[3] , \mgmt_io_nc[2] , \mgmt_io_nc[1] , \mgmt_io_nc[0] , \mgmt_io_oeb[1] , \mgmt_io_oeb[0]  }),
+    .mgmt_gpio_out({ \mgmt_io_out[4] , \mgmt_io_out[3] , \mgmt_io_out[2] , \mgmt_io_in[34] , \mgmt_io_in[33] , \mgmt_io_in[32] , \mgmt_io_in[31] , \mgmt_io_in[30] , \mgmt_io_in[29] , \mgmt_io_in[28] , \mgmt_io_in[27] , \mgmt_io_in[26] , \mgmt_io_in[25] , \mgmt_io_in[24] , \mgmt_io_in[23] , \mgmt_io_in[22] , \mgmt_io_in[21] , \mgmt_io_in[20] , \mgmt_io_in[19] , \mgmt_io_in[18] , \mgmt_io_in[17] , \mgmt_io_in[16] , \mgmt_io_in[15] , \mgmt_io_in[14] , \mgmt_io_in[13] , \mgmt_io_in[12] , \mgmt_io_in[11] , \mgmt_io_in[10] , \mgmt_io_in[9] , \mgmt_io_in[8] , \mgmt_io_in[7] , \mgmt_io_in[6] , \mgmt_io_in[5] , \mgmt_io_in[4] , \mgmt_io_in[3] , \mgmt_io_in[2] , \mgmt_io_out[1] , \mgmt_io_out[0]  }),
+    .pad_flash_clk(flash_clk_frame),
+    .pad_flash_clk_oeb(flash_clk_oeb),
+    .pad_flash_csb(flash_csb_frame),
+    .pad_flash_csb_oeb(flash_csb_oeb),
+    .pad_flash_io0_di(flash_io0_di),
+    .pad_flash_io0_do(flash_io0_do),
+    .pad_flash_io0_ieb(flash_io0_ieb),
+    .pad_flash_io0_oeb(flash_io0_oeb),
+    .pad_flash_io1_di(flash_io1_di),
+    .pad_flash_io1_do(flash_io1_do),
+    .pad_flash_io1_ieb(flash_io1_ieb),
+    .pad_flash_io1_oeb(flash_io1_oeb),
+    .pll90_sel({ \spi_pll90_sel[2] , \spi_pll90_sel[1] , \spi_pll90_sel[0]  }),
+    .pll_bypass(ext_clk_sel),
+    .pll_dco_ena(spi_pll_dco_ena),
+    .pll_div({ \spi_pll_div[4] , \spi_pll_div[3] , \spi_pll_div[2] , \spi_pll_div[1] , \spi_pll_div[0]  }),
+    .pll_ena(spi_pll_ena),
+    .pll_sel({ \spi_pll_sel[2] , \spi_pll_sel[1] , \spi_pll_sel[0]  }),
+    .pll_trim({ \spi_pll_trim[25] , \spi_pll_trim[24] , \spi_pll_trim[23] , \spi_pll_trim[22] , \spi_pll_trim[21] , \spi_pll_trim[20] , \spi_pll_trim[19] , \spi_pll_trim[18] , \spi_pll_trim[17] , \spi_pll_trim[16] , \spi_pll_trim[15] , \spi_pll_trim[14] , \spi_pll_trim[13] , \spi_pll_trim[12] , \spi_pll_trim[11] , \spi_pll_trim[10] , \spi_pll_trim[9] , \spi_pll_trim[8] , \spi_pll_trim[7] , \spi_pll_trim[6] , \spi_pll_trim[5] , \spi_pll_trim[4] , \spi_pll_trim[3] , \spi_pll_trim[2] , \spi_pll_trim[1] , \spi_pll_trim[0]  }),
+    .porb(porb_l),
+    .pwr_ctrl_out({ \pwr_ctrl_nc[3] , \pwr_ctrl_nc[2] , \pwr_ctrl_nc[1] , \pwr_ctrl_nc[0]  }),
+    .qspi_enabled(qspi_enabled),
+    .reset(ext_reset),
+    .ser_rx(ser_rx),
+    .ser_tx(ser_tx),
+    .serial_clock(\gpio_clock_1_shifted[0] ),
+    .serial_data_1(\gpio_serial_link_1_shifted[0] ),
+    .serial_data_2(\gpio_serial_link_2_shifted[12] ),
+    .serial_load(\gpio_load_1_shifted[0] ),
+    .serial_resetn(\gpio_resetn_1_shifted[0] ),
+    .spi_csb(spi_csb),
+    .spi_enabled(spi_enabled),
+    .spi_sck(spi_sck),
+    .spi_sdi(spi_sdi),
+    .spi_sdo(spi_sdo),
+    .spi_sdoenb(spi_sdoenb),
+    .spimemio_flash_clk(flash_clk_core),
+    .spimemio_flash_csb(flash_csb_core),
+    .spimemio_flash_io0_di(flash_io0_di_core),
+    .spimemio_flash_io0_do(flash_io0_do_core),
+    .spimemio_flash_io0_oeb(flash_io0_oeb_core),
+    .spimemio_flash_io1_di(flash_io1_di_core),
+    .spimemio_flash_io1_do(flash_io1_do_core),
+    .spimemio_flash_io1_oeb(flash_io1_oeb_core),
+    .spimemio_flash_io2_di(flash_io2_di_core),
+    .spimemio_flash_io2_do(flash_io2_do_core),
+    .spimemio_flash_io2_oeb(flash_io2_oeb_core),
+    .spimemio_flash_io3_di(flash_io3_di_core),
+    .spimemio_flash_io3_do(flash_io3_do_core),
+    .spimemio_flash_io3_oeb(flash_io3_oeb_core),
+    .sram_ro_addr({ \hkspi_sram_addr[7] , \hkspi_sram_addr[6] , \hkspi_sram_addr[5] , \hkspi_sram_addr[4] , \hkspi_sram_addr[3] , \hkspi_sram_addr[2] , \hkspi_sram_addr[1] , \hkspi_sram_addr[0]  }),
+    .sram_ro_clk(hkspi_sram_clk),
+    .sram_ro_csb(hkspi_sram_csb),
+    .sram_ro_data({ \hkspi_sram_data[31] , \hkspi_sram_data[30] , \hkspi_sram_data[29] , \hkspi_sram_data[28] , \hkspi_sram_data[27] , \hkspi_sram_data[26] , \hkspi_sram_data[25] , \hkspi_sram_data[24] , \hkspi_sram_data[23] , \hkspi_sram_data[22] , \hkspi_sram_data[21] , \hkspi_sram_data[20] , \hkspi_sram_data[19] , \hkspi_sram_data[18] , \hkspi_sram_data[17] , \hkspi_sram_data[16] , \hkspi_sram_data[15] , \hkspi_sram_data[14] , \hkspi_sram_data[13] , \hkspi_sram_data[12] , \hkspi_sram_data[11] , \hkspi_sram_data[10] , \hkspi_sram_data[9] , \hkspi_sram_data[8] , \hkspi_sram_data[7] , \hkspi_sram_data[6] , \hkspi_sram_data[5] , \hkspi_sram_data[4] , \hkspi_sram_data[3] , \hkspi_sram_data[2] , \hkspi_sram_data[1] , \hkspi_sram_data[0]  }),
+    .trap(trap),
+    .uart_enabled(uart_enabled),
+    .user_clock(caravel_clk2),
+    .usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+    .usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+    .usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+    .usr2_vdd_pwrgood(mprj2_vdd_pwrgood),
+    .wb_ack_o(hk_ack_i),
+    .wb_adr_i({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0]  }),
+    .wb_clk_i(caravel_clk),
+    .wb_cyc_i(hk_cyc_o),
+    .wb_dat_i({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0]  }),
+    .wb_dat_o({ \hk_dat_i[31] , \hk_dat_i[30] , \hk_dat_i[29] , \hk_dat_i[28] , \hk_dat_i[27] , \hk_dat_i[26] , \hk_dat_i[25] , \hk_dat_i[24] , \hk_dat_i[23] , \hk_dat_i[22] , \hk_dat_i[21] , \hk_dat_i[20] , \hk_dat_i[19] , \hk_dat_i[18] , \hk_dat_i[17] , \hk_dat_i[16] , \hk_dat_i[15] , \hk_dat_i[14] , \hk_dat_i[13] , \hk_dat_i[12] , \hk_dat_i[11] , \hk_dat_i[10] , \hk_dat_i[9] , \hk_dat_i[8] , \hk_dat_i[7] , \hk_dat_i[6] , \hk_dat_i[5] , \hk_dat_i[4] , \hk_dat_i[3] , \hk_dat_i[2] , \hk_dat_i[1] , \hk_dat_i[0]  }),
+    .wb_rstn_i(caravel_rstn),
+    .wb_sel_i({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0]  }),
+    .wb_stb_i(hk_stb_o),
+    .wb_we_i(mprj_we_o_core)
+  );
+  mgmt_protect mgmt_buffers (
+    .caravel_clk(caravel_clk),
+    .caravel_clk2(caravel_clk2),
+    .caravel_rstn(caravel_rstn),
+    .la_data_in_core({ \la_data_in_user[127] , \la_data_in_user[126] , \la_data_in_user[125] , \la_data_in_user[124] , \la_data_in_user[123] , \la_data_in_user[122] , \la_data_in_user[121] , \la_data_in_user[120] , \la_data_in_user[119] , \la_data_in_user[118] , \la_data_in_user[117] , \la_data_in_user[116] , \la_data_in_user[115] , \la_data_in_user[114] , \la_data_in_user[113] , \la_data_in_user[112] , \la_data_in_user[111] , \la_data_in_user[110] , \la_data_in_user[109] , \la_data_in_user[108] , \la_data_in_user[107] , \la_data_in_user[106] , \la_data_in_user[105] , \la_data_in_user[104] , \la_data_in_user[103] , \la_data_in_user[102] , \la_data_in_user[101] , \la_data_in_user[100] , \la_data_in_user[99] , \la_data_in_user[98] , \la_data_in_user[97] , \la_data_in_user[96] , \la_data_in_user[95] , \la_data_in_user[94] , \la_data_in_user[93] , \la_data_in_user[92] , \la_data_in_user[91] , \la_data_in_user[90] , \la_data_in_user[89] , \la_data_in_user[88] , \la_data_in_user[87] , \la_data_in_user[86] , \la_data_in_user[85] , \la_data_in_user[84] , \la_data_in_user[83] , \la_data_in_user[82] , \la_data_in_user[81] , \la_data_in_user[80] , \la_data_in_user[79] , \la_data_in_user[78] , \la_data_in_user[77] , \la_data_in_user[76] , \la_data_in_user[75] , \la_data_in_user[74] , \la_data_in_user[73] , \la_data_in_user[72] , \la_data_in_user[71] , \la_data_in_user[70] , \la_data_in_user[69] , \la_data_in_user[68] , \la_data_in_user[67] , \la_data_in_user[66] , \la_data_in_user[65] , \la_data_in_user[64] , \la_data_in_user[63] , \la_data_in_user[62] , \la_data_in_user[61] , \la_data_in_user[60] , \la_data_in_user[59] , \la_data_in_user[58] , \la_data_in_user[57] , \la_data_in_user[56] , \la_data_in_user[55] , \la_data_in_user[54] , \la_data_in_user[53] , \la_data_in_user[52] , \la_data_in_user[51] , \la_data_in_user[50] , \la_data_in_user[49] , \la_data_in_user[48] , \la_data_in_user[47] , \la_data_in_user[46] , \la_data_in_user[45] , \la_data_in_user[44] , \la_data_in_user[43] , \la_data_in_user[42] , \la_data_in_user[41] , \la_data_in_user[40] , \la_data_in_user[39] , \la_data_in_user[38] , \la_data_in_user[37] , \la_data_in_user[36] , \la_data_in_user[35] , \la_data_in_user[34] , \la_data_in_user[33] , \la_data_in_user[32] , \la_data_in_user[31] , \la_data_in_user[30] , \la_data_in_user[29] , \la_data_in_user[28] , \la_data_in_user[27] , \la_data_in_user[26] , \la_data_in_user[25] , \la_data_in_user[24] , \la_data_in_user[23] , \la_data_in_user[22] , \la_data_in_user[21] , \la_data_in_user[20] , \la_data_in_user[19] , \la_data_in_user[18] , \la_data_in_user[17] , \la_data_in_user[16] , \la_data_in_user[15] , \la_data_in_user[14] , \la_data_in_user[13] , \la_data_in_user[12] , \la_data_in_user[11] , \la_data_in_user[10] , \la_data_in_user[9] , \la_data_in_user[8] , \la_data_in_user[7] , \la_data_in_user[6] , \la_data_in_user[5] , \la_data_in_user[4] , \la_data_in_user[3] , \la_data_in_user[2] , \la_data_in_user[1] , \la_data_in_user[0]  }),
+    .la_data_in_mprj({ \la_data_in_mprj[127] , \la_data_in_mprj[126] , \la_data_in_mprj[125] , \la_data_in_mprj[124] , \la_data_in_mprj[123] , \la_data_in_mprj[122] , \la_data_in_mprj[121] , \la_data_in_mprj[120] , \la_data_in_mprj[119] , \la_data_in_mprj[118] , \la_data_in_mprj[117] , \la_data_in_mprj[116] , \la_data_in_mprj[115] , \la_data_in_mprj[114] , \la_data_in_mprj[113] , \la_data_in_mprj[112] , \la_data_in_mprj[111] , \la_data_in_mprj[110] , \la_data_in_mprj[109] , \la_data_in_mprj[108] , \la_data_in_mprj[107] , \la_data_in_mprj[106] , \la_data_in_mprj[105] , \la_data_in_mprj[104] , \la_data_in_mprj[103] , \la_data_in_mprj[102] , \la_data_in_mprj[101] , \la_data_in_mprj[100] , \la_data_in_mprj[99] , \la_data_in_mprj[98] , \la_data_in_mprj[97] , \la_data_in_mprj[96] , \la_data_in_mprj[95] , \la_data_in_mprj[94] , \la_data_in_mprj[93] , \la_data_in_mprj[92] , \la_data_in_mprj[91] , \la_data_in_mprj[90] , \la_data_in_mprj[89] , \la_data_in_mprj[88] , \la_data_in_mprj[87] , \la_data_in_mprj[86] , \la_data_in_mprj[85] , \la_data_in_mprj[84] , \la_data_in_mprj[83] , \la_data_in_mprj[82] , \la_data_in_mprj[81] , \la_data_in_mprj[80] , \la_data_in_mprj[79] , \la_data_in_mprj[78] , \la_data_in_mprj[77] , \la_data_in_mprj[76] , \la_data_in_mprj[75] , \la_data_in_mprj[74] , \la_data_in_mprj[73] , \la_data_in_mprj[72] , \la_data_in_mprj[71] , \la_data_in_mprj[70] , \la_data_in_mprj[69] , \la_data_in_mprj[68] , \la_data_in_mprj[67] , \la_data_in_mprj[66] , \la_data_in_mprj[65] , \la_data_in_mprj[64] , \la_data_in_mprj[63] , \la_data_in_mprj[62] , \la_data_in_mprj[61] , \la_data_in_mprj[60] , \la_data_in_mprj[59] , \la_data_in_mprj[58] , \la_data_in_mprj[57] , \la_data_in_mprj[56] , \la_data_in_mprj[55] , \la_data_in_mprj[54] , \la_data_in_mprj[53] , \la_data_in_mprj[52] , \la_data_in_mprj[51] , \la_data_in_mprj[50] , \la_data_in_mprj[49] , \la_data_in_mprj[48] , \la_data_in_mprj[47] , \la_data_in_mprj[46] , \la_data_in_mprj[45] , \la_data_in_mprj[44] , \la_data_in_mprj[43] , \la_data_in_mprj[42] , \la_data_in_mprj[41] , \la_data_in_mprj[40] , \la_data_in_mprj[39] , \la_data_in_mprj[38] , \la_data_in_mprj[37] , \la_data_in_mprj[36] , \la_data_in_mprj[35] , \la_data_in_mprj[34] , \la_data_in_mprj[33] , \la_data_in_mprj[32] , \la_data_in_mprj[31] , \la_data_in_mprj[30] , \la_data_in_mprj[29] , \la_data_in_mprj[28] , \la_data_in_mprj[27] , \la_data_in_mprj[26] , \la_data_in_mprj[25] , \la_data_in_mprj[24] , \la_data_in_mprj[23] , \la_data_in_mprj[22] , \la_data_in_mprj[21] , \la_data_in_mprj[20] , \la_data_in_mprj[19] , \la_data_in_mprj[18] , \la_data_in_mprj[17] , \la_data_in_mprj[16] , \la_data_in_mprj[15] , \la_data_in_mprj[14] , \la_data_in_mprj[13] , \la_data_in_mprj[12] , \la_data_in_mprj[11] , \la_data_in_mprj[10] , \la_data_in_mprj[9] , \la_data_in_mprj[8] , \la_data_in_mprj[7] , \la_data_in_mprj[6] , \la_data_in_mprj[5] , \la_data_in_mprj[4] , \la_data_in_mprj[3] , \la_data_in_mprj[2] , \la_data_in_mprj[1] , \la_data_in_mprj[0]  }),
+    .la_data_out_core({ \la_data_out_user[127] , \la_data_out_user[126] , \la_data_out_user[125] , \la_data_out_user[124] , \la_data_out_user[123] , \la_data_out_user[122] , \la_data_out_user[121] , \la_data_out_user[120] , \la_data_out_user[119] , \la_data_out_user[118] , \la_data_out_user[117] , \la_data_out_user[116] , \la_data_out_user[115] , \la_data_out_user[114] , \la_data_out_user[113] , \la_data_out_user[112] , \la_data_out_user[111] , \la_data_out_user[110] , \la_data_out_user[109] , \la_data_out_user[108] , \la_data_out_user[107] , \la_data_out_user[106] , \la_data_out_user[105] , \la_data_out_user[104] , \la_data_out_user[103] , \la_data_out_user[102] , \la_data_out_user[101] , \la_data_out_user[100] , \la_data_out_user[99] , \la_data_out_user[98] , \la_data_out_user[97] , \la_data_out_user[96] , \la_data_out_user[95] , \la_data_out_user[94] , \la_data_out_user[93] , \la_data_out_user[92] , \la_data_out_user[91] , \la_data_out_user[90] , \la_data_out_user[89] , \la_data_out_user[88] , \la_data_out_user[87] , \la_data_out_user[86] , \la_data_out_user[85] , \la_data_out_user[84] , \la_data_out_user[83] , \la_data_out_user[82] , \la_data_out_user[81] , \la_data_out_user[80] , \la_data_out_user[79] , \la_data_out_user[78] , \la_data_out_user[77] , \la_data_out_user[76] , \la_data_out_user[75] , \la_data_out_user[74] , \la_data_out_user[73] , \la_data_out_user[72] , \la_data_out_user[71] , \la_data_out_user[70] , \la_data_out_user[69] , \la_data_out_user[68] , \la_data_out_user[67] , \la_data_out_user[66] , \la_data_out_user[65] , \la_data_out_user[64] , \la_data_out_user[63] , \la_data_out_user[62] , \la_data_out_user[61] , \la_data_out_user[60] , \la_data_out_user[59] , \la_data_out_user[58] , \la_data_out_user[57] , \la_data_out_user[56] , \la_data_out_user[55] , \la_data_out_user[54] , \la_data_out_user[53] , \la_data_out_user[52] , \la_data_out_user[51] , \la_data_out_user[50] , \la_data_out_user[49] , \la_data_out_user[48] , \la_data_out_user[47] , \la_data_out_user[46] , \la_data_out_user[45] , \la_data_out_user[44] , \la_data_out_user[43] , \la_data_out_user[42] , \la_data_out_user[41] , \la_data_out_user[40] , \la_data_out_user[39] , \la_data_out_user[38] , \la_data_out_user[37] , \la_data_out_user[36] , \la_data_out_user[35] , \la_data_out_user[34] , \la_data_out_user[33] , \la_data_out_user[32] , \la_data_out_user[31] , \la_data_out_user[30] , \la_data_out_user[29] , \la_data_out_user[28] , \la_data_out_user[27] , \la_data_out_user[26] , \la_data_out_user[25] , \la_data_out_user[24] , \la_data_out_user[23] , \la_data_out_user[22] , \la_data_out_user[21] , \la_data_out_user[20] , \la_data_out_user[19] , \la_data_out_user[18] , \la_data_out_user[17] , \la_data_out_user[16] , \la_data_out_user[15] , \la_data_out_user[14] , \la_data_out_user[13] , \la_data_out_user[12] , \la_data_out_user[11] , \la_data_out_user[10] , \la_data_out_user[9] , \la_data_out_user[8] , \la_data_out_user[7] , \la_data_out_user[6] , \la_data_out_user[5] , \la_data_out_user[4] , \la_data_out_user[3] , \la_data_out_user[2] , \la_data_out_user[1] , \la_data_out_user[0]  }),
+    .la_data_out_mprj({ \la_data_out_mprj[127] , \la_data_out_mprj[126] , \la_data_out_mprj[125] , \la_data_out_mprj[124] , \la_data_out_mprj[123] , \la_data_out_mprj[122] , \la_data_out_mprj[121] , \la_data_out_mprj[120] , \la_data_out_mprj[119] , \la_data_out_mprj[118] , \la_data_out_mprj[117] , \la_data_out_mprj[116] , \la_data_out_mprj[115] , \la_data_out_mprj[114] , \la_data_out_mprj[113] , \la_data_out_mprj[112] , \la_data_out_mprj[111] , \la_data_out_mprj[110] , \la_data_out_mprj[109] , \la_data_out_mprj[108] , \la_data_out_mprj[107] , \la_data_out_mprj[106] , \la_data_out_mprj[105] , \la_data_out_mprj[104] , \la_data_out_mprj[103] , \la_data_out_mprj[102] , \la_data_out_mprj[101] , \la_data_out_mprj[100] , \la_data_out_mprj[99] , \la_data_out_mprj[98] , \la_data_out_mprj[97] , \la_data_out_mprj[96] , \la_data_out_mprj[95] , \la_data_out_mprj[94] , \la_data_out_mprj[93] , \la_data_out_mprj[92] , \la_data_out_mprj[91] , \la_data_out_mprj[90] , \la_data_out_mprj[89] , \la_data_out_mprj[88] , \la_data_out_mprj[87] , \la_data_out_mprj[86] , \la_data_out_mprj[85] , \la_data_out_mprj[84] , \la_data_out_mprj[83] , \la_data_out_mprj[82] , \la_data_out_mprj[81] , \la_data_out_mprj[80] , \la_data_out_mprj[79] , \la_data_out_mprj[78] , \la_data_out_mprj[77] , \la_data_out_mprj[76] , \la_data_out_mprj[75] , \la_data_out_mprj[74] , \la_data_out_mprj[73] , \la_data_out_mprj[72] , \la_data_out_mprj[71] , \la_data_out_mprj[70] , \la_data_out_mprj[69] , \la_data_out_mprj[68] , \la_data_out_mprj[67] , \la_data_out_mprj[66] , \la_data_out_mprj[65] , \la_data_out_mprj[64] , \la_data_out_mprj[63] , \la_data_out_mprj[62] , \la_data_out_mprj[61] , \la_data_out_mprj[60] , \la_data_out_mprj[59] , \la_data_out_mprj[58] , \la_data_out_mprj[57] , \la_data_out_mprj[56] , \la_data_out_mprj[55] , \la_data_out_mprj[54] , \la_data_out_mprj[53] , \la_data_out_mprj[52] , \la_data_out_mprj[51] , \la_data_out_mprj[50] , \la_data_out_mprj[49] , \la_data_out_mprj[48] , \la_data_out_mprj[47] , \la_data_out_mprj[46] , \la_data_out_mprj[45] , \la_data_out_mprj[44] , \la_data_out_mprj[43] , \la_data_out_mprj[42] , \la_data_out_mprj[41] , \la_data_out_mprj[40] , \la_data_out_mprj[39] , \la_data_out_mprj[38] , \la_data_out_mprj[37] , \la_data_out_mprj[36] , \la_data_out_mprj[35] , \la_data_out_mprj[34] , \la_data_out_mprj[33] , \la_data_out_mprj[32] , \la_data_out_mprj[31] , \la_data_out_mprj[30] , \la_data_out_mprj[29] , \la_data_out_mprj[28] , \la_data_out_mprj[27] , \la_data_out_mprj[26] , \la_data_out_mprj[25] , \la_data_out_mprj[24] , \la_data_out_mprj[23] , \la_data_out_mprj[22] , \la_data_out_mprj[21] , \la_data_out_mprj[20] , \la_data_out_mprj[19] , \la_data_out_mprj[18] , \la_data_out_mprj[17] , \la_data_out_mprj[16] , \la_data_out_mprj[15] , \la_data_out_mprj[14] , \la_data_out_mprj[13] , \la_data_out_mprj[12] , \la_data_out_mprj[11] , \la_data_out_mprj[10] , \la_data_out_mprj[9] , \la_data_out_mprj[8] , \la_data_out_mprj[7] , \la_data_out_mprj[6] , \la_data_out_mprj[5] , \la_data_out_mprj[4] , \la_data_out_mprj[3] , \la_data_out_mprj[2] , \la_data_out_mprj[1] , \la_data_out_mprj[0]  }),
+    .la_iena_mprj({ \la_iena_mprj[127] , \la_iena_mprj[126] , \la_iena_mprj[125] , \la_iena_mprj[124] , \la_iena_mprj[123] , \la_iena_mprj[122] , \la_iena_mprj[121] , \la_iena_mprj[120] , \la_iena_mprj[119] , \la_iena_mprj[118] , \la_iena_mprj[117] , \la_iena_mprj[116] , \la_iena_mprj[115] , \la_iena_mprj[114] , \la_iena_mprj[113] , \la_iena_mprj[112] , \la_iena_mprj[111] , \la_iena_mprj[110] , \la_iena_mprj[109] , \la_iena_mprj[108] , \la_iena_mprj[107] , \la_iena_mprj[106] , \la_iena_mprj[105] , \la_iena_mprj[104] , \la_iena_mprj[103] , \la_iena_mprj[102] , \la_iena_mprj[101] , \la_iena_mprj[100] , \la_iena_mprj[99] , \la_iena_mprj[98] , \la_iena_mprj[97] , \la_iena_mprj[96] , \la_iena_mprj[95] , \la_iena_mprj[94] , \la_iena_mprj[93] , \la_iena_mprj[92] , \la_iena_mprj[91] , \la_iena_mprj[90] , \la_iena_mprj[89] , \la_iena_mprj[88] , \la_iena_mprj[87] , \la_iena_mprj[86] , \la_iena_mprj[85] , \la_iena_mprj[84] , \la_iena_mprj[83] , \la_iena_mprj[82] , \la_iena_mprj[81] , \la_iena_mprj[80] , \la_iena_mprj[79] , \la_iena_mprj[78] , \la_iena_mprj[77] , \la_iena_mprj[76] , \la_iena_mprj[75] , \la_iena_mprj[74] , \la_iena_mprj[73] , \la_iena_mprj[72] , \la_iena_mprj[71] , \la_iena_mprj[70] , \la_iena_mprj[69] , \la_iena_mprj[68] , \la_iena_mprj[67] , \la_iena_mprj[66] , \la_iena_mprj[65] , \la_iena_mprj[64] , \la_iena_mprj[63] , \la_iena_mprj[62] , \la_iena_mprj[61] , \la_iena_mprj[60] , \la_iena_mprj[59] , \la_iena_mprj[58] , \la_iena_mprj[57] , \la_iena_mprj[56] , \la_iena_mprj[55] , \la_iena_mprj[54] , \la_iena_mprj[53] , \la_iena_mprj[52] , \la_iena_mprj[51] , \la_iena_mprj[50] , \la_iena_mprj[49] , \la_iena_mprj[48] , \la_iena_mprj[47] , \la_iena_mprj[46] , \la_iena_mprj[45] , \la_iena_mprj[44] , \la_iena_mprj[43] , \la_iena_mprj[42] , \la_iena_mprj[41] , \la_iena_mprj[40] , \la_iena_mprj[39] , \la_iena_mprj[38] , \la_iena_mprj[37] , \la_iena_mprj[36] , \la_iena_mprj[35] , \la_iena_mprj[34] , \la_iena_mprj[33] , \la_iena_mprj[32] , \la_iena_mprj[31] , \la_iena_mprj[30] , \la_iena_mprj[29] , \la_iena_mprj[28] , \la_iena_mprj[27] , \la_iena_mprj[26] , \la_iena_mprj[25] , \la_iena_mprj[24] , \la_iena_mprj[23] , \la_iena_mprj[22] , \la_iena_mprj[21] , \la_iena_mprj[20] , \la_iena_mprj[19] , \la_iena_mprj[18] , \la_iena_mprj[17] , \la_iena_mprj[16] , \la_iena_mprj[15] , \la_iena_mprj[14] , \la_iena_mprj[13] , \la_iena_mprj[12] , \la_iena_mprj[11] , \la_iena_mprj[10] , \la_iena_mprj[9] , \la_iena_mprj[8] , \la_iena_mprj[7] , \la_iena_mprj[6] , \la_iena_mprj[5] , \la_iena_mprj[4] , \la_iena_mprj[3] , \la_iena_mprj[2] , \la_iena_mprj[1] , \la_iena_mprj[0]  }),
+    .la_oenb_core({ \la_oenb_user[127] , \la_oenb_user[126] , \la_oenb_user[125] , \la_oenb_user[124] , \la_oenb_user[123] , \la_oenb_user[122] , \la_oenb_user[121] , \la_oenb_user[120] , \la_oenb_user[119] , \la_oenb_user[118] , \la_oenb_user[117] , \la_oenb_user[116] , \la_oenb_user[115] , \la_oenb_user[114] , \la_oenb_user[113] , \la_oenb_user[112] , \la_oenb_user[111] , \la_oenb_user[110] , \la_oenb_user[109] , \la_oenb_user[108] , \la_oenb_user[107] , \la_oenb_user[106] , \la_oenb_user[105] , \la_oenb_user[104] , \la_oenb_user[103] , \la_oenb_user[102] , \la_oenb_user[101] , \la_oenb_user[100] , \la_oenb_user[99] , \la_oenb_user[98] , \la_oenb_user[97] , \la_oenb_user[96] , \la_oenb_user[95] , \la_oenb_user[94] , \la_oenb_user[93] , \la_oenb_user[92] , \la_oenb_user[91] , \la_oenb_user[90] , \la_oenb_user[89] , \la_oenb_user[88] , \la_oenb_user[87] , \la_oenb_user[86] , \la_oenb_user[85] , \la_oenb_user[84] , \la_oenb_user[83] , \la_oenb_user[82] , \la_oenb_user[81] , \la_oenb_user[80] , \la_oenb_user[79] , \la_oenb_user[78] , \la_oenb_user[77] , \la_oenb_user[76] , \la_oenb_user[75] , \la_oenb_user[74] , \la_oenb_user[73] , \la_oenb_user[72] , \la_oenb_user[71] , \la_oenb_user[70] , \la_oenb_user[69] , \la_oenb_user[68] , \la_oenb_user[67] , \la_oenb_user[66] , \la_oenb_user[65] , \la_oenb_user[64] , \la_oenb_user[63] , \la_oenb_user[62] , \la_oenb_user[61] , \la_oenb_user[60] , \la_oenb_user[59] , \la_oenb_user[58] , \la_oenb_user[57] , \la_oenb_user[56] , \la_oenb_user[55] , \la_oenb_user[54] , \la_oenb_user[53] , \la_oenb_user[52] , \la_oenb_user[51] , \la_oenb_user[50] , \la_oenb_user[49] , \la_oenb_user[48] , \la_oenb_user[47] , \la_oenb_user[46] , \la_oenb_user[45] , \la_oenb_user[44] , \la_oenb_user[43] , \la_oenb_user[42] , \la_oenb_user[41] , \la_oenb_user[40] , \la_oenb_user[39] , \la_oenb_user[38] , \la_oenb_user[37] , \la_oenb_user[36] , \la_oenb_user[35] , \la_oenb_user[34] , \la_oenb_user[33] , \la_oenb_user[32] , \la_oenb_user[31] , \la_oenb_user[30] , \la_oenb_user[29] , \la_oenb_user[28] , \la_oenb_user[27] , \la_oenb_user[26] , \la_oenb_user[25] , \la_oenb_user[24] , \la_oenb_user[23] , \la_oenb_user[22] , \la_oenb_user[21] , \la_oenb_user[20] , \la_oenb_user[19] , \la_oenb_user[18] , \la_oenb_user[17] , \la_oenb_user[16] , \la_oenb_user[15] , \la_oenb_user[14] , \la_oenb_user[13] , \la_oenb_user[12] , \la_oenb_user[11] , \la_oenb_user[10] , \la_oenb_user[9] , \la_oenb_user[8] , \la_oenb_user[7] , \la_oenb_user[6] , \la_oenb_user[5] , \la_oenb_user[4] , \la_oenb_user[3] , \la_oenb_user[2] , \la_oenb_user[1] , \la_oenb_user[0]  }),
+    .la_oenb_mprj({ \la_oenb_mprj[127] , \la_oenb_mprj[126] , \la_oenb_mprj[125] , \la_oenb_mprj[124] , \la_oenb_mprj[123] , \la_oenb_mprj[122] , \la_oenb_mprj[121] , \la_oenb_mprj[120] , \la_oenb_mprj[119] , \la_oenb_mprj[118] , \la_oenb_mprj[117] , \la_oenb_mprj[116] , \la_oenb_mprj[115] , \la_oenb_mprj[114] , \la_oenb_mprj[113] , \la_oenb_mprj[112] , \la_oenb_mprj[111] , \la_oenb_mprj[110] , \la_oenb_mprj[109] , \la_oenb_mprj[108] , \la_oenb_mprj[107] , \la_oenb_mprj[106] , \la_oenb_mprj[105] , \la_oenb_mprj[104] , \la_oenb_mprj[103] , \la_oenb_mprj[102] , \la_oenb_mprj[101] , \la_oenb_mprj[100] , \la_oenb_mprj[99] , \la_oenb_mprj[98] , \la_oenb_mprj[97] , \la_oenb_mprj[96] , \la_oenb_mprj[95] , \la_oenb_mprj[94] , \la_oenb_mprj[93] , \la_oenb_mprj[92] , \la_oenb_mprj[91] , \la_oenb_mprj[90] , \la_oenb_mprj[89] , \la_oenb_mprj[88] , \la_oenb_mprj[87] , \la_oenb_mprj[86] , \la_oenb_mprj[85] , \la_oenb_mprj[84] , \la_oenb_mprj[83] , \la_oenb_mprj[82] , \la_oenb_mprj[81] , \la_oenb_mprj[80] , \la_oenb_mprj[79] , \la_oenb_mprj[78] , \la_oenb_mprj[77] , \la_oenb_mprj[76] , \la_oenb_mprj[75] , \la_oenb_mprj[74] , \la_oenb_mprj[73] , \la_oenb_mprj[72] , \la_oenb_mprj[71] , \la_oenb_mprj[70] , \la_oenb_mprj[69] , \la_oenb_mprj[68] , \la_oenb_mprj[67] , \la_oenb_mprj[66] , \la_oenb_mprj[65] , \la_oenb_mprj[64] , \la_oenb_mprj[63] , \la_oenb_mprj[62] , \la_oenb_mprj[61] , \la_oenb_mprj[60] , \la_oenb_mprj[59] , \la_oenb_mprj[58] , \la_oenb_mprj[57] , \la_oenb_mprj[56] , \la_oenb_mprj[55] , \la_oenb_mprj[54] , \la_oenb_mprj[53] , \la_oenb_mprj[52] , \la_oenb_mprj[51] , \la_oenb_mprj[50] , \la_oenb_mprj[49] , \la_oenb_mprj[48] , \la_oenb_mprj[47] , \la_oenb_mprj[46] , \la_oenb_mprj[45] , \la_oenb_mprj[44] , \la_oenb_mprj[43] , \la_oenb_mprj[42] , \la_oenb_mprj[41] , \la_oenb_mprj[40] , \la_oenb_mprj[39] , \la_oenb_mprj[38] , \la_oenb_mprj[37] , \la_oenb_mprj[36] , \la_oenb_mprj[35] , \la_oenb_mprj[34] , \la_oenb_mprj[33] , \la_oenb_mprj[32] , \la_oenb_mprj[31] , \la_oenb_mprj[30] , \la_oenb_mprj[29] , \la_oenb_mprj[28] , \la_oenb_mprj[27] , \la_oenb_mprj[26] , \la_oenb_mprj[25] , \la_oenb_mprj[24] , \la_oenb_mprj[23] , \la_oenb_mprj[22] , \la_oenb_mprj[21] , \la_oenb_mprj[20] , \la_oenb_mprj[19] , \la_oenb_mprj[18] , \la_oenb_mprj[17] , \la_oenb_mprj[16] , \la_oenb_mprj[15] , \la_oenb_mprj[14] , \la_oenb_mprj[13] , \la_oenb_mprj[12] , \la_oenb_mprj[11] , \la_oenb_mprj[10] , \la_oenb_mprj[9] , \la_oenb_mprj[8] , \la_oenb_mprj[7] , \la_oenb_mprj[6] , \la_oenb_mprj[5] , \la_oenb_mprj[4] , \la_oenb_mprj[3] , \la_oenb_mprj[2] , \la_oenb_mprj[1] , \la_oenb_mprj[0]  }),
+    .mprj_ack_i_core(mprj_ack_i_core),
+    .mprj_ack_i_user(mprj_ack_i_user),
+    .mprj_adr_o_core({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0]  }),
+    .mprj_adr_o_user({ \mprj_adr_o_user[31] , \mprj_adr_o_user[30] , \mprj_adr_o_user[29] , \mprj_adr_o_user[28] , \mprj_adr_o_user[27] , \mprj_adr_o_user[26] , \mprj_adr_o_user[25] , \mprj_adr_o_user[24] , \mprj_adr_o_user[23] , \mprj_adr_o_user[22] , \mprj_adr_o_user[21] , \mprj_adr_o_user[20] , \mprj_adr_o_user[19] , \mprj_adr_o_user[18] , \mprj_adr_o_user[17] , \mprj_adr_o_user[16] , \mprj_adr_o_user[15] , \mprj_adr_o_user[14] , \mprj_adr_o_user[13] , \mprj_adr_o_user[12] , \mprj_adr_o_user[11] , \mprj_adr_o_user[10] , \mprj_adr_o_user[9] , \mprj_adr_o_user[8] , \mprj_adr_o_user[7] , \mprj_adr_o_user[6] , \mprj_adr_o_user[5] , \mprj_adr_o_user[4] , \mprj_adr_o_user[3] , \mprj_adr_o_user[2] , \mprj_adr_o_user[1] , \mprj_adr_o_user[0]  }),
+    .mprj_cyc_o_core(mprj_cyc_o_core),
+    .mprj_cyc_o_user(mprj_cyc_o_user),
+    .mprj_dat_i_core({ \mprj_dat_i_core[31] , \mprj_dat_i_core[30] , \mprj_dat_i_core[29] , \mprj_dat_i_core[28] , \mprj_dat_i_core[27] , \mprj_dat_i_core[26] , \mprj_dat_i_core[25] , \mprj_dat_i_core[24] , \mprj_dat_i_core[23] , \mprj_dat_i_core[22] , \mprj_dat_i_core[21] , \mprj_dat_i_core[20] , \mprj_dat_i_core[19] , \mprj_dat_i_core[18] , \mprj_dat_i_core[17] , \mprj_dat_i_core[16] , \mprj_dat_i_core[15] , \mprj_dat_i_core[14] , \mprj_dat_i_core[13] , \mprj_dat_i_core[12] , \mprj_dat_i_core[11] , \mprj_dat_i_core[10] , \mprj_dat_i_core[9] , \mprj_dat_i_core[8] , \mprj_dat_i_core[7] , \mprj_dat_i_core[6] , \mprj_dat_i_core[5] , \mprj_dat_i_core[4] , \mprj_dat_i_core[3] , \mprj_dat_i_core[2] , \mprj_dat_i_core[1] , \mprj_dat_i_core[0]  }),
+    .mprj_dat_i_user({ \mprj_dat_i_user[31] , \mprj_dat_i_user[30] , \mprj_dat_i_user[29] , \mprj_dat_i_user[28] , \mprj_dat_i_user[27] , \mprj_dat_i_user[26] , \mprj_dat_i_user[25] , \mprj_dat_i_user[24] , \mprj_dat_i_user[23] , \mprj_dat_i_user[22] , \mprj_dat_i_user[21] , \mprj_dat_i_user[20] , \mprj_dat_i_user[19] , \mprj_dat_i_user[18] , \mprj_dat_i_user[17] , \mprj_dat_i_user[16] , \mprj_dat_i_user[15] , \mprj_dat_i_user[14] , \mprj_dat_i_user[13] , \mprj_dat_i_user[12] , \mprj_dat_i_user[11] , \mprj_dat_i_user[10] , \mprj_dat_i_user[9] , \mprj_dat_i_user[8] , \mprj_dat_i_user[7] , \mprj_dat_i_user[6] , \mprj_dat_i_user[5] , \mprj_dat_i_user[4] , \mprj_dat_i_user[3] , \mprj_dat_i_user[2] , \mprj_dat_i_user[1] , \mprj_dat_i_user[0]  }),
+    .mprj_dat_o_core({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0]  }),
+    .mprj_dat_o_user({ \mprj_dat_o_user[31] , \mprj_dat_o_user[30] , \mprj_dat_o_user[29] , \mprj_dat_o_user[28] , \mprj_dat_o_user[27] , \mprj_dat_o_user[26] , \mprj_dat_o_user[25] , \mprj_dat_o_user[24] , \mprj_dat_o_user[23] , \mprj_dat_o_user[22] , \mprj_dat_o_user[21] , \mprj_dat_o_user[20] , \mprj_dat_o_user[19] , \mprj_dat_o_user[18] , \mprj_dat_o_user[17] , \mprj_dat_o_user[16] , \mprj_dat_o_user[15] , \mprj_dat_o_user[14] , \mprj_dat_o_user[13] , \mprj_dat_o_user[12] , \mprj_dat_o_user[11] , \mprj_dat_o_user[10] , \mprj_dat_o_user[9] , \mprj_dat_o_user[8] , \mprj_dat_o_user[7] , \mprj_dat_o_user[6] , \mprj_dat_o_user[5] , \mprj_dat_o_user[4] , \mprj_dat_o_user[3] , \mprj_dat_o_user[2] , \mprj_dat_o_user[1] , \mprj_dat_o_user[0]  }),
+    .mprj_iena_wb(mprj_iena_wb),
+    .mprj_sel_o_core({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0]  }),
+    .mprj_sel_o_user({ \mprj_sel_o_user[3] , \mprj_sel_o_user[2] , \mprj_sel_o_user[1] , \mprj_sel_o_user[0]  }),
+    .mprj_stb_o_core(mprj_stb_o_core),
+    .mprj_stb_o_user(mprj_stb_o_user),
+    .mprj_we_o_core(mprj_we_o_core),
+    .mprj_we_o_user(mprj_we_o_user),
+    .user1_vcc_powergood(mprj_vcc_pwrgood),
+    .user1_vdd_powergood(mprj_vdd_pwrgood),
+    .user2_vcc_powergood(mprj2_vcc_pwrgood),
+    .user2_vdd_powergood(mprj2_vdd_pwrgood),
+    .user_clock(mprj_clock),
+    .user_clock2(mprj_clock2),
+    .user_irq({ \user_irq[2] , \user_irq[1] , \user_irq[0]  }),
+    .user_irq_core({ \user_irq_core[2] , \user_irq_core[1] , \user_irq_core[0]  }),
+    .user_irq_ena({ \user_irq_ena[2] , \user_irq_ena[1] , \user_irq_ena[0]  }),
+    .user_reset(mprj_reset),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vccd2(vccd2_core),
+    .vdda1(vdda1_core),
+    .vdda2(vdda2_core),
+    .vssa1(vssa1_core),
+    .vssa2(vssa2_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .vssd2(vssd2_core)
+  );
+  user_analog_project_wrapper mprj (
+    .gpio_analog({ \user_gpio_analog[17] , \user_gpio_analog[16] , \user_gpio_analog[15] , \user_gpio_analog[14] , \user_gpio_analog[13] , \user_gpio_analog[12] , \user_gpio_analog[11] , \user_gpio_analog[10] , \user_gpio_analog[9] , \user_gpio_analog[8] , \user_gpio_analog[7] , \user_gpio_analog[6] , \user_gpio_analog[5] , \user_gpio_analog[4] , \user_gpio_analog[3] , \user_gpio_analog[2] , \user_gpio_analog[1] , \user_gpio_analog[0]  }),
+    .gpio_noesd({ \user_gpio_noesd[17] , \user_gpio_noesd[16] , \user_gpio_noesd[15] , \user_gpio_noesd[14] , \user_gpio_noesd[13] , \user_gpio_noesd[12] , \user_gpio_noesd[11] , \user_gpio_noesd[10] , \user_gpio_noesd[9] , \user_gpio_noesd[8] , \user_gpio_noesd[7] , \user_gpio_noesd[6] , \user_gpio_noesd[5] , \user_gpio_noesd[4] , \user_gpio_noesd[3] , \user_gpio_noesd[2] , \user_gpio_noesd[1] , \user_gpio_noesd[0]  }),
+    .io_analog({ \user_analog[10] , \user_analog[9] , \user_analog[8] , \user_analog[7] , \user_analog[6] , \user_analog[5] , \user_analog[4] , \user_analog[3] , \user_analog[2] , \user_analog[1] , \user_analog[0]  }),
+    .io_clamp_high({ \user_clamp_high[2] , \user_clamp_high[1] , \user_clamp_high[0]  }),
+    .io_clamp_low({ \user_clamp_low[2] , \user_clamp_low[1] , \user_clamp_low[0]  }),
+    .io_in({ \user_io_in[26] , \user_io_in[25] , \user_io_in[24] , \user_io_in[23] , \user_io_in[22] , \user_io_in[21] , \user_io_in[20] , \user_io_in[19] , \user_io_in[18] , \user_io_in[17] , \user_io_in[16] , \user_io_in[15] , \user_io_in[14] , \user_io_in[13] , \user_io_in[12] , \user_io_in[11] , \user_io_in[10] , \user_io_in[9] , \user_io_in[8] , \user_io_in[7] , \user_io_in[6] , \user_io_in[5] , \user_io_in[4] , \user_io_in[3] , \user_io_in[2] , \user_io_in[1] , \user_io_in[0]  }),
+    .io_in_3v3({ \mprj_io_in_3v3[26] , \mprj_io_in_3v3[25] , \mprj_io_in_3v3[24] , \mprj_io_in_3v3[23] , \mprj_io_in_3v3[22] , \mprj_io_in_3v3[21] , \mprj_io_in_3v3[20] , \mprj_io_in_3v3[19] , \mprj_io_in_3v3[18] , \mprj_io_in_3v3[17] , \mprj_io_in_3v3[16] , \mprj_io_in_3v3[15] , \mprj_io_in_3v3[14] , \mprj_io_in_3v3[13] , \mprj_io_in_3v3[12] , \mprj_io_in_3v3[11] , \mprj_io_in_3v3[10] , \mprj_io_in_3v3[9] , \mprj_io_in_3v3[8] , \mprj_io_in_3v3[7] , \mprj_io_in_3v3[6] , \mprj_io_in_3v3[5] , \mprj_io_in_3v3[4] , \mprj_io_in_3v3[3] , \mprj_io_in_3v3[2] , \mprj_io_in_3v3[1] , \mprj_io_in_3v3[0]  }),
+    .io_oeb({ \user_io_oeb[26] , \user_io_oeb[25] , \user_io_oeb[24] , \user_io_oeb[23] , \user_io_oeb[22] , \user_io_oeb[21] , \user_io_oeb[20] , \user_io_oeb[19] , \user_io_oeb[18] , \user_io_oeb[17] , \user_io_oeb[16] , \user_io_oeb[15] , \user_io_oeb[14] , \user_io_oeb[13] , \user_io_oeb[12] , \user_io_oeb[11] , \user_io_oeb[10] , \user_io_oeb[9] , \user_io_oeb[8] , \user_io_oeb[7] , \user_io_oeb[6] , \user_io_oeb[5] , \user_io_oeb[4] , \user_io_oeb[3] , \user_io_oeb[2] , \user_io_oeb[1] , \user_io_oeb[0]  }),
+    .io_out({ \user_io_out[26] , \user_io_out[25] , \user_io_out[24] , \user_io_out[23] , \user_io_out[22] , \user_io_out[21] , \user_io_out[20] , \user_io_out[19] , \user_io_out[18] , \user_io_out[17] , \user_io_out[16] , \user_io_out[15] , \user_io_out[14] , \user_io_out[13] , \user_io_out[12] , \user_io_out[11] , \user_io_out[10] , \user_io_out[9] , \user_io_out[8] , \user_io_out[7] , \user_io_out[6] , \user_io_out[5] , \user_io_out[4] , \user_io_out[3] , \user_io_out[2] , \user_io_out[1] , \user_io_out[0]  }),
+    .la_data_in({ \la_data_in_user[127] , \la_data_in_user[126] , \la_data_in_user[125] , \la_data_in_user[124] , \la_data_in_user[123] , \la_data_in_user[122] , \la_data_in_user[121] , \la_data_in_user[120] , \la_data_in_user[119] , \la_data_in_user[118] , \la_data_in_user[117] , \la_data_in_user[116] , \la_data_in_user[115] , \la_data_in_user[114] , \la_data_in_user[113] , \la_data_in_user[112] , \la_data_in_user[111] , \la_data_in_user[110] , \la_data_in_user[109] , \la_data_in_user[108] , \la_data_in_user[107] , \la_data_in_user[106] , \la_data_in_user[105] , \la_data_in_user[104] , \la_data_in_user[103] , \la_data_in_user[102] , \la_data_in_user[101] , \la_data_in_user[100] , \la_data_in_user[99] , \la_data_in_user[98] , \la_data_in_user[97] , \la_data_in_user[96] , \la_data_in_user[95] , \la_data_in_user[94] , \la_data_in_user[93] , \la_data_in_user[92] , \la_data_in_user[91] , \la_data_in_user[90] , \la_data_in_user[89] , \la_data_in_user[88] , \la_data_in_user[87] , \la_data_in_user[86] , \la_data_in_user[85] , \la_data_in_user[84] , \la_data_in_user[83] , \la_data_in_user[82] , \la_data_in_user[81] , \la_data_in_user[80] , \la_data_in_user[79] , \la_data_in_user[78] , \la_data_in_user[77] , \la_data_in_user[76] , \la_data_in_user[75] , \la_data_in_user[74] , \la_data_in_user[73] , \la_data_in_user[72] , \la_data_in_user[71] , \la_data_in_user[70] , \la_data_in_user[69] , \la_data_in_user[68] , \la_data_in_user[67] , \la_data_in_user[66] , \la_data_in_user[65] , \la_data_in_user[64] , \la_data_in_user[63] , \la_data_in_user[62] , \la_data_in_user[61] , \la_data_in_user[60] , \la_data_in_user[59] , \la_data_in_user[58] , \la_data_in_user[57] , \la_data_in_user[56] , \la_data_in_user[55] , \la_data_in_user[54] , \la_data_in_user[53] , \la_data_in_user[52] , \la_data_in_user[51] , \la_data_in_user[50] , \la_data_in_user[49] , \la_data_in_user[48] , \la_data_in_user[47] , \la_data_in_user[46] , \la_data_in_user[45] , \la_data_in_user[44] , \la_data_in_user[43] , \la_data_in_user[42] , \la_data_in_user[41] , \la_data_in_user[40] , \la_data_in_user[39] , \la_data_in_user[38] , \la_data_in_user[37] , \la_data_in_user[36] , \la_data_in_user[35] , \la_data_in_user[34] , \la_data_in_user[33] , \la_data_in_user[32] , \la_data_in_user[31] , \la_data_in_user[30] , \la_data_in_user[29] , \la_data_in_user[28] , \la_data_in_user[27] , \la_data_in_user[26] , \la_data_in_user[25] , \la_data_in_user[24] , \la_data_in_user[23] , \la_data_in_user[22] , \la_data_in_user[21] , \la_data_in_user[20] , \la_data_in_user[19] , \la_data_in_user[18] , \la_data_in_user[17] , \la_data_in_user[16] , \la_data_in_user[15] , \la_data_in_user[14] , \la_data_in_user[13] , \la_data_in_user[12] , \la_data_in_user[11] , \la_data_in_user[10] , \la_data_in_user[9] , \la_data_in_user[8] , \la_data_in_user[7] , \la_data_in_user[6] , \la_data_in_user[5] , \la_data_in_user[4] , \la_data_in_user[3] , \la_data_in_user[2] , \la_data_in_user[1] , \la_data_in_user[0]  }),
+    .la_data_out({ \la_data_out_user[127] , \la_data_out_user[126] , \la_data_out_user[125] , \la_data_out_user[124] , \la_data_out_user[123] , \la_data_out_user[122] , \la_data_out_user[121] , \la_data_out_user[120] , \la_data_out_user[119] , \la_data_out_user[118] , \la_data_out_user[117] , \la_data_out_user[116] , \la_data_out_user[115] , \la_data_out_user[114] , \la_data_out_user[113] , \la_data_out_user[112] , \la_data_out_user[111] , \la_data_out_user[110] , \la_data_out_user[109] , \la_data_out_user[108] , \la_data_out_user[107] , \la_data_out_user[106] , \la_data_out_user[105] , \la_data_out_user[104] , \la_data_out_user[103] , \la_data_out_user[102] , \la_data_out_user[101] , \la_data_out_user[100] , \la_data_out_user[99] , \la_data_out_user[98] , \la_data_out_user[97] , \la_data_out_user[96] , \la_data_out_user[95] , \la_data_out_user[94] , \la_data_out_user[93] , \la_data_out_user[92] , \la_data_out_user[91] , \la_data_out_user[90] , \la_data_out_user[89] , \la_data_out_user[88] , \la_data_out_user[87] , \la_data_out_user[86] , \la_data_out_user[85] , \la_data_out_user[84] , \la_data_out_user[83] , \la_data_out_user[82] , \la_data_out_user[81] , \la_data_out_user[80] , \la_data_out_user[79] , \la_data_out_user[78] , \la_data_out_user[77] , \la_data_out_user[76] , \la_data_out_user[75] , \la_data_out_user[74] , \la_data_out_user[73] , \la_data_out_user[72] , \la_data_out_user[71] , \la_data_out_user[70] , \la_data_out_user[69] , \la_data_out_user[68] , \la_data_out_user[67] , \la_data_out_user[66] , \la_data_out_user[65] , \la_data_out_user[64] , \la_data_out_user[63] , \la_data_out_user[62] , \la_data_out_user[61] , \la_data_out_user[60] , \la_data_out_user[59] , \la_data_out_user[58] , \la_data_out_user[57] , \la_data_out_user[56] , \la_data_out_user[55] , \la_data_out_user[54] , \la_data_out_user[53] , \la_data_out_user[52] , \la_data_out_user[51] , \la_data_out_user[50] , \la_data_out_user[49] , \la_data_out_user[48] , \la_data_out_user[47] , \la_data_out_user[46] , \la_data_out_user[45] , \la_data_out_user[44] , \la_data_out_user[43] , \la_data_out_user[42] , \la_data_out_user[41] , \la_data_out_user[40] , \la_data_out_user[39] , \la_data_out_user[38] , \la_data_out_user[37] , \la_data_out_user[36] , \la_data_out_user[35] , \la_data_out_user[34] , \la_data_out_user[33] , \la_data_out_user[32] , \la_data_out_user[31] , \la_data_out_user[30] , \la_data_out_user[29] , \la_data_out_user[28] , \la_data_out_user[27] , \la_data_out_user[26] , \la_data_out_user[25] , \la_data_out_user[24] , \la_data_out_user[23] , \la_data_out_user[22] , \la_data_out_user[21] , \la_data_out_user[20] , \la_data_out_user[19] , \la_data_out_user[18] , \la_data_out_user[17] , \la_data_out_user[16] , \la_data_out_user[15] , \la_data_out_user[14] , \la_data_out_user[13] , \la_data_out_user[12] , \la_data_out_user[11] , \la_data_out_user[10] , \la_data_out_user[9] , \la_data_out_user[8] , \la_data_out_user[7] , \la_data_out_user[6] , \la_data_out_user[5] , \la_data_out_user[4] , \la_data_out_user[3] , \la_data_out_user[2] , \la_data_out_user[1] , \la_data_out_user[0]  }),
+    .la_oenb({ \la_oenb_user[127] , \la_oenb_user[126] , \la_oenb_user[125] , \la_oenb_user[124] , \la_oenb_user[123] , \la_oenb_user[122] , \la_oenb_user[121] , \la_oenb_user[120] , \la_oenb_user[119] , \la_oenb_user[118] , \la_oenb_user[117] , \la_oenb_user[116] , \la_oenb_user[115] , \la_oenb_user[114] , \la_oenb_user[113] , \la_oenb_user[112] , \la_oenb_user[111] , \la_oenb_user[110] , \la_oenb_user[109] , \la_oenb_user[108] , \la_oenb_user[107] , \la_oenb_user[106] , \la_oenb_user[105] , \la_oenb_user[104] , \la_oenb_user[103] , \la_oenb_user[102] , \la_oenb_user[101] , \la_oenb_user[100] , \la_oenb_user[99] , \la_oenb_user[98] , \la_oenb_user[97] , \la_oenb_user[96] , \la_oenb_user[95] , \la_oenb_user[94] , \la_oenb_user[93] , \la_oenb_user[92] , \la_oenb_user[91] , \la_oenb_user[90] , \la_oenb_user[89] , \la_oenb_user[88] , \la_oenb_user[87] , \la_oenb_user[86] , \la_oenb_user[85] , \la_oenb_user[84] , \la_oenb_user[83] , \la_oenb_user[82] , \la_oenb_user[81] , \la_oenb_user[80] , \la_oenb_user[79] , \la_oenb_user[78] , \la_oenb_user[77] , \la_oenb_user[76] , \la_oenb_user[75] , \la_oenb_user[74] , \la_oenb_user[73] , \la_oenb_user[72] , \la_oenb_user[71] , \la_oenb_user[70] , \la_oenb_user[69] , \la_oenb_user[68] , \la_oenb_user[67] , \la_oenb_user[66] , \la_oenb_user[65] , \la_oenb_user[64] , \la_oenb_user[63] , \la_oenb_user[62] , \la_oenb_user[61] , \la_oenb_user[60] , \la_oenb_user[59] , \la_oenb_user[58] , \la_oenb_user[57] , \la_oenb_user[56] , \la_oenb_user[55] , \la_oenb_user[54] , \la_oenb_user[53] , \la_oenb_user[52] , \la_oenb_user[51] , \la_oenb_user[50] , \la_oenb_user[49] , \la_oenb_user[48] , \la_oenb_user[47] , \la_oenb_user[46] , \la_oenb_user[45] , \la_oenb_user[44] , \la_oenb_user[43] , \la_oenb_user[42] , \la_oenb_user[41] , \la_oenb_user[40] , \la_oenb_user[39] , \la_oenb_user[38] , \la_oenb_user[37] , \la_oenb_user[36] , \la_oenb_user[35] , \la_oenb_user[34] , \la_oenb_user[33] , \la_oenb_user[32] , \la_oenb_user[31] , \la_oenb_user[30] , \la_oenb_user[29] , \la_oenb_user[28] , \la_oenb_user[27] , \la_oenb_user[26] , \la_oenb_user[25] , \la_oenb_user[24] , \la_oenb_user[23] , \la_oenb_user[22] , \la_oenb_user[21] , \la_oenb_user[20] , \la_oenb_user[19] , \la_oenb_user[18] , \la_oenb_user[17] , \la_oenb_user[16] , \la_oenb_user[15] , \la_oenb_user[14] , \la_oenb_user[13] , \la_oenb_user[12] , \la_oenb_user[11] , \la_oenb_user[10] , \la_oenb_user[9] , \la_oenb_user[8] , \la_oenb_user[7] , \la_oenb_user[6] , \la_oenb_user[5] , \la_oenb_user[4] , \la_oenb_user[3] , \la_oenb_user[2] , \la_oenb_user[1] , \la_oenb_user[0]  }),
+    .user_clock2(mprj_clock2),
+    .user_irq({ \user_irq_core[2] , \user_irq_core[1] , \user_irq_core[0]  }),
+    .vccd1(vccd1_core),
+    .vccd2(vccd2_core),
+    .vdda1(vdda1_core),
+    .vdda2(vdda2_core),
+    .vssa1(vssa1_core),
+    .vssa2(vssa2_core),
+    .vssd1(vssd1_core),
+    .vssd2(vssd2_core),
+    .wb_clk_i(mprj_clock),
+    .wb_rst_i(mprj_reset),
+    .wbs_ack_o(mprj_ack_i_user),
+    .wbs_adr_i({ \mprj_adr_o_user[31] , \mprj_adr_o_user[30] , \mprj_adr_o_user[29] , \mprj_adr_o_user[28] , \mprj_adr_o_user[27] , \mprj_adr_o_user[26] , \mprj_adr_o_user[25] , \mprj_adr_o_user[24] , \mprj_adr_o_user[23] , \mprj_adr_o_user[22] , \mprj_adr_o_user[21] , \mprj_adr_o_user[20] , \mprj_adr_o_user[19] , \mprj_adr_o_user[18] , \mprj_adr_o_user[17] , \mprj_adr_o_user[16] , \mprj_adr_o_user[15] , \mprj_adr_o_user[14] , \mprj_adr_o_user[13] , \mprj_adr_o_user[12] , \mprj_adr_o_user[11] , \mprj_adr_o_user[10] , \mprj_adr_o_user[9] , \mprj_adr_o_user[8] , \mprj_adr_o_user[7] , \mprj_adr_o_user[6] , \mprj_adr_o_user[5] , \mprj_adr_o_user[4] , \mprj_adr_o_user[3] , \mprj_adr_o_user[2] , \mprj_adr_o_user[1] , \mprj_adr_o_user[0]  }),
+    .wbs_cyc_i(mprj_cyc_o_user),
+    .wbs_dat_i({ \mprj_dat_o_user[31] , \mprj_dat_o_user[30] , \mprj_dat_o_user[29] , \mprj_dat_o_user[28] , \mprj_dat_o_user[27] , \mprj_dat_o_user[26] , \mprj_dat_o_user[25] , \mprj_dat_o_user[24] , \mprj_dat_o_user[23] , \mprj_dat_o_user[22] , \mprj_dat_o_user[21] , \mprj_dat_o_user[20] , \mprj_dat_o_user[19] , \mprj_dat_o_user[18] , \mprj_dat_o_user[17] , \mprj_dat_o_user[16] , \mprj_dat_o_user[15] , \mprj_dat_o_user[14] , \mprj_dat_o_user[13] , \mprj_dat_o_user[12] , \mprj_dat_o_user[11] , \mprj_dat_o_user[10] , \mprj_dat_o_user[9] , \mprj_dat_o_user[8] , \mprj_dat_o_user[7] , \mprj_dat_o_user[6] , \mprj_dat_o_user[5] , \mprj_dat_o_user[4] , \mprj_dat_o_user[3] , \mprj_dat_o_user[2] , \mprj_dat_o_user[1] , \mprj_dat_o_user[0]  }),
+    .wbs_dat_o({ \mprj_dat_i_user[31] , \mprj_dat_i_user[30] , \mprj_dat_i_user[29] , \mprj_dat_i_user[28] , \mprj_dat_i_user[27] , \mprj_dat_i_user[26] , \mprj_dat_i_user[25] , \mprj_dat_i_user[24] , \mprj_dat_i_user[23] , \mprj_dat_i_user[22] , \mprj_dat_i_user[21] , \mprj_dat_i_user[20] , \mprj_dat_i_user[19] , \mprj_dat_i_user[18] , \mprj_dat_i_user[17] , \mprj_dat_i_user[16] , \mprj_dat_i_user[15] , \mprj_dat_i_user[14] , \mprj_dat_i_user[13] , \mprj_dat_i_user[12] , \mprj_dat_i_user[11] , \mprj_dat_i_user[10] , \mprj_dat_i_user[9] , \mprj_dat_i_user[8] , \mprj_dat_i_user[7] , \mprj_dat_i_user[6] , \mprj_dat_i_user[5] , \mprj_dat_i_user[4] , \mprj_dat_i_user[3] , \mprj_dat_i_user[2] , \mprj_dat_i_user[1] , \mprj_dat_i_user[0]  }),
+    .wbs_sel_i({ \mprj_sel_o_user[3] , \mprj_sel_o_user[2] , \mprj_sel_o_user[1] , \mprj_sel_o_user[0]  }),
+    .wbs_stb_i(mprj_stb_o_user),
+    .wbs_we_i(mprj_we_o_user)
+  );
+  chip_io_alt padframe (
+    .clock(clock),
+    .clock_core(clock_core),
+    .flash_clk(flash_clk),
+    .flash_clk_core(flash_clk_frame),
+    .flash_clk_ieb_core(flash_clk_ieb),
+    .flash_clk_oeb_core(flash_clk_oeb),
+    .flash_csb(flash_csb),
+    .flash_csb_core(flash_csb_frame),
+    .flash_csb_ieb_core(flash_csb_ieb),
+    .flash_csb_oeb_core(flash_csb_oeb),
+    .flash_io0(flash_io0),
+    .flash_io0_di_core(flash_io0_di),
+    .flash_io0_do_core(flash_io0_do),
+    .flash_io0_ieb_core(flash_io0_ieb),
+    .flash_io0_oeb_core(flash_io0_oeb),
+    .flash_io1(flash_io1),
+    .flash_io1_di_core(flash_io1_di),
+    .flash_io1_do_core(flash_io1_do),
+    .flash_io1_ieb_core(flash_io1_ieb),
+    .flash_io1_oeb_core(flash_io1_oeb),
+    .gpio(gpio),
+    .gpio_in_core(gpio_in_core),
+    .gpio_inenb_core(gpio_inenb_core),
+    .gpio_mode0_core(gpio_mode0_core),
+    .gpio_mode1_core(gpio_mode1_core),
+    .gpio_out_core(gpio_out_core),
+    .gpio_outenb_core(gpio_outenb_core),
+    .mprj_analog({ \user_analog[10] , \user_analog[9] , \user_analog[8] , \user_analog[7] , \user_analog[6] , \user_analog[5] , \user_analog[4] , \user_analog[3] , \user_analog[2] , \user_analog[1] , \user_analog[0]  }),
+    .mprj_clamp_high({ \user_clamp_high[2] , \user_clamp_high[1] , \user_clamp_high[0]  }),
+    .mprj_clamp_low({ \user_clamp_low[2] , \user_clamp_low[1] , \user_clamp_low[0]  }),
+    .mprj_gpio_analog({ \user_gpio_analog[17] , \user_gpio_analog[16] , \user_gpio_analog[15] , \user_gpio_analog[14] , \user_gpio_analog[13] , \user_gpio_analog[12] , \user_gpio_analog[11] , \user_gpio_analog[10] , \user_gpio_analog[9] , \user_gpio_analog[8] , \user_gpio_analog[7] , \user_gpio_analog[6] , \user_gpio_analog[5] , \user_gpio_analog[4] , \user_gpio_analog[3] , \user_gpio_analog[2] , \user_gpio_analog[1] , \user_gpio_analog[0]  }),
+    .mprj_gpio_noesd({ \user_gpio_noesd[17] , \user_gpio_noesd[16] , \user_gpio_noesd[15] , \user_gpio_noesd[14] , \user_gpio_noesd[13] , \user_gpio_noesd[12] , \user_gpio_noesd[11] , \user_gpio_noesd[10] , \user_gpio_noesd[9] , \user_gpio_noesd[8] , \user_gpio_noesd[7] , \user_gpio_noesd[6] , \user_gpio_noesd[5] , \user_gpio_noesd[4] , \user_gpio_noesd[3] , \user_gpio_noesd[2] , \user_gpio_noesd[1] , \user_gpio_noesd[0]  }),
+    .mprj_io(mprj_io),
+    .mprj_io_analog_en({ \mprj_io_analog_en[26] , \mprj_io_analog_en[25] , \mprj_io_analog_en[24] , \mprj_io_analog_en[23] , \mprj_io_analog_en[22] , \mprj_io_analog_en[21] , \mprj_io_analog_en[20] , \mprj_io_analog_en[19] , \mprj_io_analog_en[18] , \mprj_io_analog_en[17] , \mprj_io_analog_en[16] , \mprj_io_analog_en[15] , \mprj_io_analog_en[14] , \mprj_io_analog_en[13] , \mprj_io_analog_en[12] , \mprj_io_analog_en[11] , \mprj_io_analog_en[10] , \mprj_io_analog_en[9] , \mprj_io_analog_en[8] , \mprj_io_analog_en[7] , \mprj_io_analog_en[6] , \mprj_io_analog_en[5] , \mprj_io_analog_en[4] , \mprj_io_analog_en[3] , \mprj_io_analog_en[2] , \mprj_io_analog_en[1] , \mprj_io_analog_en[0]  }),
+    .mprj_io_analog_pol({ \mprj_io_analog_pol[26] , \mprj_io_analog_pol[25] , \mprj_io_analog_pol[24] , \mprj_io_analog_pol[23] , \mprj_io_analog_pol[22] , \mprj_io_analog_pol[21] , \mprj_io_analog_pol[20] , \mprj_io_analog_pol[19] , \mprj_io_analog_pol[18] , \mprj_io_analog_pol[17] , \mprj_io_analog_pol[16] , \mprj_io_analog_pol[15] , \mprj_io_analog_pol[14] , \mprj_io_analog_pol[13] , \mprj_io_analog_pol[12] , \mprj_io_analog_pol[11] , \mprj_io_analog_pol[10] , \mprj_io_analog_pol[9] , \mprj_io_analog_pol[8] , \mprj_io_analog_pol[7] , \mprj_io_analog_pol[6] , \mprj_io_analog_pol[5] , \mprj_io_analog_pol[4] , \mprj_io_analog_pol[3] , \mprj_io_analog_pol[2] , \mprj_io_analog_pol[1] , \mprj_io_analog_pol[0]  }),
+    .mprj_io_analog_sel({ \mprj_io_analog_sel[26] , \mprj_io_analog_sel[25] , \mprj_io_analog_sel[24] , \mprj_io_analog_sel[23] , \mprj_io_analog_sel[22] , \mprj_io_analog_sel[21] , \mprj_io_analog_sel[20] , \mprj_io_analog_sel[19] , \mprj_io_analog_sel[18] , \mprj_io_analog_sel[17] , \mprj_io_analog_sel[16] , \mprj_io_analog_sel[15] , \mprj_io_analog_sel[14] , \mprj_io_analog_sel[13] , \mprj_io_analog_sel[12] , \mprj_io_analog_sel[11] , \mprj_io_analog_sel[10] , \mprj_io_analog_sel[9] , \mprj_io_analog_sel[8] , \mprj_io_analog_sel[7] , \mprj_io_analog_sel[6] , \mprj_io_analog_sel[5] , \mprj_io_analog_sel[4] , \mprj_io_analog_sel[3] , \mprj_io_analog_sel[2] , \mprj_io_analog_sel[1] , \mprj_io_analog_sel[0]  }),
+    .mprj_io_dm({ \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78] , \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75] , \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72] , \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69] , \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66] , \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63] , \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60] , \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57] , \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54] , \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51] , \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48] , \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45] , \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42] , \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39] , \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36] , \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33] , \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30] , \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27] , \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24] , \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21] , \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18] , \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15] , \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12] , \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9] , \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6] , \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3] , \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0]  }),
+    .mprj_io_holdover({ \mprj_io_holdover[26] , \mprj_io_holdover[25] , \mprj_io_holdover[24] , \mprj_io_holdover[23] , \mprj_io_holdover[22] , \mprj_io_holdover[21] , \mprj_io_holdover[20] , \mprj_io_holdover[19] , \mprj_io_holdover[18] , \mprj_io_holdover[17] , \mprj_io_holdover[16] , \mprj_io_holdover[15] , \mprj_io_holdover[14] , \mprj_io_holdover[13] , \mprj_io_holdover[12] , \mprj_io_holdover[11] , \mprj_io_holdover[10] , \mprj_io_holdover[9] , \mprj_io_holdover[8] , \mprj_io_holdover[7] , \mprj_io_holdover[6] , \mprj_io_holdover[5] , \mprj_io_holdover[4] , \mprj_io_holdover[3] , \mprj_io_holdover[2] , \mprj_io_holdover[1] , \mprj_io_holdover[0]  }),
+    .mprj_io_ib_mode_sel({ \mprj_io_ib_mode_sel[26] , \mprj_io_ib_mode_sel[25] , \mprj_io_ib_mode_sel[24] , \mprj_io_ib_mode_sel[23] , \mprj_io_ib_mode_sel[22] , \mprj_io_ib_mode_sel[21] , \mprj_io_ib_mode_sel[20] , \mprj_io_ib_mode_sel[19] , \mprj_io_ib_mode_sel[18] , \mprj_io_ib_mode_sel[17] , \mprj_io_ib_mode_sel[16] , \mprj_io_ib_mode_sel[15] , \mprj_io_ib_mode_sel[14] , \mprj_io_ib_mode_sel[13] , \mprj_io_ib_mode_sel[12] , \mprj_io_ib_mode_sel[11] , \mprj_io_ib_mode_sel[10] , \mprj_io_ib_mode_sel[9] , \mprj_io_ib_mode_sel[8] , \mprj_io_ib_mode_sel[7] , \mprj_io_ib_mode_sel[6] , \mprj_io_ib_mode_sel[5] , \mprj_io_ib_mode_sel[4] , \mprj_io_ib_mode_sel[3] , \mprj_io_ib_mode_sel[2] , \mprj_io_ib_mode_sel[1] , \mprj_io_ib_mode_sel[0]  }),
+    .mprj_io_in({ \mprj_io_in[26] , \mprj_io_in[25] , \mprj_io_in[24] , \mprj_io_in[23] , \mprj_io_in[22] , \mprj_io_in[21] , \mprj_io_in[20] , \mprj_io_in[19] , \mprj_io_in[18] , \mprj_io_in[17] , \mprj_io_in[16] , \mprj_io_in[15] , \mprj_io_in[14] , \mprj_io_in[13] , \mprj_io_in[12] , \mprj_io_in[11] , \mprj_io_in[10] , \mprj_io_in[9] , \mprj_io_in[8] , \mprj_io_in[7] , \mprj_io_in[6] , \mprj_io_in[5] , \mprj_io_in[4] , \mprj_io_in[3] , \mprj_io_in[2] , \mprj_io_in[1] , \mprj_io_in[0]  }),
+    .mprj_io_in_3v3({ \mprj_io_in_3v3[26] , \mprj_io_in_3v3[25] , \mprj_io_in_3v3[24] , \mprj_io_in_3v3[23] , \mprj_io_in_3v3[22] , \mprj_io_in_3v3[21] , \mprj_io_in_3v3[20] , \mprj_io_in_3v3[19] , \mprj_io_in_3v3[18] , \mprj_io_in_3v3[17] , \mprj_io_in_3v3[16] , \mprj_io_in_3v3[15] , \mprj_io_in_3v3[14] , \mprj_io_in_3v3[13] , \mprj_io_in_3v3[12] , \mprj_io_in_3v3[11] , \mprj_io_in_3v3[10] , \mprj_io_in_3v3[9] , \mprj_io_in_3v3[8] , \mprj_io_in_3v3[7] , \mprj_io_in_3v3[6] , \mprj_io_in_3v3[5] , \mprj_io_in_3v3[4] , \mprj_io_in_3v3[3] , \mprj_io_in_3v3[2] , \mprj_io_in_3v3[1] , \mprj_io_in_3v3[0]  }),
+    .mprj_io_inp_dis({ \mprj_io_inp_dis[26] , \mprj_io_inp_dis[25] , \mprj_io_inp_dis[24] , \mprj_io_inp_dis[23] , \mprj_io_inp_dis[22] , \mprj_io_inp_dis[21] , \mprj_io_inp_dis[20] , \mprj_io_inp_dis[19] , \mprj_io_inp_dis[18] , \mprj_io_inp_dis[17] , \mprj_io_inp_dis[16] , \mprj_io_inp_dis[15] , \mprj_io_inp_dis[14] , \mprj_io_inp_dis[13] , \mprj_io_inp_dis[12] , \mprj_io_inp_dis[11] , \mprj_io_inp_dis[10] , \mprj_io_inp_dis[9] , \mprj_io_inp_dis[8] , \mprj_io_inp_dis[7] , \mprj_io_inp_dis[6] , \mprj_io_inp_dis[5] , \mprj_io_inp_dis[4] , \mprj_io_inp_dis[3] , \mprj_io_inp_dis[2] , \mprj_io_inp_dis[1] , \mprj_io_inp_dis[0]  }),
+    .mprj_io_oeb({ \mprj_io_oeb[26] , \mprj_io_oeb[25] , \mprj_io_oeb[24] , \mprj_io_oeb[23] , \mprj_io_oeb[22] , \mprj_io_oeb[21] , \mprj_io_oeb[20] , \mprj_io_oeb[19] , \mprj_io_oeb[18] , \mprj_io_oeb[17] , \mprj_io_oeb[16] , \mprj_io_oeb[15] , \mprj_io_oeb[14] , \mprj_io_oeb[13] , \mprj_io_oeb[12] , \mprj_io_oeb[11] , \mprj_io_oeb[10] , \mprj_io_oeb[9] , \mprj_io_oeb[8] , \mprj_io_oeb[7] , \mprj_io_oeb[6] , \mprj_io_oeb[5] , \mprj_io_oeb[4] , \mprj_io_oeb[3] , \mprj_io_oeb[2] , \mprj_io_oeb[1] , \mprj_io_oeb[0]  }),
+    .mprj_io_out({ \mprj_io_out[26] , \mprj_io_out[25] , \mprj_io_out[24] , \mprj_io_out[23] , \mprj_io_out[22] , \mprj_io_out[21] , \mprj_io_out[20] , \mprj_io_out[19] , \mprj_io_out[18] , \mprj_io_out[17] , \mprj_io_out[16] , \mprj_io_out[15] , \mprj_io_out[14] , \mprj_io_out[13] , \mprj_io_out[12] , \mprj_io_out[11] , \mprj_io_out[10] , \mprj_io_out[9] , \mprj_io_out[8] , \mprj_io_out[7] , \mprj_io_out[6] , \mprj_io_out[5] , \mprj_io_out[4] , \mprj_io_out[3] , \mprj_io_out[2] , \mprj_io_out[1] , \mprj_io_out[0]  }),
+    .mprj_io_slow_sel({ \mprj_io_slow_sel[26] , \mprj_io_slow_sel[25] , \mprj_io_slow_sel[24] , \mprj_io_slow_sel[23] , \mprj_io_slow_sel[22] , \mprj_io_slow_sel[21] , \mprj_io_slow_sel[20] , \mprj_io_slow_sel[19] , \mprj_io_slow_sel[18] , \mprj_io_slow_sel[17] , \mprj_io_slow_sel[16] , \mprj_io_slow_sel[15] , \mprj_io_slow_sel[14] , \mprj_io_slow_sel[13] , \mprj_io_slow_sel[12] , \mprj_io_slow_sel[11] , \mprj_io_slow_sel[10] , \mprj_io_slow_sel[9] , \mprj_io_slow_sel[8] , \mprj_io_slow_sel[7] , \mprj_io_slow_sel[6] , \mprj_io_slow_sel[5] , \mprj_io_slow_sel[4] , \mprj_io_slow_sel[3] , \mprj_io_slow_sel[2] , \mprj_io_slow_sel[1] , \mprj_io_slow_sel[0]  }),
+    .mprj_io_vtrip_sel({ \mprj_io_vtrip_sel[26] , \mprj_io_vtrip_sel[25] , \mprj_io_vtrip_sel[24] , \mprj_io_vtrip_sel[23] , \mprj_io_vtrip_sel[22] , \mprj_io_vtrip_sel[21] , \mprj_io_vtrip_sel[20] , \mprj_io_vtrip_sel[19] , \mprj_io_vtrip_sel[18] , \mprj_io_vtrip_sel[17] , \mprj_io_vtrip_sel[16] , \mprj_io_vtrip_sel[15] , \mprj_io_vtrip_sel[14] , \mprj_io_vtrip_sel[13] , \mprj_io_vtrip_sel[12] , \mprj_io_vtrip_sel[11] , \mprj_io_vtrip_sel[10] , \mprj_io_vtrip_sel[9] , \mprj_io_vtrip_sel[8] , \mprj_io_vtrip_sel[7] , \mprj_io_vtrip_sel[6] , \mprj_io_vtrip_sel[5] , \mprj_io_vtrip_sel[4] , \mprj_io_vtrip_sel[3] , \mprj_io_vtrip_sel[2] , \mprj_io_vtrip_sel[1] , \mprj_io_vtrip_sel[0]  }),
+    .por(por_l),
+    .porb_h(porb_h),
+    .resetb(resetb),
+    .resetb_core_h(rstb_h),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vccd1_pad(vccd1),
+    .vccd2(vccd2_core),
+    .vccd2_pad(vccd2),
+    .vccd_pad(vccd),
+    .vdda(vdda_core),
+    .vdda1(vdda1_core),
+    .vdda1_pad(vdda1),
+    .vdda1_pad2(vdda1_2),
+    .vdda2(vdda2_core),
+    .vdda2_pad(vdda2),
+    .vdda_pad(vdda),
+    .vddio(vddio_core),
+    .vddio_pad(vddio),
+    .vddio_pad2(vddio_2),
+    .vssa(vssa_core),
+    .vssa1(vssa1_core),
+    .vssa1_pad(vssa1),
+    .vssa1_pad2(vssa1_2),
+    .vssa2(vssa2_core),
+    .vssa2_pad(vssa2),
+    .vssa_pad(vssa),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .vssd1_pad(vssd1),
+    .vssd2(vssd2_core),
+    .vssd2_pad(vssd2),
+    .vssd_pad(vssd),
+    .vssio(vssio_core),
+    .vssio_pad(vssio),
+    .vssio_pad2(vssio_2)
+  );
+  digital_pll pll (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .clockp({ pll_clk, pll_clk90 }),
+    .dco(spi_pll_dco_ena),
+    .div({ \spi_pll_div[4] , \spi_pll_div[3] , \spi_pll_div[2] , \spi_pll_div[1] , \spi_pll_div[0]  }),
+    .enable(spi_pll_ena),
+    .ext_trim({ \spi_pll_trim[25] , \spi_pll_trim[24] , \spi_pll_trim[23] , \spi_pll_trim[22] , \spi_pll_trim[21] , \spi_pll_trim[20] , \spi_pll_trim[19] , \spi_pll_trim[18] , \spi_pll_trim[17] , \spi_pll_trim[16] , \spi_pll_trim[15] , \spi_pll_trim[14] , \spi_pll_trim[13] , \spi_pll_trim[12] , \spi_pll_trim[11] , \spi_pll_trim[10] , \spi_pll_trim[9] , \spi_pll_trim[8] , \spi_pll_trim[7] , \spi_pll_trim[6] , \spi_pll_trim[5] , \spi_pll_trim[4] , \spi_pll_trim[3] , \spi_pll_trim[2] , \spi_pll_trim[1] , \spi_pll_trim[0]  }),
+    .osc(clock_core),
+    .resetb(rstb_l)
+  );
+  simple_por por (
+    .por_l(por_l),
+    .porb_h(porb_h),
+    .porb_l(porb_l),
+    .vdd1v8(vccd_core),
+    .vdd3v3(vddio_core),
+    .vss3v3(vssio_core),
+    .vss1v8(vssd_core)
+  );
+  xres_buf rstb_level (
+    .A(rstb_h),
+    .LVGND(vssd_core),
+    .LVPWR(vccd_core),
+    .VGND(vssio_core),
+    .VPWR(vddio_core),
+    .X(rstb_l)
+  );
+  mgmt_core_wrapper soc (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .core_clk(caravel_clk),
+    .core_rstn(caravel_rstn),
+    .debug_in(debug_in),
+    .debug_mode(debug_mode),
+    .debug_oeb(debug_oeb),
+    .debug_out(debug_out),
+    .flash_clk(flash_clk_core),
+    .flash_csb(flash_csb_core),
+    .flash_io0_di(flash_io0_di_core),
+    .flash_io0_do(flash_io0_do_core),
+    .flash_io0_oeb(flash_io0_oeb_core),
+    .flash_io1_di(flash_io1_di_core),
+    .flash_io1_do(flash_io1_do_core),
+    .flash_io1_oeb(flash_io1_oeb_core),
+    .flash_io2_di(flash_io2_di_core),
+    .flash_io2_do(flash_io2_do_core),
+    .flash_io2_oeb(flash_io2_oeb_core),
+    .flash_io3_di(flash_io3_di_core),
+    .flash_io3_do(flash_io3_do_core),
+    .flash_io3_oeb(flash_io3_oeb_core),
+    .gpio_in_pad(gpio_in_core),
+    .gpio_inenb_pad(gpio_inenb_core),
+    .gpio_mode0_pad(gpio_mode0_core),
+    .gpio_mode1_pad(gpio_mode1_core),
+    .gpio_out_pad(gpio_out_core),
+    .gpio_outenb_pad(gpio_outenb_core),
+    .hk_ack_i(hk_ack_i),
+    .hk_dat_i({ \hk_dat_i[31] , \hk_dat_i[30] , \hk_dat_i[29] , \hk_dat_i[28] , \hk_dat_i[27] , \hk_dat_i[26] , \hk_dat_i[25] , \hk_dat_i[24] , \hk_dat_i[23] , \hk_dat_i[22] , \hk_dat_i[21] , \hk_dat_i[20] , \hk_dat_i[19] , \hk_dat_i[18] , \hk_dat_i[17] , \hk_dat_i[16] , \hk_dat_i[15] , \hk_dat_i[14] , \hk_dat_i[13] , \hk_dat_i[12] , \hk_dat_i[11] , \hk_dat_i[10] , \hk_dat_i[9] , \hk_dat_i[8] , \hk_dat_i[7] , \hk_dat_i[6] , \hk_dat_i[5] , \hk_dat_i[4] , \hk_dat_i[3] , \hk_dat_i[2] , \hk_dat_i[1] , \hk_dat_i[0]  }),
+    .hk_stb_o(hk_stb_o),
+    .hk_cyc_o(hk_cyc_o),
+    .irq({ \irq_spi[2] , \irq_spi[1] , \irq_spi[0] , \user_irq[2] , \user_irq[1] , \user_irq[0]  }),
+    .la_iena({ \la_iena_mprj[127] , \la_iena_mprj[126] , \la_iena_mprj[125] , \la_iena_mprj[124] , \la_iena_mprj[123] , \la_iena_mprj[122] , \la_iena_mprj[121] , \la_iena_mprj[120] , \la_iena_mprj[119] , \la_iena_mprj[118] , \la_iena_mprj[117] , \la_iena_mprj[116] , \la_iena_mprj[115] , \la_iena_mprj[114] , \la_iena_mprj[113] , \la_iena_mprj[112] , \la_iena_mprj[111] , \la_iena_mprj[110] , \la_iena_mprj[109] , \la_iena_mprj[108] , \la_iena_mprj[107] , \la_iena_mprj[106] , \la_iena_mprj[105] , \la_iena_mprj[104] , \la_iena_mprj[103] , \la_iena_mprj[102] , \la_iena_mprj[101] , \la_iena_mprj[100] , \la_iena_mprj[99] , \la_iena_mprj[98] , \la_iena_mprj[97] , \la_iena_mprj[96] , \la_iena_mprj[95] , \la_iena_mprj[94] , \la_iena_mprj[93] , \la_iena_mprj[92] , \la_iena_mprj[91] , \la_iena_mprj[90] , \la_iena_mprj[89] , \la_iena_mprj[88] , \la_iena_mprj[87] , \la_iena_mprj[86] , \la_iena_mprj[85] , \la_iena_mprj[84] , \la_iena_mprj[83] , \la_iena_mprj[82] , \la_iena_mprj[81] , \la_iena_mprj[80] , \la_iena_mprj[79] , \la_iena_mprj[78] , \la_iena_mprj[77] , \la_iena_mprj[76] , \la_iena_mprj[75] , \la_iena_mprj[74] , \la_iena_mprj[73] , \la_iena_mprj[72] , \la_iena_mprj[71] , \la_iena_mprj[70] , \la_iena_mprj[69] , \la_iena_mprj[68] , \la_iena_mprj[67] , \la_iena_mprj[66] , \la_iena_mprj[65] , \la_iena_mprj[64] , \la_iena_mprj[63] , \la_iena_mprj[62] , \la_iena_mprj[61] , \la_iena_mprj[60] , \la_iena_mprj[59] , \la_iena_mprj[58] , \la_iena_mprj[57] , \la_iena_mprj[56] , \la_iena_mprj[55] , \la_iena_mprj[54] , \la_iena_mprj[53] , \la_iena_mprj[52] , \la_iena_mprj[51] , \la_iena_mprj[50] , \la_iena_mprj[49] , \la_iena_mprj[48] , \la_iena_mprj[47] , \la_iena_mprj[46] , \la_iena_mprj[45] , \la_iena_mprj[44] , \la_iena_mprj[43] , \la_iena_mprj[42] , \la_iena_mprj[41] , \la_iena_mprj[40] , \la_iena_mprj[39] , \la_iena_mprj[38] , \la_iena_mprj[37] , \la_iena_mprj[36] , \la_iena_mprj[35] , \la_iena_mprj[34] , \la_iena_mprj[33] , \la_iena_mprj[32] , \la_iena_mprj[31] , \la_iena_mprj[30] , \la_iena_mprj[29] , \la_iena_mprj[28] , \la_iena_mprj[27] , \la_iena_mprj[26] , \la_iena_mprj[25] , \la_iena_mprj[24] , \la_iena_mprj[23] , \la_iena_mprj[22] , \la_iena_mprj[21] , \la_iena_mprj[20] , \la_iena_mprj[19] , \la_iena_mprj[18] , \la_iena_mprj[17] , \la_iena_mprj[16] , \la_iena_mprj[15] , \la_iena_mprj[14] , \la_iena_mprj[13] , \la_iena_mprj[12] , \la_iena_mprj[11] , \la_iena_mprj[10] , \la_iena_mprj[9] , \la_iena_mprj[8] , \la_iena_mprj[7] , \la_iena_mprj[6] , \la_iena_mprj[5] , \la_iena_mprj[4] , \la_iena_mprj[3] , \la_iena_mprj[2] , \la_iena_mprj[1] , \la_iena_mprj[0]  }),
+    .la_input({ \la_data_in_mprj[127] , \la_data_in_mprj[126] , \la_data_in_mprj[125] , \la_data_in_mprj[124] , \la_data_in_mprj[123] , \la_data_in_mprj[122] , \la_data_in_mprj[121] , \la_data_in_mprj[120] , \la_data_in_mprj[119] , \la_data_in_mprj[118] , \la_data_in_mprj[117] , \la_data_in_mprj[116] , \la_data_in_mprj[115] , \la_data_in_mprj[114] , \la_data_in_mprj[113] , \la_data_in_mprj[112] , \la_data_in_mprj[111] , \la_data_in_mprj[110] , \la_data_in_mprj[109] , \la_data_in_mprj[108] , \la_data_in_mprj[107] , \la_data_in_mprj[106] , \la_data_in_mprj[105] , \la_data_in_mprj[104] , \la_data_in_mprj[103] , \la_data_in_mprj[102] , \la_data_in_mprj[101] , \la_data_in_mprj[100] , \la_data_in_mprj[99] , \la_data_in_mprj[98] , \la_data_in_mprj[97] , \la_data_in_mprj[96] , \la_data_in_mprj[95] , \la_data_in_mprj[94] , \la_data_in_mprj[93] , \la_data_in_mprj[92] , \la_data_in_mprj[91] , \la_data_in_mprj[90] , \la_data_in_mprj[89] , \la_data_in_mprj[88] , \la_data_in_mprj[87] , \la_data_in_mprj[86] , \la_data_in_mprj[85] , \la_data_in_mprj[84] , \la_data_in_mprj[83] , \la_data_in_mprj[82] , \la_data_in_mprj[81] , \la_data_in_mprj[80] , \la_data_in_mprj[79] , \la_data_in_mprj[78] , \la_data_in_mprj[77] , \la_data_in_mprj[76] , \la_data_in_mprj[75] , \la_data_in_mprj[74] , \la_data_in_mprj[73] , \la_data_in_mprj[72] , \la_data_in_mprj[71] , \la_data_in_mprj[70] , \la_data_in_mprj[69] , \la_data_in_mprj[68] , \la_data_in_mprj[67] , \la_data_in_mprj[66] , \la_data_in_mprj[65] , \la_data_in_mprj[64] , \la_data_in_mprj[63] , \la_data_in_mprj[62] , \la_data_in_mprj[61] , \la_data_in_mprj[60] , \la_data_in_mprj[59] , \la_data_in_mprj[58] , \la_data_in_mprj[57] , \la_data_in_mprj[56] , \la_data_in_mprj[55] , \la_data_in_mprj[54] , \la_data_in_mprj[53] , \la_data_in_mprj[52] , \la_data_in_mprj[51] , \la_data_in_mprj[50] , \la_data_in_mprj[49] , \la_data_in_mprj[48] , \la_data_in_mprj[47] , \la_data_in_mprj[46] , \la_data_in_mprj[45] , \la_data_in_mprj[44] , \la_data_in_mprj[43] , \la_data_in_mprj[42] , \la_data_in_mprj[41] , \la_data_in_mprj[40] , \la_data_in_mprj[39] , \la_data_in_mprj[38] , \la_data_in_mprj[37] , \la_data_in_mprj[36] , \la_data_in_mprj[35] , \la_data_in_mprj[34] , \la_data_in_mprj[33] , \la_data_in_mprj[32] , \la_data_in_mprj[31] , \la_data_in_mprj[30] , \la_data_in_mprj[29] , \la_data_in_mprj[28] , \la_data_in_mprj[27] , \la_data_in_mprj[26] , \la_data_in_mprj[25] , \la_data_in_mprj[24] , \la_data_in_mprj[23] , \la_data_in_mprj[22] , \la_data_in_mprj[21] , \la_data_in_mprj[20] , \la_data_in_mprj[19] , \la_data_in_mprj[18] , \la_data_in_mprj[17] , \la_data_in_mprj[16] , \la_data_in_mprj[15] , \la_data_in_mprj[14] , \la_data_in_mprj[13] , \la_data_in_mprj[12] , \la_data_in_mprj[11] , \la_data_in_mprj[10] , \la_data_in_mprj[9] , \la_data_in_mprj[8] , \la_data_in_mprj[7] , \la_data_in_mprj[6] , \la_data_in_mprj[5] , \la_data_in_mprj[4] , \la_data_in_mprj[3] , \la_data_in_mprj[2] , \la_data_in_mprj[1] , \la_data_in_mprj[0]  }),
+    .la_oenb({ \la_oenb_mprj[127] , \la_oenb_mprj[126] , \la_oenb_mprj[125] , \la_oenb_mprj[124] , \la_oenb_mprj[123] , \la_oenb_mprj[122] , \la_oenb_mprj[121] , \la_oenb_mprj[120] , \la_oenb_mprj[119] , \la_oenb_mprj[118] , \la_oenb_mprj[117] , \la_oenb_mprj[116] , \la_oenb_mprj[115] , \la_oenb_mprj[114] , \la_oenb_mprj[113] , \la_oenb_mprj[112] , \la_oenb_mprj[111] , \la_oenb_mprj[110] , \la_oenb_mprj[109] , \la_oenb_mprj[108] , \la_oenb_mprj[107] , \la_oenb_mprj[106] , \la_oenb_mprj[105] , \la_oenb_mprj[104] , \la_oenb_mprj[103] , \la_oenb_mprj[102] , \la_oenb_mprj[101] , \la_oenb_mprj[100] , \la_oenb_mprj[99] , \la_oenb_mprj[98] , \la_oenb_mprj[97] , \la_oenb_mprj[96] , \la_oenb_mprj[95] , \la_oenb_mprj[94] , \la_oenb_mprj[93] , \la_oenb_mprj[92] , \la_oenb_mprj[91] , \la_oenb_mprj[90] , \la_oenb_mprj[89] , \la_oenb_mprj[88] , \la_oenb_mprj[87] , \la_oenb_mprj[86] , \la_oenb_mprj[85] , \la_oenb_mprj[84] , \la_oenb_mprj[83] , \la_oenb_mprj[82] , \la_oenb_mprj[81] , \la_oenb_mprj[80] , \la_oenb_mprj[79] , \la_oenb_mprj[78] , \la_oenb_mprj[77] , \la_oenb_mprj[76] , \la_oenb_mprj[75] , \la_oenb_mprj[74] , \la_oenb_mprj[73] , \la_oenb_mprj[72] , \la_oenb_mprj[71] , \la_oenb_mprj[70] , \la_oenb_mprj[69] , \la_oenb_mprj[68] , \la_oenb_mprj[67] , \la_oenb_mprj[66] , \la_oenb_mprj[65] , \la_oenb_mprj[64] , \la_oenb_mprj[63] , \la_oenb_mprj[62] , \la_oenb_mprj[61] , \la_oenb_mprj[60] , \la_oenb_mprj[59] , \la_oenb_mprj[58] , \la_oenb_mprj[57] , \la_oenb_mprj[56] , \la_oenb_mprj[55] , \la_oenb_mprj[54] , \la_oenb_mprj[53] , \la_oenb_mprj[52] , \la_oenb_mprj[51] , \la_oenb_mprj[50] , \la_oenb_mprj[49] , \la_oenb_mprj[48] , \la_oenb_mprj[47] , \la_oenb_mprj[46] , \la_oenb_mprj[45] , \la_oenb_mprj[44] , \la_oenb_mprj[43] , \la_oenb_mprj[42] , \la_oenb_mprj[41] , \la_oenb_mprj[40] , \la_oenb_mprj[39] , \la_oenb_mprj[38] , \la_oenb_mprj[37] , \la_oenb_mprj[36] , \la_oenb_mprj[35] , \la_oenb_mprj[34] , \la_oenb_mprj[33] , \la_oenb_mprj[32] , \la_oenb_mprj[31] , \la_oenb_mprj[30] , \la_oenb_mprj[29] , \la_oenb_mprj[28] , \la_oenb_mprj[27] , \la_oenb_mprj[26] , \la_oenb_mprj[25] , \la_oenb_mprj[24] , \la_oenb_mprj[23] , \la_oenb_mprj[22] , \la_oenb_mprj[21] , \la_oenb_mprj[20] , \la_oenb_mprj[19] , \la_oenb_mprj[18] , \la_oenb_mprj[17] , \la_oenb_mprj[16] , \la_oenb_mprj[15] , \la_oenb_mprj[14] , \la_oenb_mprj[13] , \la_oenb_mprj[12] , \la_oenb_mprj[11] , \la_oenb_mprj[10] , \la_oenb_mprj[9] , \la_oenb_mprj[8] , \la_oenb_mprj[7] , \la_oenb_mprj[6] , \la_oenb_mprj[5] , \la_oenb_mprj[4] , \la_oenb_mprj[3] , \la_oenb_mprj[2] , \la_oenb_mprj[1] , \la_oenb_mprj[0]  }),
+    .la_output({ \la_data_out_mprj[127] , \la_data_out_mprj[126] , \la_data_out_mprj[125] , \la_data_out_mprj[124] , \la_data_out_mprj[123] , \la_data_out_mprj[122] , \la_data_out_mprj[121] , \la_data_out_mprj[120] , \la_data_out_mprj[119] , \la_data_out_mprj[118] , \la_data_out_mprj[117] , \la_data_out_mprj[116] , \la_data_out_mprj[115] , \la_data_out_mprj[114] , \la_data_out_mprj[113] , \la_data_out_mprj[112] , \la_data_out_mprj[111] , \la_data_out_mprj[110] , \la_data_out_mprj[109] , \la_data_out_mprj[108] , \la_data_out_mprj[107] , \la_data_out_mprj[106] , \la_data_out_mprj[105] , \la_data_out_mprj[104] , \la_data_out_mprj[103] , \la_data_out_mprj[102] , \la_data_out_mprj[101] , \la_data_out_mprj[100] , \la_data_out_mprj[99] , \la_data_out_mprj[98] , \la_data_out_mprj[97] , \la_data_out_mprj[96] , \la_data_out_mprj[95] , \la_data_out_mprj[94] , \la_data_out_mprj[93] , \la_data_out_mprj[92] , \la_data_out_mprj[91] , \la_data_out_mprj[90] , \la_data_out_mprj[89] , \la_data_out_mprj[88] , \la_data_out_mprj[87] , \la_data_out_mprj[86] , \la_data_out_mprj[85] , \la_data_out_mprj[84] , \la_data_out_mprj[83] , \la_data_out_mprj[82] , \la_data_out_mprj[81] , \la_data_out_mprj[80] , \la_data_out_mprj[79] , \la_data_out_mprj[78] , \la_data_out_mprj[77] , \la_data_out_mprj[76] , \la_data_out_mprj[75] , \la_data_out_mprj[74] , \la_data_out_mprj[73] , \la_data_out_mprj[72] , \la_data_out_mprj[71] , \la_data_out_mprj[70] , \la_data_out_mprj[69] , \la_data_out_mprj[68] , \la_data_out_mprj[67] , \la_data_out_mprj[66] , \la_data_out_mprj[65] , \la_data_out_mprj[64] , \la_data_out_mprj[63] , \la_data_out_mprj[62] , \la_data_out_mprj[61] , \la_data_out_mprj[60] , \la_data_out_mprj[59] , \la_data_out_mprj[58] , \la_data_out_mprj[57] , \la_data_out_mprj[56] , \la_data_out_mprj[55] , \la_data_out_mprj[54] , \la_data_out_mprj[53] , \la_data_out_mprj[52] , \la_data_out_mprj[51] , \la_data_out_mprj[50] , \la_data_out_mprj[49] , \la_data_out_mprj[48] , \la_data_out_mprj[47] , \la_data_out_mprj[46] , \la_data_out_mprj[45] , \la_data_out_mprj[44] , \la_data_out_mprj[43] , \la_data_out_mprj[42] , \la_data_out_mprj[41] , \la_data_out_mprj[40] , \la_data_out_mprj[39] , \la_data_out_mprj[38] , \la_data_out_mprj[37] , \la_data_out_mprj[36] , \la_data_out_mprj[35] , \la_data_out_mprj[34] , \la_data_out_mprj[33] , \la_data_out_mprj[32] , \la_data_out_mprj[31] , \la_data_out_mprj[30] , \la_data_out_mprj[29] , \la_data_out_mprj[28] , \la_data_out_mprj[27] , \la_data_out_mprj[26] , \la_data_out_mprj[25] , \la_data_out_mprj[24] , \la_data_out_mprj[23] , \la_data_out_mprj[22] , \la_data_out_mprj[21] , \la_data_out_mprj[20] , \la_data_out_mprj[19] , \la_data_out_mprj[18] , \la_data_out_mprj[17] , \la_data_out_mprj[16] , \la_data_out_mprj[15] , \la_data_out_mprj[14] , \la_data_out_mprj[13] , \la_data_out_mprj[12] , \la_data_out_mprj[11] , \la_data_out_mprj[10] , \la_data_out_mprj[9] , \la_data_out_mprj[8] , \la_data_out_mprj[7] , \la_data_out_mprj[6] , \la_data_out_mprj[5] , \la_data_out_mprj[4] , \la_data_out_mprj[3] , \la_data_out_mprj[2] , \la_data_out_mprj[1] , \la_data_out_mprj[0]  }),
+    .mprj_ack_i(mprj_ack_i_core),
+    .mprj_adr_o({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0]  }),
+    .mprj_cyc_o(mprj_cyc_o_core),
+    .mprj_dat_i({ \mprj_dat_i_core[31] , \mprj_dat_i_core[30] , \mprj_dat_i_core[29] , \mprj_dat_i_core[28] , \mprj_dat_i_core[27] , \mprj_dat_i_core[26] , \mprj_dat_i_core[25] , \mprj_dat_i_core[24] , \mprj_dat_i_core[23] , \mprj_dat_i_core[22] , \mprj_dat_i_core[21] , \mprj_dat_i_core[20] , \mprj_dat_i_core[19] , \mprj_dat_i_core[18] , \mprj_dat_i_core[17] , \mprj_dat_i_core[16] , \mprj_dat_i_core[15] , \mprj_dat_i_core[14] , \mprj_dat_i_core[13] , \mprj_dat_i_core[12] , \mprj_dat_i_core[11] , \mprj_dat_i_core[10] , \mprj_dat_i_core[9] , \mprj_dat_i_core[8] , \mprj_dat_i_core[7] , \mprj_dat_i_core[6] , \mprj_dat_i_core[5] , \mprj_dat_i_core[4] , \mprj_dat_i_core[3] , \mprj_dat_i_core[2] , \mprj_dat_i_core[1] , \mprj_dat_i_core[0]  }),
+    .mprj_dat_o({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0]  }),
+    .mprj_sel_o({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0]  }),
+    .mprj_stb_o(mprj_stb_o_core),
+    .mprj_we_o(mprj_we_o_core),
+    .qspi_enabled(qspi_enabled),
+    .ser_rx(ser_rx),
+    .ser_tx(ser_tx),
+    .spi_csb(spi_csb),
+    .spi_enabled(spi_enabled),
+    .spi_sck(spi_sck),
+    .spi_sdi(spi_sdi),
+    .spi_sdo(spi_sdo),
+    .spi_sdoenb(spi_sdoenb),
+    .sram_ro_addr({ \hkspi_sram_addr[7] , \hkspi_sram_addr[6] , \hkspi_sram_addr[5] , \hkspi_sram_addr[4] , \hkspi_sram_addr[3] , \hkspi_sram_addr[2] , \hkspi_sram_addr[1] , \hkspi_sram_addr[0]  }),
+    .sram_ro_clk(hkspi_sram_clk),
+    .sram_ro_csb(hkspi_sram_csb),
+    .sram_ro_data({ \hkspi_sram_data[31] , \hkspi_sram_data[30] , \hkspi_sram_data[29] , \hkspi_sram_data[28] , \hkspi_sram_data[27] , \hkspi_sram_data[26] , \hkspi_sram_data[25] , \hkspi_sram_data[24] , \hkspi_sram_data[23] , \hkspi_sram_data[22] , \hkspi_sram_data[21] , \hkspi_sram_data[20] , \hkspi_sram_data[19] , \hkspi_sram_data[18] , \hkspi_sram_data[17] , \hkspi_sram_data[16] , \hkspi_sram_data[15] , \hkspi_sram_data[14] , \hkspi_sram_data[13] , \hkspi_sram_data[12] , \hkspi_sram_data[11] , \hkspi_sram_data[10] , \hkspi_sram_data[9] , \hkspi_sram_data[8] , \hkspi_sram_data[7] , \hkspi_sram_data[6] , \hkspi_sram_data[5] , \hkspi_sram_data[4] , \hkspi_sram_data[3] , \hkspi_sram_data[2] , \hkspi_sram_data[1] , \hkspi_sram_data[0]  }),
+    .trap(trap),
+    .uart_enabled(uart_enabled)
+  );
+  user_id_programming user_id_value (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .mask_rev({ \mask_rev[31] , \mask_rev[30] , \mask_rev[29] , \mask_rev[28] , \mask_rev[27] , \mask_rev[26] , \mask_rev[25] , \mask_rev[24] , \mask_rev[23] , \mask_rev[22] , \mask_rev[21] , \mask_rev[20] , \mask_rev[19] , \mask_rev[18] , \mask_rev[17] , \mask_rev[16] , \mask_rev[15] , \mask_rev[14] , \mask_rev[13] , \mask_rev[12] , \mask_rev[11] , \mask_rev[10] , \mask_rev[9] , \mask_rev[8] , \mask_rev[7] , \mask_rev[6] , \mask_rev[5] , \mask_rev[4] , \mask_rev[3] , \mask_rev[2] , \mask_rev[1] , \mask_rev[0]  })
+  );
+  spare_logic_block \spare_logic[0]  (
+    .vssd(vssd_core),
+    .vccd(vccd_core),
+    .spare_xz(),
+    .spare_xi(),
+    .spare_xib(),
+    .spare_xna(),
+    .spare_xno(),
+    .spare_xmx(),
+    .spare_xfq(),
+    .spare_xfqn()
+  );
+  spare_logic_block \spare_logic[1]  (
+    .vssd(vssd_core),
+    .vccd(vccd_core),
+    .spare_xz(),
+    .spare_xi(),
+    .spare_xib(),
+    .spare_xna(),
+    .spare_xno(),
+    .spare_xmx(),
+    .spare_xfq(),
+    .spare_xfqn()
+  );
+  spare_logic_block \spare_logic[2]  (
+    .vssd(vssd_core),
+    .vccd(vccd_core),
+    .spare_xz(),
+    .spare_xi(),
+    .spare_xib(),
+    .spare_xna(),
+    .spare_xno(),
+    .spare_xmx(),
+    .spare_xfq(),
+    .spare_xfqn()
+  );
+  spare_logic_block \spare_logic[3]  (
+    .vssd(vssd_core),
+    .vccd(vccd_core),
+    .spare_xz(),
+    .spare_xi(),
+    .spare_xib(),
+    .spare_xna(),
+    .spare_xno(),
+    .spare_xmx(),
+    .spare_xfq(),
+    .spare_xfqn()
+  );
+
+  assign \gpio_resetn_1_shifted[13]  = \gpio_resetn_1[12] ;
+  assign \gpio_resetn_1_shifted[12]  = \gpio_resetn_1[11] ;
+  assign \gpio_resetn_1_shifted[11]  = \gpio_resetn_1[10] ;
+  assign \gpio_resetn_1_shifted[10]  = \gpio_resetn_1[9] ;
+  assign \gpio_resetn_1_shifted[9]  = \gpio_resetn_1[8] ;
+  assign \gpio_resetn_1_shifted[8]  = \gpio_resetn_1[7] ;
+  assign \gpio_resetn_1_shifted[7]  = \gpio_resetn_1[6] ;
+  assign \gpio_resetn_1_shifted[6]  = \gpio_resetn_1[5] ;
+  assign \gpio_resetn_1_shifted[5]  = \gpio_resetn_1[4] ;
+  assign \gpio_resetn_1_shifted[4]  = \gpio_resetn_1[3] ;
+  assign \gpio_resetn_1_shifted[3]  = \gpio_resetn_1[2] ;
+  assign \gpio_resetn_1_shifted[2]  = \gpio_resetn_1[1] ;
+  assign \gpio_resetn_1_shifted[1]  = \gpio_resetn_1[0] ;
+  assign \gpio_clock_2_shifted[12]  = \gpio_clock_1_shifted[0] ;
+  assign \gpio_clock_2_shifted[11]  = \gpio_clock_2[12] ;
+  assign \gpio_clock_2_shifted[10]  = \gpio_clock_2[11] ;
+  assign \gpio_clock_2_shifted[9]  = \gpio_clock_2[10] ;
+  assign \gpio_clock_2_shifted[8]  = \gpio_clock_2[9] ;
+  assign \gpio_clock_2_shifted[7]  = \gpio_clock_2[8] ;
+  assign \gpio_clock_2_shifted[6]  = \gpio_clock_2[7] ;
+  assign \gpio_clock_2_shifted[5]  = \gpio_clock_2[6] ;
+  assign \gpio_clock_2_shifted[4]  = \gpio_clock_2[5] ;
+  assign \gpio_clock_2_shifted[3]  = \gpio_clock_2[4] ;
+  assign \gpio_clock_2_shifted[2]  = \gpio_clock_2[3] ;
+  assign \gpio_clock_2_shifted[1]  = \gpio_clock_2[2] ;
+  assign \gpio_clock_2_shifted[0]  = \gpio_clock_2[1] ;
+  assign \gpio_serial_link_2_shifted[11]  = \gpio_serial_link_2[12] ;
+  assign \gpio_serial_link_2_shifted[10]  = \gpio_serial_link_2[11] ;
+  assign \gpio_serial_link_2_shifted[9]  = \gpio_serial_link_2[10] ;
+  assign \gpio_serial_link_2_shifted[8]  = \gpio_serial_link_2[9] ;
+  assign \gpio_serial_link_2_shifted[7]  = \gpio_serial_link_2[8] ;
+  assign \gpio_serial_link_2_shifted[6]  = \gpio_serial_link_2[7] ;
+  assign \gpio_serial_link_2_shifted[5]  = \gpio_serial_link_2[6] ;
+  assign \gpio_serial_link_2_shifted[4]  = \gpio_serial_link_2[5] ;
+  assign \gpio_serial_link_2_shifted[3]  = \gpio_serial_link_2[4] ;
+  assign \gpio_serial_link_2_shifted[2]  = \gpio_serial_link_2[3] ;
+  assign \gpio_serial_link_2_shifted[1]  = \gpio_serial_link_2[2] ;
+  assign \gpio_serial_link_2_shifted[0]  = \gpio_serial_link_2[1] ;
+  assign \gpio_serial_link_1_shifted[13]  = \gpio_serial_link_1[12] ;
+  assign \gpio_serial_link_1_shifted[12]  = \gpio_serial_link_1[11] ;
+  assign \gpio_serial_link_1_shifted[11]  = \gpio_serial_link_1[10] ;
+  assign \gpio_serial_link_1_shifted[10]  = \gpio_serial_link_1[9] ;
+  assign \gpio_serial_link_1_shifted[9]  = \gpio_serial_link_1[8] ;
+  assign \gpio_serial_link_1_shifted[8]  = \gpio_serial_link_1[7] ;
+  assign \gpio_serial_link_1_shifted[7]  = \gpio_serial_link_1[6] ;
+  assign \gpio_serial_link_1_shifted[6]  = \gpio_serial_link_1[5] ;
+  assign \gpio_serial_link_1_shifted[5]  = \gpio_serial_link_1[4] ;
+  assign \gpio_serial_link_1_shifted[4]  = \gpio_serial_link_1[3] ;
+  assign \gpio_serial_link_1_shifted[3]  = \gpio_serial_link_1[2] ;
+  assign \gpio_serial_link_1_shifted[2]  = \gpio_serial_link_1[1] ;
+  assign \gpio_serial_link_1_shifted[1]  = \gpio_serial_link_1[0] ;
+  assign \user_io_in_3v3[26]  = \mprj_io_in_3v3[26] ;
+  assign \user_io_in_3v3[25]  = \mprj_io_in_3v3[25] ;
+  assign \user_io_in_3v3[24]  = \mprj_io_in_3v3[24] ;
+  assign \user_io_in_3v3[23]  = \mprj_io_in_3v3[23] ;
+  assign \user_io_in_3v3[22]  = \mprj_io_in_3v3[22] ;
+  assign \user_io_in_3v3[21]  = \mprj_io_in_3v3[21] ;
+  assign \user_io_in_3v3[20]  = \mprj_io_in_3v3[20] ;
+  assign \user_io_in_3v3[19]  = \mprj_io_in_3v3[19] ;
+  assign \user_io_in_3v3[18]  = \mprj_io_in_3v3[18] ;
+  assign \user_io_in_3v3[17]  = \mprj_io_in_3v3[17] ;
+  assign \user_io_in_3v3[16]  = \mprj_io_in_3v3[16] ;
+  assign \user_io_in_3v3[15]  = \mprj_io_in_3v3[15] ;
+  assign \user_io_in_3v3[14]  = \mprj_io_in_3v3[14] ;
+  assign \user_io_in_3v3[13]  = \mprj_io_in_3v3[13] ;
+  assign \user_io_in_3v3[12]  = \mprj_io_in_3v3[12] ;
+  assign \user_io_in_3v3[11]  = \mprj_io_in_3v3[11] ;
+  assign \user_io_in_3v3[10]  = \mprj_io_in_3v3[10] ;
+  assign \user_io_in_3v3[9]  = \mprj_io_in_3v3[9] ;
+  assign \user_io_in_3v3[8]  = \mprj_io_in_3v3[8] ;
+  assign \user_io_in_3v3[7]  = \mprj_io_in_3v3[7] ;
+  assign \user_io_in_3v3[6]  = \mprj_io_in_3v3[6] ;
+  assign \user_io_in_3v3[5]  = \mprj_io_in_3v3[5] ;
+  assign \user_io_in_3v3[4]  = \mprj_io_in_3v3[4] ;
+  assign \user_io_in_3v3[3]  = \mprj_io_in_3v3[3] ;
+  assign \user_io_in_3v3[2]  = \mprj_io_in_3v3[2] ;
+  assign \user_io_in_3v3[1]  = \mprj_io_in_3v3[1] ;
+  assign \user_io_in_3v3[0]  = \mprj_io_in_3v3[0] ;
+  assign \gpio_load_2_shifted[12]  = \gpio_load_1_shifted[0] ;
+  assign \gpio_load_2_shifted[11]  = \gpio_load_2[12] ;
+  assign \gpio_load_2_shifted[10]  = \gpio_load_2[11] ;
+  assign \gpio_load_2_shifted[9]  = \gpio_load_2[10] ;
+  assign \gpio_load_2_shifted[8]  = \gpio_load_2[9] ;
+  assign \gpio_load_2_shifted[7]  = \gpio_load_2[8] ;
+  assign \gpio_load_2_shifted[6]  = \gpio_load_2[7] ;
+  assign \gpio_load_2_shifted[5]  = \gpio_load_2[6] ;
+  assign \gpio_load_2_shifted[4]  = \gpio_load_2[5] ;
+  assign \gpio_load_2_shifted[3]  = \gpio_load_2[4] ;
+  assign \gpio_load_2_shifted[2]  = \gpio_load_2[3] ;
+  assign \gpio_load_2_shifted[1]  = \gpio_load_2[2] ;
+  assign \gpio_load_2_shifted[0]  = \gpio_load_2[1] ;
+  assign \gpio_resetn_2_shifted[12]  = \gpio_resetn_1_shifted[0] ;
+  assign \gpio_resetn_2_shifted[11]  = \gpio_resetn_2[12] ;
+  assign \gpio_resetn_2_shifted[10]  = \gpio_resetn_2[11] ;
+  assign \gpio_resetn_2_shifted[9]  = \gpio_resetn_2[10] ;
+  assign \gpio_resetn_2_shifted[8]  = \gpio_resetn_2[9] ;
+  assign \gpio_resetn_2_shifted[7]  = \gpio_resetn_2[8] ;
+  assign \gpio_resetn_2_shifted[6]  = \gpio_resetn_2[7] ;
+  assign \gpio_resetn_2_shifted[5]  = \gpio_resetn_2[6] ;
+  assign \gpio_resetn_2_shifted[4]  = \gpio_resetn_2[5] ;
+  assign \gpio_resetn_2_shifted[3]  = \gpio_resetn_2[4] ;
+  assign \gpio_resetn_2_shifted[2]  = \gpio_resetn_2[3] ;
+  assign \gpio_resetn_2_shifted[1]  = \gpio_resetn_2[2] ;
+  assign \gpio_resetn_2_shifted[0]  = \gpio_resetn_2[1] ;
+  assign \gpio_load_1_shifted[13]  = \gpio_load_1[12] ;
+  assign \gpio_load_1_shifted[12]  = \gpio_load_1[11] ;
+  assign \gpio_load_1_shifted[11]  = \gpio_load_1[10] ;
+  assign \gpio_load_1_shifted[10]  = \gpio_load_1[9] ;
+  assign \gpio_load_1_shifted[9]  = \gpio_load_1[8] ;
+  assign \gpio_load_1_shifted[8]  = \gpio_load_1[7] ;
+  assign \gpio_load_1_shifted[7]  = \gpio_load_1[6] ;
+  assign \gpio_load_1_shifted[6]  = \gpio_load_1[5] ;
+  assign \gpio_load_1_shifted[5]  = \gpio_load_1[4] ;
+  assign \gpio_load_1_shifted[4]  = \gpio_load_1[3] ;
+  assign \gpio_load_1_shifted[3]  = \gpio_load_1[2] ;
+  assign \gpio_load_1_shifted[2]  = \gpio_load_1[1] ;
+  assign \gpio_load_1_shifted[1]  = \gpio_load_1[0] ;
+  assign \gpio_clock_1_shifted[13]  = \gpio_clock_1[12] ;
+  assign \gpio_clock_1_shifted[12]  = \gpio_clock_1[11] ;
+  assign \gpio_clock_1_shifted[11]  = \gpio_clock_1[10] ;
+  assign \gpio_clock_1_shifted[10]  = \gpio_clock_1[9] ;
+  assign \gpio_clock_1_shifted[9]  = \gpio_clock_1[8] ;
+  assign \gpio_clock_1_shifted[8]  = \gpio_clock_1[7] ;
+  assign \gpio_clock_1_shifted[7]  = \gpio_clock_1[6] ;
+  assign \gpio_clock_1_shifted[6]  = \gpio_clock_1[5] ;
+  assign \gpio_clock_1_shifted[5]  = \gpio_clock_1[4] ;
+  assign \gpio_clock_1_shifted[4]  = \gpio_clock_1[3] ;
+  assign \gpio_clock_1_shifted[3]  = \gpio_clock_1[2] ;
+  assign \gpio_clock_1_shifted[2]  = \gpio_clock_1[1] ;
+  assign \gpio_clock_1_shifted[1]  = \gpio_clock_1[0] ;
+  assign mprj_io_loader_data_2 = \gpio_serial_link_2_shifted[12] ;
+  assign mprj_io_loader_data_1 = \gpio_serial_link_1_shifted[0] ;
+  assign mprj_io_loader_strobe = \gpio_load_1_shifted[0] ;
+  assign mprj_io_loader_clock = \gpio_clock_1_shifted[0] ;
+  assign mprj_io_loader_resetn = \gpio_resetn_1_shifted[0] ;
+endmodule
diff --git a/verilog/gl/caravel.v b/verilog/gl/caravel.v
new file mode 100644
index 0000000..91ae7a2
--- /dev/null
+++ b/verilog/gl/caravel.v
@@ -0,0 +1,5053 @@
+/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
+
+module caravel(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vdda1_2, vdda2, vssa1, vssa1_2, vssa2, vccd1, vccd2, vssd1, vssd2, gpio, mprj_io, clock, resetb, flash_csb, flash_clk, flash_io0, flash_io1);
+  wire caravel_clk;
+  wire caravel_clk2;
+  wire caravel_rstn;
+  input clock;
+  wire clock_core;
+  wire debug_in;
+  wire debug_mode;
+  wire debug_oeb;
+  wire debug_out;
+  wire ext_clk_sel;
+  wire ext_reset;
+  output flash_clk;
+  wire flash_clk_core;
+  wire flash_clk_frame;
+  wire flash_clk_ieb;
+  wire flash_clk_ieb_core;
+  wire flash_clk_oeb;
+  wire flash_clk_oeb_core;
+  output flash_csb;
+  wire flash_csb_core;
+  wire flash_csb_frame;
+  wire flash_csb_ieb;
+  wire flash_csb_ieb_core;
+  wire flash_csb_oeb;
+  wire flash_csb_oeb_core;
+  output flash_io0;
+  wire flash_io0_di;
+  wire flash_io0_di_core;
+  wire flash_io0_do;
+  wire flash_io0_do_core;
+  wire flash_io0_ieb;
+  wire flash_io0_ieb_core;
+  wire flash_io0_oeb;
+  wire flash_io0_oeb_core;
+  output flash_io1;
+  wire flash_io1_di;
+  wire flash_io1_di_core;
+  wire flash_io1_do;
+  wire flash_io1_do_core;
+  wire flash_io1_ieb;
+  wire flash_io1_ieb_core;
+  wire flash_io1_oeb;
+  wire flash_io1_oeb_core;
+  wire flash_io2_di_core;
+  wire flash_io2_do_core;
+  wire flash_io2_ieb_core;
+  wire flash_io2_oeb_core;
+  wire flash_io3_di_core;
+  wire flash_io3_do_core;
+  wire flash_io3_ieb_core;
+  wire flash_io3_oeb_core;
+  inout gpio;
+  wire \gpio_clock_1[0] ;
+  wire \gpio_clock_1[10] ;
+  wire \gpio_clock_1[11] ;
+  wire \gpio_clock_1[12] ;
+  wire \gpio_clock_1[13] ;
+  wire \gpio_clock_1[14] ;
+  wire \gpio_clock_1[15] ;
+  wire \gpio_clock_1[16] ;
+  wire \gpio_clock_1[17] ;
+  wire \gpio_clock_1[18] ;
+  wire \gpio_clock_1[1] ;
+  wire \gpio_clock_1[2] ;
+  wire \gpio_clock_1[3] ;
+  wire \gpio_clock_1[4] ;
+  wire \gpio_clock_1[5] ;
+  wire \gpio_clock_1[6] ;
+  wire \gpio_clock_1[7] ;
+  wire \gpio_clock_1[8] ;
+  wire \gpio_clock_1[9] ;
+  wire \gpio_clock_1_shifted[0] ;
+  wire \gpio_clock_1_shifted[10] ;
+  wire \gpio_clock_1_shifted[11] ;
+  wire \gpio_clock_1_shifted[12] ;
+  wire \gpio_clock_1_shifted[13] ;
+  wire \gpio_clock_1_shifted[14] ;
+  wire \gpio_clock_1_shifted[15] ;
+  wire \gpio_clock_1_shifted[16] ;
+  wire \gpio_clock_1_shifted[17] ;
+  wire \gpio_clock_1_shifted[18] ;
+  wire \gpio_clock_1_shifted[1] ;
+  wire \gpio_clock_1_shifted[2] ;
+  wire \gpio_clock_1_shifted[3] ;
+  wire \gpio_clock_1_shifted[4] ;
+  wire \gpio_clock_1_shifted[5] ;
+  wire \gpio_clock_1_shifted[6] ;
+  wire \gpio_clock_1_shifted[7] ;
+  wire \gpio_clock_1_shifted[8] ;
+  wire \gpio_clock_1_shifted[9] ;
+  wire \gpio_clock_2[0] ;
+  wire \gpio_clock_2[10] ;
+  wire \gpio_clock_2[11] ;
+  wire \gpio_clock_2[12] ;
+  wire \gpio_clock_2[13] ;
+  wire \gpio_clock_2[14] ;
+  wire \gpio_clock_2[15] ;
+  wire \gpio_clock_2[16] ;
+  wire \gpio_clock_2[17] ;
+  wire \gpio_clock_2[18] ;
+  wire \gpio_clock_2[1] ;
+  wire \gpio_clock_2[2] ;
+  wire \gpio_clock_2[3] ;
+  wire \gpio_clock_2[4] ;
+  wire \gpio_clock_2[5] ;
+  wire \gpio_clock_2[6] ;
+  wire \gpio_clock_2[7] ;
+  wire \gpio_clock_2[8] ;
+  wire \gpio_clock_2[9] ;
+  wire \gpio_clock_2_shifted[0] ;
+  wire \gpio_clock_2_shifted[10] ;
+  wire \gpio_clock_2_shifted[11] ;
+  wire \gpio_clock_2_shifted[12] ;
+  wire \gpio_clock_2_shifted[13] ;
+  wire \gpio_clock_2_shifted[14] ;
+  wire \gpio_clock_2_shifted[15] ;
+  wire \gpio_clock_2_shifted[16] ;
+  wire \gpio_clock_2_shifted[17] ;
+  wire \gpio_clock_2_shifted[18] ;
+  wire \gpio_clock_2_shifted[1] ;
+  wire \gpio_clock_2_shifted[2] ;
+  wire \gpio_clock_2_shifted[3] ;
+  wire \gpio_clock_2_shifted[4] ;
+  wire \gpio_clock_2_shifted[5] ;
+  wire \gpio_clock_2_shifted[6] ;
+  wire \gpio_clock_2_shifted[7] ;
+  wire \gpio_clock_2_shifted[8] ;
+  wire \gpio_clock_2_shifted[9] ;
+  wire \gpio_defaults[0] ;
+  wire \gpio_defaults[100] ;
+  wire \gpio_defaults[101] ;
+  wire \gpio_defaults[102] ;
+  wire \gpio_defaults[103] ;
+  wire \gpio_defaults[104] ;
+  wire \gpio_defaults[105] ;
+  wire \gpio_defaults[106] ;
+  wire \gpio_defaults[107] ;
+  wire \gpio_defaults[108] ;
+  wire \gpio_defaults[109] ;
+  wire \gpio_defaults[10] ;
+  wire \gpio_defaults[110] ;
+  wire \gpio_defaults[111] ;
+  wire \gpio_defaults[112] ;
+  wire \gpio_defaults[113] ;
+  wire \gpio_defaults[114] ;
+  wire \gpio_defaults[115] ;
+  wire \gpio_defaults[116] ;
+  wire \gpio_defaults[117] ;
+  wire \gpio_defaults[118] ;
+  wire \gpio_defaults[119] ;
+  wire \gpio_defaults[11] ;
+  wire \gpio_defaults[120] ;
+  wire \gpio_defaults[121] ;
+  wire \gpio_defaults[122] ;
+  wire \gpio_defaults[123] ;
+  wire \gpio_defaults[124] ;
+  wire \gpio_defaults[125] ;
+  wire \gpio_defaults[126] ;
+  wire \gpio_defaults[127] ;
+  wire \gpio_defaults[128] ;
+  wire \gpio_defaults[129] ;
+  wire \gpio_defaults[12] ;
+  wire \gpio_defaults[130] ;
+  wire \gpio_defaults[131] ;
+  wire \gpio_defaults[132] ;
+  wire \gpio_defaults[133] ;
+  wire \gpio_defaults[134] ;
+  wire \gpio_defaults[135] ;
+  wire \gpio_defaults[136] ;
+  wire \gpio_defaults[137] ;
+  wire \gpio_defaults[138] ;
+  wire \gpio_defaults[139] ;
+  wire \gpio_defaults[13] ;
+  wire \gpio_defaults[140] ;
+  wire \gpio_defaults[141] ;
+  wire \gpio_defaults[142] ;
+  wire \gpio_defaults[143] ;
+  wire \gpio_defaults[144] ;
+  wire \gpio_defaults[145] ;
+  wire \gpio_defaults[146] ;
+  wire \gpio_defaults[147] ;
+  wire \gpio_defaults[148] ;
+  wire \gpio_defaults[149] ;
+  wire \gpio_defaults[14] ;
+  wire \gpio_defaults[150] ;
+  wire \gpio_defaults[151] ;
+  wire \gpio_defaults[152] ;
+  wire \gpio_defaults[153] ;
+  wire \gpio_defaults[154] ;
+  wire \gpio_defaults[155] ;
+  wire \gpio_defaults[156] ;
+  wire \gpio_defaults[157] ;
+  wire \gpio_defaults[158] ;
+  wire \gpio_defaults[159] ;
+  wire \gpio_defaults[15] ;
+  wire \gpio_defaults[160] ;
+  wire \gpio_defaults[161] ;
+  wire \gpio_defaults[162] ;
+  wire \gpio_defaults[163] ;
+  wire \gpio_defaults[164] ;
+  wire \gpio_defaults[165] ;
+  wire \gpio_defaults[166] ;
+  wire \gpio_defaults[167] ;
+  wire \gpio_defaults[168] ;
+  wire \gpio_defaults[169] ;
+  wire \gpio_defaults[16] ;
+  wire \gpio_defaults[170] ;
+  wire \gpio_defaults[171] ;
+  wire \gpio_defaults[172] ;
+  wire \gpio_defaults[173] ;
+  wire \gpio_defaults[174] ;
+  wire \gpio_defaults[175] ;
+  wire \gpio_defaults[176] ;
+  wire \gpio_defaults[177] ;
+  wire \gpio_defaults[178] ;
+  wire \gpio_defaults[179] ;
+  wire \gpio_defaults[17] ;
+  wire \gpio_defaults[180] ;
+  wire \gpio_defaults[181] ;
+  wire \gpio_defaults[182] ;
+  wire \gpio_defaults[183] ;
+  wire \gpio_defaults[184] ;
+  wire \gpio_defaults[185] ;
+  wire \gpio_defaults[186] ;
+  wire \gpio_defaults[187] ;
+  wire \gpio_defaults[188] ;
+  wire \gpio_defaults[189] ;
+  wire \gpio_defaults[18] ;
+  wire \gpio_defaults[190] ;
+  wire \gpio_defaults[191] ;
+  wire \gpio_defaults[192] ;
+  wire \gpio_defaults[193] ;
+  wire \gpio_defaults[194] ;
+  wire \gpio_defaults[195] ;
+  wire \gpio_defaults[196] ;
+  wire \gpio_defaults[197] ;
+  wire \gpio_defaults[198] ;
+  wire \gpio_defaults[199] ;
+  wire \gpio_defaults[19] ;
+  wire \gpio_defaults[1] ;
+  wire \gpio_defaults[200] ;
+  wire \gpio_defaults[201] ;
+  wire \gpio_defaults[202] ;
+  wire \gpio_defaults[203] ;
+  wire \gpio_defaults[204] ;
+  wire \gpio_defaults[205] ;
+  wire \gpio_defaults[206] ;
+  wire \gpio_defaults[207] ;
+  wire \gpio_defaults[208] ;
+  wire \gpio_defaults[209] ;
+  wire \gpio_defaults[20] ;
+  wire \gpio_defaults[210] ;
+  wire \gpio_defaults[211] ;
+  wire \gpio_defaults[212] ;
+  wire \gpio_defaults[213] ;
+  wire \gpio_defaults[214] ;
+  wire \gpio_defaults[215] ;
+  wire \gpio_defaults[216] ;
+  wire \gpio_defaults[217] ;
+  wire \gpio_defaults[218] ;
+  wire \gpio_defaults[219] ;
+  wire \gpio_defaults[21] ;
+  wire \gpio_defaults[220] ;
+  wire \gpio_defaults[221] ;
+  wire \gpio_defaults[222] ;
+  wire \gpio_defaults[223] ;
+  wire \gpio_defaults[224] ;
+  wire \gpio_defaults[225] ;
+  wire \gpio_defaults[226] ;
+  wire \gpio_defaults[227] ;
+  wire \gpio_defaults[228] ;
+  wire \gpio_defaults[229] ;
+  wire \gpio_defaults[22] ;
+  wire \gpio_defaults[230] ;
+  wire \gpio_defaults[231] ;
+  wire \gpio_defaults[232] ;
+  wire \gpio_defaults[233] ;
+  wire \gpio_defaults[234] ;
+  wire \gpio_defaults[235] ;
+  wire \gpio_defaults[236] ;
+  wire \gpio_defaults[237] ;
+  wire \gpio_defaults[238] ;
+  wire \gpio_defaults[239] ;
+  wire \gpio_defaults[23] ;
+  wire \gpio_defaults[240] ;
+  wire \gpio_defaults[241] ;
+  wire \gpio_defaults[242] ;
+  wire \gpio_defaults[243] ;
+  wire \gpio_defaults[244] ;
+  wire \gpio_defaults[245] ;
+  wire \gpio_defaults[246] ;
+  wire \gpio_defaults[247] ;
+  wire \gpio_defaults[248] ;
+  wire \gpio_defaults[249] ;
+  wire \gpio_defaults[24] ;
+  wire \gpio_defaults[250] ;
+  wire \gpio_defaults[251] ;
+  wire \gpio_defaults[252] ;
+  wire \gpio_defaults[253] ;
+  wire \gpio_defaults[254] ;
+  wire \gpio_defaults[255] ;
+  wire \gpio_defaults[256] ;
+  wire \gpio_defaults[257] ;
+  wire \gpio_defaults[258] ;
+  wire \gpio_defaults[259] ;
+  wire \gpio_defaults[25] ;
+  wire \gpio_defaults[260] ;
+  wire \gpio_defaults[261] ;
+  wire \gpio_defaults[262] ;
+  wire \gpio_defaults[263] ;
+  wire \gpio_defaults[264] ;
+  wire \gpio_defaults[265] ;
+  wire \gpio_defaults[266] ;
+  wire \gpio_defaults[267] ;
+  wire \gpio_defaults[268] ;
+  wire \gpio_defaults[269] ;
+  wire \gpio_defaults[26] ;
+  wire \gpio_defaults[270] ;
+  wire \gpio_defaults[271] ;
+  wire \gpio_defaults[272] ;
+  wire \gpio_defaults[273] ;
+  wire \gpio_defaults[274] ;
+  wire \gpio_defaults[275] ;
+  wire \gpio_defaults[276] ;
+  wire \gpio_defaults[277] ;
+  wire \gpio_defaults[278] ;
+  wire \gpio_defaults[279] ;
+  wire \gpio_defaults[27] ;
+  wire \gpio_defaults[280] ;
+  wire \gpio_defaults[281] ;
+  wire \gpio_defaults[282] ;
+  wire \gpio_defaults[283] ;
+  wire \gpio_defaults[284] ;
+  wire \gpio_defaults[285] ;
+  wire \gpio_defaults[286] ;
+  wire \gpio_defaults[287] ;
+  wire \gpio_defaults[288] ;
+  wire \gpio_defaults[289] ;
+  wire \gpio_defaults[28] ;
+  wire \gpio_defaults[290] ;
+  wire \gpio_defaults[291] ;
+  wire \gpio_defaults[292] ;
+  wire \gpio_defaults[293] ;
+  wire \gpio_defaults[294] ;
+  wire \gpio_defaults[295] ;
+  wire \gpio_defaults[296] ;
+  wire \gpio_defaults[297] ;
+  wire \gpio_defaults[298] ;
+  wire \gpio_defaults[299] ;
+  wire \gpio_defaults[29] ;
+  wire \gpio_defaults[2] ;
+  wire \gpio_defaults[300] ;
+  wire \gpio_defaults[301] ;
+  wire \gpio_defaults[302] ;
+  wire \gpio_defaults[303] ;
+  wire \gpio_defaults[304] ;
+  wire \gpio_defaults[305] ;
+  wire \gpio_defaults[306] ;
+  wire \gpio_defaults[307] ;
+  wire \gpio_defaults[308] ;
+  wire \gpio_defaults[309] ;
+  wire \gpio_defaults[30] ;
+  wire \gpio_defaults[310] ;
+  wire \gpio_defaults[311] ;
+  wire \gpio_defaults[312] ;
+  wire \gpio_defaults[313] ;
+  wire \gpio_defaults[314] ;
+  wire \gpio_defaults[315] ;
+  wire \gpio_defaults[316] ;
+  wire \gpio_defaults[317] ;
+  wire \gpio_defaults[318] ;
+  wire \gpio_defaults[319] ;
+  wire \gpio_defaults[31] ;
+  wire \gpio_defaults[320] ;
+  wire \gpio_defaults[321] ;
+  wire \gpio_defaults[322] ;
+  wire \gpio_defaults[323] ;
+  wire \gpio_defaults[324] ;
+  wire \gpio_defaults[325] ;
+  wire \gpio_defaults[326] ;
+  wire \gpio_defaults[327] ;
+  wire \gpio_defaults[328] ;
+  wire \gpio_defaults[329] ;
+  wire \gpio_defaults[32] ;
+  wire \gpio_defaults[330] ;
+  wire \gpio_defaults[331] ;
+  wire \gpio_defaults[332] ;
+  wire \gpio_defaults[333] ;
+  wire \gpio_defaults[334] ;
+  wire \gpio_defaults[335] ;
+  wire \gpio_defaults[336] ;
+  wire \gpio_defaults[337] ;
+  wire \gpio_defaults[338] ;
+  wire \gpio_defaults[339] ;
+  wire \gpio_defaults[33] ;
+  wire \gpio_defaults[340] ;
+  wire \gpio_defaults[341] ;
+  wire \gpio_defaults[342] ;
+  wire \gpio_defaults[343] ;
+  wire \gpio_defaults[344] ;
+  wire \gpio_defaults[345] ;
+  wire \gpio_defaults[346] ;
+  wire \gpio_defaults[347] ;
+  wire \gpio_defaults[348] ;
+  wire \gpio_defaults[349] ;
+  wire \gpio_defaults[34] ;
+  wire \gpio_defaults[350] ;
+  wire \gpio_defaults[351] ;
+  wire \gpio_defaults[352] ;
+  wire \gpio_defaults[353] ;
+  wire \gpio_defaults[354] ;
+  wire \gpio_defaults[355] ;
+  wire \gpio_defaults[356] ;
+  wire \gpio_defaults[357] ;
+  wire \gpio_defaults[358] ;
+  wire \gpio_defaults[359] ;
+  wire \gpio_defaults[35] ;
+  wire \gpio_defaults[360] ;
+  wire \gpio_defaults[361] ;
+  wire \gpio_defaults[362] ;
+  wire \gpio_defaults[363] ;
+  wire \gpio_defaults[364] ;
+  wire \gpio_defaults[365] ;
+  wire \gpio_defaults[366] ;
+  wire \gpio_defaults[367] ;
+  wire \gpio_defaults[368] ;
+  wire \gpio_defaults[369] ;
+  wire \gpio_defaults[36] ;
+  wire \gpio_defaults[370] ;
+  wire \gpio_defaults[371] ;
+  wire \gpio_defaults[372] ;
+  wire \gpio_defaults[373] ;
+  wire \gpio_defaults[374] ;
+  wire \gpio_defaults[375] ;
+  wire \gpio_defaults[376] ;
+  wire \gpio_defaults[377] ;
+  wire \gpio_defaults[378] ;
+  wire \gpio_defaults[379] ;
+  wire \gpio_defaults[37] ;
+  wire \gpio_defaults[380] ;
+  wire \gpio_defaults[381] ;
+  wire \gpio_defaults[382] ;
+  wire \gpio_defaults[383] ;
+  wire \gpio_defaults[384] ;
+  wire \gpio_defaults[385] ;
+  wire \gpio_defaults[386] ;
+  wire \gpio_defaults[387] ;
+  wire \gpio_defaults[388] ;
+  wire \gpio_defaults[389] ;
+  wire \gpio_defaults[38] ;
+  wire \gpio_defaults[390] ;
+  wire \gpio_defaults[391] ;
+  wire \gpio_defaults[392] ;
+  wire \gpio_defaults[393] ;
+  wire \gpio_defaults[394] ;
+  wire \gpio_defaults[395] ;
+  wire \gpio_defaults[396] ;
+  wire \gpio_defaults[397] ;
+  wire \gpio_defaults[398] ;
+  wire \gpio_defaults[399] ;
+  wire \gpio_defaults[39] ;
+  wire \gpio_defaults[3] ;
+  wire \gpio_defaults[400] ;
+  wire \gpio_defaults[401] ;
+  wire \gpio_defaults[402] ;
+  wire \gpio_defaults[403] ;
+  wire \gpio_defaults[404] ;
+  wire \gpio_defaults[405] ;
+  wire \gpio_defaults[406] ;
+  wire \gpio_defaults[407] ;
+  wire \gpio_defaults[408] ;
+  wire \gpio_defaults[409] ;
+  wire \gpio_defaults[40] ;
+  wire \gpio_defaults[410] ;
+  wire \gpio_defaults[411] ;
+  wire \gpio_defaults[412] ;
+  wire \gpio_defaults[413] ;
+  wire \gpio_defaults[414] ;
+  wire \gpio_defaults[415] ;
+  wire \gpio_defaults[416] ;
+  wire \gpio_defaults[417] ;
+  wire \gpio_defaults[418] ;
+  wire \gpio_defaults[419] ;
+  wire \gpio_defaults[41] ;
+  wire \gpio_defaults[420] ;
+  wire \gpio_defaults[421] ;
+  wire \gpio_defaults[422] ;
+  wire \gpio_defaults[423] ;
+  wire \gpio_defaults[424] ;
+  wire \gpio_defaults[425] ;
+  wire \gpio_defaults[426] ;
+  wire \gpio_defaults[427] ;
+  wire \gpio_defaults[428] ;
+  wire \gpio_defaults[429] ;
+  wire \gpio_defaults[42] ;
+  wire \gpio_defaults[430] ;
+  wire \gpio_defaults[431] ;
+  wire \gpio_defaults[432] ;
+  wire \gpio_defaults[433] ;
+  wire \gpio_defaults[434] ;
+  wire \gpio_defaults[435] ;
+  wire \gpio_defaults[436] ;
+  wire \gpio_defaults[437] ;
+  wire \gpio_defaults[438] ;
+  wire \gpio_defaults[439] ;
+  wire \gpio_defaults[43] ;
+  wire \gpio_defaults[440] ;
+  wire \gpio_defaults[441] ;
+  wire \gpio_defaults[442] ;
+  wire \gpio_defaults[443] ;
+  wire \gpio_defaults[444] ;
+  wire \gpio_defaults[445] ;
+  wire \gpio_defaults[446] ;
+  wire \gpio_defaults[447] ;
+  wire \gpio_defaults[448] ;
+  wire \gpio_defaults[449] ;
+  wire \gpio_defaults[44] ;
+  wire \gpio_defaults[450] ;
+  wire \gpio_defaults[451] ;
+  wire \gpio_defaults[452] ;
+  wire \gpio_defaults[453] ;
+  wire \gpio_defaults[454] ;
+  wire \gpio_defaults[455] ;
+  wire \gpio_defaults[456] ;
+  wire \gpio_defaults[457] ;
+  wire \gpio_defaults[458] ;
+  wire \gpio_defaults[459] ;
+  wire \gpio_defaults[45] ;
+  wire \gpio_defaults[460] ;
+  wire \gpio_defaults[461] ;
+  wire \gpio_defaults[462] ;
+  wire \gpio_defaults[463] ;
+  wire \gpio_defaults[464] ;
+  wire \gpio_defaults[465] ;
+  wire \gpio_defaults[466] ;
+  wire \gpio_defaults[467] ;
+  wire \gpio_defaults[468] ;
+  wire \gpio_defaults[469] ;
+  wire \gpio_defaults[46] ;
+  wire \gpio_defaults[470] ;
+  wire \gpio_defaults[471] ;
+  wire \gpio_defaults[472] ;
+  wire \gpio_defaults[473] ;
+  wire \gpio_defaults[474] ;
+  wire \gpio_defaults[475] ;
+  wire \gpio_defaults[476] ;
+  wire \gpio_defaults[477] ;
+  wire \gpio_defaults[478] ;
+  wire \gpio_defaults[479] ;
+  wire \gpio_defaults[47] ;
+  wire \gpio_defaults[480] ;
+  wire \gpio_defaults[481] ;
+  wire \gpio_defaults[482] ;
+  wire \gpio_defaults[483] ;
+  wire \gpio_defaults[484] ;
+  wire \gpio_defaults[485] ;
+  wire \gpio_defaults[486] ;
+  wire \gpio_defaults[487] ;
+  wire \gpio_defaults[488] ;
+  wire \gpio_defaults[489] ;
+  wire \gpio_defaults[48] ;
+  wire \gpio_defaults[490] ;
+  wire \gpio_defaults[491] ;
+  wire \gpio_defaults[492] ;
+  wire \gpio_defaults[493] ;
+  wire \gpio_defaults[49] ;
+  wire \gpio_defaults[4] ;
+  wire \gpio_defaults[50] ;
+  wire \gpio_defaults[51] ;
+  wire \gpio_defaults[52] ;
+  wire \gpio_defaults[53] ;
+  wire \gpio_defaults[54] ;
+  wire \gpio_defaults[55] ;
+  wire \gpio_defaults[56] ;
+  wire \gpio_defaults[57] ;
+  wire \gpio_defaults[58] ;
+  wire \gpio_defaults[59] ;
+  wire \gpio_defaults[5] ;
+  wire \gpio_defaults[60] ;
+  wire \gpio_defaults[61] ;
+  wire \gpio_defaults[62] ;
+  wire \gpio_defaults[63] ;
+  wire \gpio_defaults[64] ;
+  wire \gpio_defaults[65] ;
+  wire \gpio_defaults[66] ;
+  wire \gpio_defaults[67] ;
+  wire \gpio_defaults[68] ;
+  wire \gpio_defaults[69] ;
+  wire \gpio_defaults[6] ;
+  wire \gpio_defaults[70] ;
+  wire \gpio_defaults[71] ;
+  wire \gpio_defaults[72] ;
+  wire \gpio_defaults[73] ;
+  wire \gpio_defaults[74] ;
+  wire \gpio_defaults[75] ;
+  wire \gpio_defaults[76] ;
+  wire \gpio_defaults[77] ;
+  wire \gpio_defaults[78] ;
+  wire \gpio_defaults[79] ;
+  wire \gpio_defaults[7] ;
+  wire \gpio_defaults[80] ;
+  wire \gpio_defaults[81] ;
+  wire \gpio_defaults[82] ;
+  wire \gpio_defaults[83] ;
+  wire \gpio_defaults[84] ;
+  wire \gpio_defaults[85] ;
+  wire \gpio_defaults[86] ;
+  wire \gpio_defaults[87] ;
+  wire \gpio_defaults[88] ;
+  wire \gpio_defaults[89] ;
+  wire \gpio_defaults[8] ;
+  wire \gpio_defaults[90] ;
+  wire \gpio_defaults[91] ;
+  wire \gpio_defaults[92] ;
+  wire \gpio_defaults[93] ;
+  wire \gpio_defaults[94] ;
+  wire \gpio_defaults[95] ;
+  wire \gpio_defaults[96] ;
+  wire \gpio_defaults[97] ;
+  wire \gpio_defaults[98] ;
+  wire \gpio_defaults[99] ;
+  wire \gpio_defaults[9] ;
+  wire gpio_in_core;
+  wire gpio_inenb_core;
+  wire \gpio_load_1[0] ;
+  wire \gpio_load_1[10] ;
+  wire \gpio_load_1[11] ;
+  wire \gpio_load_1[12] ;
+  wire \gpio_load_1[13] ;
+  wire \gpio_load_1[14] ;
+  wire \gpio_load_1[15] ;
+  wire \gpio_load_1[16] ;
+  wire \gpio_load_1[17] ;
+  wire \gpio_load_1[18] ;
+  wire \gpio_load_1[1] ;
+  wire \gpio_load_1[2] ;
+  wire \gpio_load_1[3] ;
+  wire \gpio_load_1[4] ;
+  wire \gpio_load_1[5] ;
+  wire \gpio_load_1[6] ;
+  wire \gpio_load_1[7] ;
+  wire \gpio_load_1[8] ;
+  wire \gpio_load_1[9] ;
+  wire \gpio_load_1_shifted[0] ;
+  wire \gpio_load_1_shifted[10] ;
+  wire \gpio_load_1_shifted[11] ;
+  wire \gpio_load_1_shifted[12] ;
+  wire \gpio_load_1_shifted[13] ;
+  wire \gpio_load_1_shifted[14] ;
+  wire \gpio_load_1_shifted[15] ;
+  wire \gpio_load_1_shifted[16] ;
+  wire \gpio_load_1_shifted[17] ;
+  wire \gpio_load_1_shifted[18] ;
+  wire \gpio_load_1_shifted[1] ;
+  wire \gpio_load_1_shifted[2] ;
+  wire \gpio_load_1_shifted[3] ;
+  wire \gpio_load_1_shifted[4] ;
+  wire \gpio_load_1_shifted[5] ;
+  wire \gpio_load_1_shifted[6] ;
+  wire \gpio_load_1_shifted[7] ;
+  wire \gpio_load_1_shifted[8] ;
+  wire \gpio_load_1_shifted[9] ;
+  wire \gpio_load_2[0] ;
+  wire \gpio_load_2[10] ;
+  wire \gpio_load_2[11] ;
+  wire \gpio_load_2[12] ;
+  wire \gpio_load_2[13] ;
+  wire \gpio_load_2[14] ;
+  wire \gpio_load_2[15] ;
+  wire \gpio_load_2[16] ;
+  wire \gpio_load_2[17] ;
+  wire \gpio_load_2[18] ;
+  wire \gpio_load_2[1] ;
+  wire \gpio_load_2[2] ;
+  wire \gpio_load_2[3] ;
+  wire \gpio_load_2[4] ;
+  wire \gpio_load_2[5] ;
+  wire \gpio_load_2[6] ;
+  wire \gpio_load_2[7] ;
+  wire \gpio_load_2[8] ;
+  wire \gpio_load_2[9] ;
+  wire \gpio_load_2_shifted[0] ;
+  wire \gpio_load_2_shifted[10] ;
+  wire \gpio_load_2_shifted[11] ;
+  wire \gpio_load_2_shifted[12] ;
+  wire \gpio_load_2_shifted[13] ;
+  wire \gpio_load_2_shifted[14] ;
+  wire \gpio_load_2_shifted[15] ;
+  wire \gpio_load_2_shifted[16] ;
+  wire \gpio_load_2_shifted[17] ;
+  wire \gpio_load_2_shifted[18] ;
+  wire \gpio_load_2_shifted[1] ;
+  wire \gpio_load_2_shifted[2] ;
+  wire \gpio_load_2_shifted[3] ;
+  wire \gpio_load_2_shifted[4] ;
+  wire \gpio_load_2_shifted[5] ;
+  wire \gpio_load_2_shifted[6] ;
+  wire \gpio_load_2_shifted[7] ;
+  wire \gpio_load_2_shifted[8] ;
+  wire \gpio_load_2_shifted[9] ;
+  wire gpio_mode0_core;
+  wire gpio_mode1_core;
+  wire gpio_out_core;
+  wire gpio_outenb_core;
+  wire \gpio_resetn_1[0] ;
+  wire \gpio_resetn_1[10] ;
+  wire \gpio_resetn_1[11] ;
+  wire \gpio_resetn_1[12] ;
+  wire \gpio_resetn_1[13] ;
+  wire \gpio_resetn_1[14] ;
+  wire \gpio_resetn_1[15] ;
+  wire \gpio_resetn_1[16] ;
+  wire \gpio_resetn_1[17] ;
+  wire \gpio_resetn_1[18] ;
+  wire \gpio_resetn_1[1] ;
+  wire \gpio_resetn_1[2] ;
+  wire \gpio_resetn_1[3] ;
+  wire \gpio_resetn_1[4] ;
+  wire \gpio_resetn_1[5] ;
+  wire \gpio_resetn_1[6] ;
+  wire \gpio_resetn_1[7] ;
+  wire \gpio_resetn_1[8] ;
+  wire \gpio_resetn_1[9] ;
+  wire \gpio_resetn_1_shifted[0] ;
+  wire \gpio_resetn_1_shifted[10] ;
+  wire \gpio_resetn_1_shifted[11] ;
+  wire \gpio_resetn_1_shifted[12] ;
+  wire \gpio_resetn_1_shifted[13] ;
+  wire \gpio_resetn_1_shifted[14] ;
+  wire \gpio_resetn_1_shifted[15] ;
+  wire \gpio_resetn_1_shifted[16] ;
+  wire \gpio_resetn_1_shifted[17] ;
+  wire \gpio_resetn_1_shifted[18] ;
+  wire \gpio_resetn_1_shifted[1] ;
+  wire \gpio_resetn_1_shifted[2] ;
+  wire \gpio_resetn_1_shifted[3] ;
+  wire \gpio_resetn_1_shifted[4] ;
+  wire \gpio_resetn_1_shifted[5] ;
+  wire \gpio_resetn_1_shifted[6] ;
+  wire \gpio_resetn_1_shifted[7] ;
+  wire \gpio_resetn_1_shifted[8] ;
+  wire \gpio_resetn_1_shifted[9] ;
+  wire \gpio_resetn_2[0] ;
+  wire \gpio_resetn_2[10] ;
+  wire \gpio_resetn_2[11] ;
+  wire \gpio_resetn_2[12] ;
+  wire \gpio_resetn_2[13] ;
+  wire \gpio_resetn_2[14] ;
+  wire \gpio_resetn_2[15] ;
+  wire \gpio_resetn_2[16] ;
+  wire \gpio_resetn_2[17] ;
+  wire \gpio_resetn_2[18] ;
+  wire \gpio_resetn_2[1] ;
+  wire \gpio_resetn_2[2] ;
+  wire \gpio_resetn_2[3] ;
+  wire \gpio_resetn_2[4] ;
+  wire \gpio_resetn_2[5] ;
+  wire \gpio_resetn_2[6] ;
+  wire \gpio_resetn_2[7] ;
+  wire \gpio_resetn_2[8] ;
+  wire \gpio_resetn_2[9] ;
+  wire \gpio_resetn_2_shifted[0] ;
+  wire \gpio_resetn_2_shifted[10] ;
+  wire \gpio_resetn_2_shifted[11] ;
+  wire \gpio_resetn_2_shifted[12] ;
+  wire \gpio_resetn_2_shifted[13] ;
+  wire \gpio_resetn_2_shifted[14] ;
+  wire \gpio_resetn_2_shifted[15] ;
+  wire \gpio_resetn_2_shifted[16] ;
+  wire \gpio_resetn_2_shifted[17] ;
+  wire \gpio_resetn_2_shifted[18] ;
+  wire \gpio_resetn_2_shifted[1] ;
+  wire \gpio_resetn_2_shifted[2] ;
+  wire \gpio_resetn_2_shifted[3] ;
+  wire \gpio_resetn_2_shifted[4] ;
+  wire \gpio_resetn_2_shifted[5] ;
+  wire \gpio_resetn_2_shifted[6] ;
+  wire \gpio_resetn_2_shifted[7] ;
+  wire \gpio_resetn_2_shifted[8] ;
+  wire \gpio_resetn_2_shifted[9] ;
+  wire \gpio_serial_link_1[0] ;
+  wire \gpio_serial_link_1[10] ;
+  wire \gpio_serial_link_1[11] ;
+  wire \gpio_serial_link_1[12] ;
+  wire \gpio_serial_link_1[13] ;
+  wire \gpio_serial_link_1[14] ;
+  wire \gpio_serial_link_1[15] ;
+  wire \gpio_serial_link_1[16] ;
+  wire \gpio_serial_link_1[17] ;
+  wire \gpio_serial_link_1[18] ;
+  wire \gpio_serial_link_1[1] ;
+  wire \gpio_serial_link_1[2] ;
+  wire \gpio_serial_link_1[3] ;
+  wire \gpio_serial_link_1[4] ;
+  wire \gpio_serial_link_1[5] ;
+  wire \gpio_serial_link_1[6] ;
+  wire \gpio_serial_link_1[7] ;
+  wire \gpio_serial_link_1[8] ;
+  wire \gpio_serial_link_1[9] ;
+  wire \gpio_serial_link_1_shifted[0] ;
+  wire \gpio_serial_link_1_shifted[10] ;
+  wire \gpio_serial_link_1_shifted[11] ;
+  wire \gpio_serial_link_1_shifted[12] ;
+  wire \gpio_serial_link_1_shifted[13] ;
+  wire \gpio_serial_link_1_shifted[14] ;
+  wire \gpio_serial_link_1_shifted[15] ;
+  wire \gpio_serial_link_1_shifted[16] ;
+  wire \gpio_serial_link_1_shifted[17] ;
+  wire \gpio_serial_link_1_shifted[18] ;
+  wire \gpio_serial_link_1_shifted[1] ;
+  wire \gpio_serial_link_1_shifted[2] ;
+  wire \gpio_serial_link_1_shifted[3] ;
+  wire \gpio_serial_link_1_shifted[4] ;
+  wire \gpio_serial_link_1_shifted[5] ;
+  wire \gpio_serial_link_1_shifted[6] ;
+  wire \gpio_serial_link_1_shifted[7] ;
+  wire \gpio_serial_link_1_shifted[8] ;
+  wire \gpio_serial_link_1_shifted[9] ;
+  wire \gpio_serial_link_2[0] ;
+  wire \gpio_serial_link_2[10] ;
+  wire \gpio_serial_link_2[11] ;
+  wire \gpio_serial_link_2[12] ;
+  wire \gpio_serial_link_2[13] ;
+  wire \gpio_serial_link_2[14] ;
+  wire \gpio_serial_link_2[15] ;
+  wire \gpio_serial_link_2[16] ;
+  wire \gpio_serial_link_2[17] ;
+  wire \gpio_serial_link_2[18] ;
+  wire \gpio_serial_link_2[1] ;
+  wire \gpio_serial_link_2[2] ;
+  wire \gpio_serial_link_2[3] ;
+  wire \gpio_serial_link_2[4] ;
+  wire \gpio_serial_link_2[5] ;
+  wire \gpio_serial_link_2[6] ;
+  wire \gpio_serial_link_2[7] ;
+  wire \gpio_serial_link_2[8] ;
+  wire \gpio_serial_link_2[9] ;
+  wire \gpio_serial_link_2_shifted[0] ;
+  wire \gpio_serial_link_2_shifted[10] ;
+  wire \gpio_serial_link_2_shifted[11] ;
+  wire \gpio_serial_link_2_shifted[12] ;
+  wire \gpio_serial_link_2_shifted[13] ;
+  wire \gpio_serial_link_2_shifted[14] ;
+  wire \gpio_serial_link_2_shifted[15] ;
+  wire \gpio_serial_link_2_shifted[16] ;
+  wire \gpio_serial_link_2_shifted[17] ;
+  wire \gpio_serial_link_2_shifted[18] ;
+  wire \gpio_serial_link_2_shifted[1] ;
+  wire \gpio_serial_link_2_shifted[2] ;
+  wire \gpio_serial_link_2_shifted[3] ;
+  wire \gpio_serial_link_2_shifted[4] ;
+  wire \gpio_serial_link_2_shifted[5] ;
+  wire \gpio_serial_link_2_shifted[6] ;
+  wire \gpio_serial_link_2_shifted[7] ;
+  wire \gpio_serial_link_2_shifted[8] ;
+  wire \gpio_serial_link_2_shifted[9] ;
+  wire hk_ack_i;
+  wire \hk_dat_i[0] ;
+  wire \hk_dat_i[10] ;
+  wire \hk_dat_i[11] ;
+  wire \hk_dat_i[12] ;
+  wire \hk_dat_i[13] ;
+  wire \hk_dat_i[14] ;
+  wire \hk_dat_i[15] ;
+  wire \hk_dat_i[16] ;
+  wire \hk_dat_i[17] ;
+  wire \hk_dat_i[18] ;
+  wire \hk_dat_i[19] ;
+  wire \hk_dat_i[1] ;
+  wire \hk_dat_i[20] ;
+  wire \hk_dat_i[21] ;
+  wire \hk_dat_i[22] ;
+  wire \hk_dat_i[23] ;
+  wire \hk_dat_i[24] ;
+  wire \hk_dat_i[25] ;
+  wire \hk_dat_i[26] ;
+  wire \hk_dat_i[27] ;
+  wire \hk_dat_i[28] ;
+  wire \hk_dat_i[29] ;
+  wire \hk_dat_i[2] ;
+  wire \hk_dat_i[30] ;
+  wire \hk_dat_i[31] ;
+  wire \hk_dat_i[3] ;
+  wire \hk_dat_i[4] ;
+  wire \hk_dat_i[5] ;
+  wire \hk_dat_i[6] ;
+  wire \hk_dat_i[7] ;
+  wire \hk_dat_i[8] ;
+  wire \hk_dat_i[9] ;
+  wire hk_stb_o;
+  wire hk_cyc_o;
+  wire \hkspi_sram_addr[0] ;
+  wire \hkspi_sram_addr[1] ;
+  wire \hkspi_sram_addr[2] ;
+  wire \hkspi_sram_addr[3] ;
+  wire \hkspi_sram_addr[4] ;
+  wire \hkspi_sram_addr[5] ;
+  wire \hkspi_sram_addr[6] ;
+  wire \hkspi_sram_addr[7] ;
+  wire hkspi_sram_clk;
+  wire hkspi_sram_csb;
+  wire \hkspi_sram_data[0] ;
+  wire \hkspi_sram_data[10] ;
+  wire \hkspi_sram_data[11] ;
+  wire \hkspi_sram_data[12] ;
+  wire \hkspi_sram_data[13] ;
+  wire \hkspi_sram_data[14] ;
+  wire \hkspi_sram_data[15] ;
+  wire \hkspi_sram_data[16] ;
+  wire \hkspi_sram_data[17] ;
+  wire \hkspi_sram_data[18] ;
+  wire \hkspi_sram_data[19] ;
+  wire \hkspi_sram_data[1] ;
+  wire \hkspi_sram_data[20] ;
+  wire \hkspi_sram_data[21] ;
+  wire \hkspi_sram_data[22] ;
+  wire \hkspi_sram_data[23] ;
+  wire \hkspi_sram_data[24] ;
+  wire \hkspi_sram_data[25] ;
+  wire \hkspi_sram_data[26] ;
+  wire \hkspi_sram_data[27] ;
+  wire \hkspi_sram_data[28] ;
+  wire \hkspi_sram_data[29] ;
+  wire \hkspi_sram_data[2] ;
+  wire \hkspi_sram_data[30] ;
+  wire \hkspi_sram_data[31] ;
+  wire \hkspi_sram_data[3] ;
+  wire \hkspi_sram_data[4] ;
+  wire \hkspi_sram_data[5] ;
+  wire \hkspi_sram_data[6] ;
+  wire \hkspi_sram_data[7] ;
+  wire \hkspi_sram_data[8] ;
+  wire \hkspi_sram_data[9] ;
+  wire \irq_spi[0] ;
+  wire \irq_spi[1] ;
+  wire \irq_spi[2] ;
+  wire \la_data_in_mprj[0] ;
+  wire \la_data_in_mprj[100] ;
+  wire \la_data_in_mprj[101] ;
+  wire \la_data_in_mprj[102] ;
+  wire \la_data_in_mprj[103] ;
+  wire \la_data_in_mprj[104] ;
+  wire \la_data_in_mprj[105] ;
+  wire \la_data_in_mprj[106] ;
+  wire \la_data_in_mprj[107] ;
+  wire \la_data_in_mprj[108] ;
+  wire \la_data_in_mprj[109] ;
+  wire \la_data_in_mprj[10] ;
+  wire \la_data_in_mprj[110] ;
+  wire \la_data_in_mprj[111] ;
+  wire \la_data_in_mprj[112] ;
+  wire \la_data_in_mprj[113] ;
+  wire \la_data_in_mprj[114] ;
+  wire \la_data_in_mprj[115] ;
+  wire \la_data_in_mprj[116] ;
+  wire \la_data_in_mprj[117] ;
+  wire \la_data_in_mprj[118] ;
+  wire \la_data_in_mprj[119] ;
+  wire \la_data_in_mprj[11] ;
+  wire \la_data_in_mprj[120] ;
+  wire \la_data_in_mprj[121] ;
+  wire \la_data_in_mprj[122] ;
+  wire \la_data_in_mprj[123] ;
+  wire \la_data_in_mprj[124] ;
+  wire \la_data_in_mprj[125] ;
+  wire \la_data_in_mprj[126] ;
+  wire \la_data_in_mprj[127] ;
+  wire \la_data_in_mprj[12] ;
+  wire \la_data_in_mprj[13] ;
+  wire \la_data_in_mprj[14] ;
+  wire \la_data_in_mprj[15] ;
+  wire \la_data_in_mprj[16] ;
+  wire \la_data_in_mprj[17] ;
+  wire \la_data_in_mprj[18] ;
+  wire \la_data_in_mprj[19] ;
+  wire \la_data_in_mprj[1] ;
+  wire \la_data_in_mprj[20] ;
+  wire \la_data_in_mprj[21] ;
+  wire \la_data_in_mprj[22] ;
+  wire \la_data_in_mprj[23] ;
+  wire \la_data_in_mprj[24] ;
+  wire \la_data_in_mprj[25] ;
+  wire \la_data_in_mprj[26] ;
+  wire \la_data_in_mprj[27] ;
+  wire \la_data_in_mprj[28] ;
+  wire \la_data_in_mprj[29] ;
+  wire \la_data_in_mprj[2] ;
+  wire \la_data_in_mprj[30] ;
+  wire \la_data_in_mprj[31] ;
+  wire \la_data_in_mprj[32] ;
+  wire \la_data_in_mprj[33] ;
+  wire \la_data_in_mprj[34] ;
+  wire \la_data_in_mprj[35] ;
+  wire \la_data_in_mprj[36] ;
+  wire \la_data_in_mprj[37] ;
+  wire \la_data_in_mprj[38] ;
+  wire \la_data_in_mprj[39] ;
+  wire \la_data_in_mprj[3] ;
+  wire \la_data_in_mprj[40] ;
+  wire \la_data_in_mprj[41] ;
+  wire \la_data_in_mprj[42] ;
+  wire \la_data_in_mprj[43] ;
+  wire \la_data_in_mprj[44] ;
+  wire \la_data_in_mprj[45] ;
+  wire \la_data_in_mprj[46] ;
+  wire \la_data_in_mprj[47] ;
+  wire \la_data_in_mprj[48] ;
+  wire \la_data_in_mprj[49] ;
+  wire \la_data_in_mprj[4] ;
+  wire \la_data_in_mprj[50] ;
+  wire \la_data_in_mprj[51] ;
+  wire \la_data_in_mprj[52] ;
+  wire \la_data_in_mprj[53] ;
+  wire \la_data_in_mprj[54] ;
+  wire \la_data_in_mprj[55] ;
+  wire \la_data_in_mprj[56] ;
+  wire \la_data_in_mprj[57] ;
+  wire \la_data_in_mprj[58] ;
+  wire \la_data_in_mprj[59] ;
+  wire \la_data_in_mprj[5] ;
+  wire \la_data_in_mprj[60] ;
+  wire \la_data_in_mprj[61] ;
+  wire \la_data_in_mprj[62] ;
+  wire \la_data_in_mprj[63] ;
+  wire \la_data_in_mprj[64] ;
+  wire \la_data_in_mprj[65] ;
+  wire \la_data_in_mprj[66] ;
+  wire \la_data_in_mprj[67] ;
+  wire \la_data_in_mprj[68] ;
+  wire \la_data_in_mprj[69] ;
+  wire \la_data_in_mprj[6] ;
+  wire \la_data_in_mprj[70] ;
+  wire \la_data_in_mprj[71] ;
+  wire \la_data_in_mprj[72] ;
+  wire \la_data_in_mprj[73] ;
+  wire \la_data_in_mprj[74] ;
+  wire \la_data_in_mprj[75] ;
+  wire \la_data_in_mprj[76] ;
+  wire \la_data_in_mprj[77] ;
+  wire \la_data_in_mprj[78] ;
+  wire \la_data_in_mprj[79] ;
+  wire \la_data_in_mprj[7] ;
+  wire \la_data_in_mprj[80] ;
+  wire \la_data_in_mprj[81] ;
+  wire \la_data_in_mprj[82] ;
+  wire \la_data_in_mprj[83] ;
+  wire \la_data_in_mprj[84] ;
+  wire \la_data_in_mprj[85] ;
+  wire \la_data_in_mprj[86] ;
+  wire \la_data_in_mprj[87] ;
+  wire \la_data_in_mprj[88] ;
+  wire \la_data_in_mprj[89] ;
+  wire \la_data_in_mprj[8] ;
+  wire \la_data_in_mprj[90] ;
+  wire \la_data_in_mprj[91] ;
+  wire \la_data_in_mprj[92] ;
+  wire \la_data_in_mprj[93] ;
+  wire \la_data_in_mprj[94] ;
+  wire \la_data_in_mprj[95] ;
+  wire \la_data_in_mprj[96] ;
+  wire \la_data_in_mprj[97] ;
+  wire \la_data_in_mprj[98] ;
+  wire \la_data_in_mprj[99] ;
+  wire \la_data_in_mprj[9] ;
+  wire \la_data_in_user[0] ;
+  wire \la_data_in_user[100] ;
+  wire \la_data_in_user[101] ;
+  wire \la_data_in_user[102] ;
+  wire \la_data_in_user[103] ;
+  wire \la_data_in_user[104] ;
+  wire \la_data_in_user[105] ;
+  wire \la_data_in_user[106] ;
+  wire \la_data_in_user[107] ;
+  wire \la_data_in_user[108] ;
+  wire \la_data_in_user[109] ;
+  wire \la_data_in_user[10] ;
+  wire \la_data_in_user[110] ;
+  wire \la_data_in_user[111] ;
+  wire \la_data_in_user[112] ;
+  wire \la_data_in_user[113] ;
+  wire \la_data_in_user[114] ;
+  wire \la_data_in_user[115] ;
+  wire \la_data_in_user[116] ;
+  wire \la_data_in_user[117] ;
+  wire \la_data_in_user[118] ;
+  wire \la_data_in_user[119] ;
+  wire \la_data_in_user[11] ;
+  wire \la_data_in_user[120] ;
+  wire \la_data_in_user[121] ;
+  wire \la_data_in_user[122] ;
+  wire \la_data_in_user[123] ;
+  wire \la_data_in_user[124] ;
+  wire \la_data_in_user[125] ;
+  wire \la_data_in_user[126] ;
+  wire \la_data_in_user[127] ;
+  wire \la_data_in_user[12] ;
+  wire \la_data_in_user[13] ;
+  wire \la_data_in_user[14] ;
+  wire \la_data_in_user[15] ;
+  wire \la_data_in_user[16] ;
+  wire \la_data_in_user[17] ;
+  wire \la_data_in_user[18] ;
+  wire \la_data_in_user[19] ;
+  wire \la_data_in_user[1] ;
+  wire \la_data_in_user[20] ;
+  wire \la_data_in_user[21] ;
+  wire \la_data_in_user[22] ;
+  wire \la_data_in_user[23] ;
+  wire \la_data_in_user[24] ;
+  wire \la_data_in_user[25] ;
+  wire \la_data_in_user[26] ;
+  wire \la_data_in_user[27] ;
+  wire \la_data_in_user[28] ;
+  wire \la_data_in_user[29] ;
+  wire \la_data_in_user[2] ;
+  wire \la_data_in_user[30] ;
+  wire \la_data_in_user[31] ;
+  wire \la_data_in_user[32] ;
+  wire \la_data_in_user[33] ;
+  wire \la_data_in_user[34] ;
+  wire \la_data_in_user[35] ;
+  wire \la_data_in_user[36] ;
+  wire \la_data_in_user[37] ;
+  wire \la_data_in_user[38] ;
+  wire \la_data_in_user[39] ;
+  wire \la_data_in_user[3] ;
+  wire \la_data_in_user[40] ;
+  wire \la_data_in_user[41] ;
+  wire \la_data_in_user[42] ;
+  wire \la_data_in_user[43] ;
+  wire \la_data_in_user[44] ;
+  wire \la_data_in_user[45] ;
+  wire \la_data_in_user[46] ;
+  wire \la_data_in_user[47] ;
+  wire \la_data_in_user[48] ;
+  wire \la_data_in_user[49] ;
+  wire \la_data_in_user[4] ;
+  wire \la_data_in_user[50] ;
+  wire \la_data_in_user[51] ;
+  wire \la_data_in_user[52] ;
+  wire \la_data_in_user[53] ;
+  wire \la_data_in_user[54] ;
+  wire \la_data_in_user[55] ;
+  wire \la_data_in_user[56] ;
+  wire \la_data_in_user[57] ;
+  wire \la_data_in_user[58] ;
+  wire \la_data_in_user[59] ;
+  wire \la_data_in_user[5] ;
+  wire \la_data_in_user[60] ;
+  wire \la_data_in_user[61] ;
+  wire \la_data_in_user[62] ;
+  wire \la_data_in_user[63] ;
+  wire \la_data_in_user[64] ;
+  wire \la_data_in_user[65] ;
+  wire \la_data_in_user[66] ;
+  wire \la_data_in_user[67] ;
+  wire \la_data_in_user[68] ;
+  wire \la_data_in_user[69] ;
+  wire \la_data_in_user[6] ;
+  wire \la_data_in_user[70] ;
+  wire \la_data_in_user[71] ;
+  wire \la_data_in_user[72] ;
+  wire \la_data_in_user[73] ;
+  wire \la_data_in_user[74] ;
+  wire \la_data_in_user[75] ;
+  wire \la_data_in_user[76] ;
+  wire \la_data_in_user[77] ;
+  wire \la_data_in_user[78] ;
+  wire \la_data_in_user[79] ;
+  wire \la_data_in_user[7] ;
+  wire \la_data_in_user[80] ;
+  wire \la_data_in_user[81] ;
+  wire \la_data_in_user[82] ;
+  wire \la_data_in_user[83] ;
+  wire \la_data_in_user[84] ;
+  wire \la_data_in_user[85] ;
+  wire \la_data_in_user[86] ;
+  wire \la_data_in_user[87] ;
+  wire \la_data_in_user[88] ;
+  wire \la_data_in_user[89] ;
+  wire \la_data_in_user[8] ;
+  wire \la_data_in_user[90] ;
+  wire \la_data_in_user[91] ;
+  wire \la_data_in_user[92] ;
+  wire \la_data_in_user[93] ;
+  wire \la_data_in_user[94] ;
+  wire \la_data_in_user[95] ;
+  wire \la_data_in_user[96] ;
+  wire \la_data_in_user[97] ;
+  wire \la_data_in_user[98] ;
+  wire \la_data_in_user[99] ;
+  wire \la_data_in_user[9] ;
+  wire \la_data_out_mprj[0] ;
+  wire \la_data_out_mprj[100] ;
+  wire \la_data_out_mprj[101] ;
+  wire \la_data_out_mprj[102] ;
+  wire \la_data_out_mprj[103] ;
+  wire \la_data_out_mprj[104] ;
+  wire \la_data_out_mprj[105] ;
+  wire \la_data_out_mprj[106] ;
+  wire \la_data_out_mprj[107] ;
+  wire \la_data_out_mprj[108] ;
+  wire \la_data_out_mprj[109] ;
+  wire \la_data_out_mprj[10] ;
+  wire \la_data_out_mprj[110] ;
+  wire \la_data_out_mprj[111] ;
+  wire \la_data_out_mprj[112] ;
+  wire \la_data_out_mprj[113] ;
+  wire \la_data_out_mprj[114] ;
+  wire \la_data_out_mprj[115] ;
+  wire \la_data_out_mprj[116] ;
+  wire \la_data_out_mprj[117] ;
+  wire \la_data_out_mprj[118] ;
+  wire \la_data_out_mprj[119] ;
+  wire \la_data_out_mprj[11] ;
+  wire \la_data_out_mprj[120] ;
+  wire \la_data_out_mprj[121] ;
+  wire \la_data_out_mprj[122] ;
+  wire \la_data_out_mprj[123] ;
+  wire \la_data_out_mprj[124] ;
+  wire \la_data_out_mprj[125] ;
+  wire \la_data_out_mprj[126] ;
+  wire \la_data_out_mprj[127] ;
+  wire \la_data_out_mprj[12] ;
+  wire \la_data_out_mprj[13] ;
+  wire \la_data_out_mprj[14] ;
+  wire \la_data_out_mprj[15] ;
+  wire \la_data_out_mprj[16] ;
+  wire \la_data_out_mprj[17] ;
+  wire \la_data_out_mprj[18] ;
+  wire \la_data_out_mprj[19] ;
+  wire \la_data_out_mprj[1] ;
+  wire \la_data_out_mprj[20] ;
+  wire \la_data_out_mprj[21] ;
+  wire \la_data_out_mprj[22] ;
+  wire \la_data_out_mprj[23] ;
+  wire \la_data_out_mprj[24] ;
+  wire \la_data_out_mprj[25] ;
+  wire \la_data_out_mprj[26] ;
+  wire \la_data_out_mprj[27] ;
+  wire \la_data_out_mprj[28] ;
+  wire \la_data_out_mprj[29] ;
+  wire \la_data_out_mprj[2] ;
+  wire \la_data_out_mprj[30] ;
+  wire \la_data_out_mprj[31] ;
+  wire \la_data_out_mprj[32] ;
+  wire \la_data_out_mprj[33] ;
+  wire \la_data_out_mprj[34] ;
+  wire \la_data_out_mprj[35] ;
+  wire \la_data_out_mprj[36] ;
+  wire \la_data_out_mprj[37] ;
+  wire \la_data_out_mprj[38] ;
+  wire \la_data_out_mprj[39] ;
+  wire \la_data_out_mprj[3] ;
+  wire \la_data_out_mprj[40] ;
+  wire \la_data_out_mprj[41] ;
+  wire \la_data_out_mprj[42] ;
+  wire \la_data_out_mprj[43] ;
+  wire \la_data_out_mprj[44] ;
+  wire \la_data_out_mprj[45] ;
+  wire \la_data_out_mprj[46] ;
+  wire \la_data_out_mprj[47] ;
+  wire \la_data_out_mprj[48] ;
+  wire \la_data_out_mprj[49] ;
+  wire \la_data_out_mprj[4] ;
+  wire \la_data_out_mprj[50] ;
+  wire \la_data_out_mprj[51] ;
+  wire \la_data_out_mprj[52] ;
+  wire \la_data_out_mprj[53] ;
+  wire \la_data_out_mprj[54] ;
+  wire \la_data_out_mprj[55] ;
+  wire \la_data_out_mprj[56] ;
+  wire \la_data_out_mprj[57] ;
+  wire \la_data_out_mprj[58] ;
+  wire \la_data_out_mprj[59] ;
+  wire \la_data_out_mprj[5] ;
+  wire \la_data_out_mprj[60] ;
+  wire \la_data_out_mprj[61] ;
+  wire \la_data_out_mprj[62] ;
+  wire \la_data_out_mprj[63] ;
+  wire \la_data_out_mprj[64] ;
+  wire \la_data_out_mprj[65] ;
+  wire \la_data_out_mprj[66] ;
+  wire \la_data_out_mprj[67] ;
+  wire \la_data_out_mprj[68] ;
+  wire \la_data_out_mprj[69] ;
+  wire \la_data_out_mprj[6] ;
+  wire \la_data_out_mprj[70] ;
+  wire \la_data_out_mprj[71] ;
+  wire \la_data_out_mprj[72] ;
+  wire \la_data_out_mprj[73] ;
+  wire \la_data_out_mprj[74] ;
+  wire \la_data_out_mprj[75] ;
+  wire \la_data_out_mprj[76] ;
+  wire \la_data_out_mprj[77] ;
+  wire \la_data_out_mprj[78] ;
+  wire \la_data_out_mprj[79] ;
+  wire \la_data_out_mprj[7] ;
+  wire \la_data_out_mprj[80] ;
+  wire \la_data_out_mprj[81] ;
+  wire \la_data_out_mprj[82] ;
+  wire \la_data_out_mprj[83] ;
+  wire \la_data_out_mprj[84] ;
+  wire \la_data_out_mprj[85] ;
+  wire \la_data_out_mprj[86] ;
+  wire \la_data_out_mprj[87] ;
+  wire \la_data_out_mprj[88] ;
+  wire \la_data_out_mprj[89] ;
+  wire \la_data_out_mprj[8] ;
+  wire \la_data_out_mprj[90] ;
+  wire \la_data_out_mprj[91] ;
+  wire \la_data_out_mprj[92] ;
+  wire \la_data_out_mprj[93] ;
+  wire \la_data_out_mprj[94] ;
+  wire \la_data_out_mprj[95] ;
+  wire \la_data_out_mprj[96] ;
+  wire \la_data_out_mprj[97] ;
+  wire \la_data_out_mprj[98] ;
+  wire \la_data_out_mprj[99] ;
+  wire \la_data_out_mprj[9] ;
+  wire \la_data_out_user[0] ;
+  wire \la_data_out_user[100] ;
+  wire \la_data_out_user[101] ;
+  wire \la_data_out_user[102] ;
+  wire \la_data_out_user[103] ;
+  wire \la_data_out_user[104] ;
+  wire \la_data_out_user[105] ;
+  wire \la_data_out_user[106] ;
+  wire \la_data_out_user[107] ;
+  wire \la_data_out_user[108] ;
+  wire \la_data_out_user[109] ;
+  wire \la_data_out_user[10] ;
+  wire \la_data_out_user[110] ;
+  wire \la_data_out_user[111] ;
+  wire \la_data_out_user[112] ;
+  wire \la_data_out_user[113] ;
+  wire \la_data_out_user[114] ;
+  wire \la_data_out_user[115] ;
+  wire \la_data_out_user[116] ;
+  wire \la_data_out_user[117] ;
+  wire \la_data_out_user[118] ;
+  wire \la_data_out_user[119] ;
+  wire \la_data_out_user[11] ;
+  wire \la_data_out_user[120] ;
+  wire \la_data_out_user[121] ;
+  wire \la_data_out_user[122] ;
+  wire \la_data_out_user[123] ;
+  wire \la_data_out_user[124] ;
+  wire \la_data_out_user[125] ;
+  wire \la_data_out_user[126] ;
+  wire \la_data_out_user[127] ;
+  wire \la_data_out_user[12] ;
+  wire \la_data_out_user[13] ;
+  wire \la_data_out_user[14] ;
+  wire \la_data_out_user[15] ;
+  wire \la_data_out_user[16] ;
+  wire \la_data_out_user[17] ;
+  wire \la_data_out_user[18] ;
+  wire \la_data_out_user[19] ;
+  wire \la_data_out_user[1] ;
+  wire \la_data_out_user[20] ;
+  wire \la_data_out_user[21] ;
+  wire \la_data_out_user[22] ;
+  wire \la_data_out_user[23] ;
+  wire \la_data_out_user[24] ;
+  wire \la_data_out_user[25] ;
+  wire \la_data_out_user[26] ;
+  wire \la_data_out_user[27] ;
+  wire \la_data_out_user[28] ;
+  wire \la_data_out_user[29] ;
+  wire \la_data_out_user[2] ;
+  wire \la_data_out_user[30] ;
+  wire \la_data_out_user[31] ;
+  wire \la_data_out_user[32] ;
+  wire \la_data_out_user[33] ;
+  wire \la_data_out_user[34] ;
+  wire \la_data_out_user[35] ;
+  wire \la_data_out_user[36] ;
+  wire \la_data_out_user[37] ;
+  wire \la_data_out_user[38] ;
+  wire \la_data_out_user[39] ;
+  wire \la_data_out_user[3] ;
+  wire \la_data_out_user[40] ;
+  wire \la_data_out_user[41] ;
+  wire \la_data_out_user[42] ;
+  wire \la_data_out_user[43] ;
+  wire \la_data_out_user[44] ;
+  wire \la_data_out_user[45] ;
+  wire \la_data_out_user[46] ;
+  wire \la_data_out_user[47] ;
+  wire \la_data_out_user[48] ;
+  wire \la_data_out_user[49] ;
+  wire \la_data_out_user[4] ;
+  wire \la_data_out_user[50] ;
+  wire \la_data_out_user[51] ;
+  wire \la_data_out_user[52] ;
+  wire \la_data_out_user[53] ;
+  wire \la_data_out_user[54] ;
+  wire \la_data_out_user[55] ;
+  wire \la_data_out_user[56] ;
+  wire \la_data_out_user[57] ;
+  wire \la_data_out_user[58] ;
+  wire \la_data_out_user[59] ;
+  wire \la_data_out_user[5] ;
+  wire \la_data_out_user[60] ;
+  wire \la_data_out_user[61] ;
+  wire \la_data_out_user[62] ;
+  wire \la_data_out_user[63] ;
+  wire \la_data_out_user[64] ;
+  wire \la_data_out_user[65] ;
+  wire \la_data_out_user[66] ;
+  wire \la_data_out_user[67] ;
+  wire \la_data_out_user[68] ;
+  wire \la_data_out_user[69] ;
+  wire \la_data_out_user[6] ;
+  wire \la_data_out_user[70] ;
+  wire \la_data_out_user[71] ;
+  wire \la_data_out_user[72] ;
+  wire \la_data_out_user[73] ;
+  wire \la_data_out_user[74] ;
+  wire \la_data_out_user[75] ;
+  wire \la_data_out_user[76] ;
+  wire \la_data_out_user[77] ;
+  wire \la_data_out_user[78] ;
+  wire \la_data_out_user[79] ;
+  wire \la_data_out_user[7] ;
+  wire \la_data_out_user[80] ;
+  wire \la_data_out_user[81] ;
+  wire \la_data_out_user[82] ;
+  wire \la_data_out_user[83] ;
+  wire \la_data_out_user[84] ;
+  wire \la_data_out_user[85] ;
+  wire \la_data_out_user[86] ;
+  wire \la_data_out_user[87] ;
+  wire \la_data_out_user[88] ;
+  wire \la_data_out_user[89] ;
+  wire \la_data_out_user[8] ;
+  wire \la_data_out_user[90] ;
+  wire \la_data_out_user[91] ;
+  wire \la_data_out_user[92] ;
+  wire \la_data_out_user[93] ;
+  wire \la_data_out_user[94] ;
+  wire \la_data_out_user[95] ;
+  wire \la_data_out_user[96] ;
+  wire \la_data_out_user[97] ;
+  wire \la_data_out_user[98] ;
+  wire \la_data_out_user[99] ;
+  wire \la_data_out_user[9] ;
+  wire \la_iena_mprj[0] ;
+  wire \la_iena_mprj[100] ;
+  wire \la_iena_mprj[101] ;
+  wire \la_iena_mprj[102] ;
+  wire \la_iena_mprj[103] ;
+  wire \la_iena_mprj[104] ;
+  wire \la_iena_mprj[105] ;
+  wire \la_iena_mprj[106] ;
+  wire \la_iena_mprj[107] ;
+  wire \la_iena_mprj[108] ;
+  wire \la_iena_mprj[109] ;
+  wire \la_iena_mprj[10] ;
+  wire \la_iena_mprj[110] ;
+  wire \la_iena_mprj[111] ;
+  wire \la_iena_mprj[112] ;
+  wire \la_iena_mprj[113] ;
+  wire \la_iena_mprj[114] ;
+  wire \la_iena_mprj[115] ;
+  wire \la_iena_mprj[116] ;
+  wire \la_iena_mprj[117] ;
+  wire \la_iena_mprj[118] ;
+  wire \la_iena_mprj[119] ;
+  wire \la_iena_mprj[11] ;
+  wire \la_iena_mprj[120] ;
+  wire \la_iena_mprj[121] ;
+  wire \la_iena_mprj[122] ;
+  wire \la_iena_mprj[123] ;
+  wire \la_iena_mprj[124] ;
+  wire \la_iena_mprj[125] ;
+  wire \la_iena_mprj[126] ;
+  wire \la_iena_mprj[127] ;
+  wire \la_iena_mprj[12] ;
+  wire \la_iena_mprj[13] ;
+  wire \la_iena_mprj[14] ;
+  wire \la_iena_mprj[15] ;
+  wire \la_iena_mprj[16] ;
+  wire \la_iena_mprj[17] ;
+  wire \la_iena_mprj[18] ;
+  wire \la_iena_mprj[19] ;
+  wire \la_iena_mprj[1] ;
+  wire \la_iena_mprj[20] ;
+  wire \la_iena_mprj[21] ;
+  wire \la_iena_mprj[22] ;
+  wire \la_iena_mprj[23] ;
+  wire \la_iena_mprj[24] ;
+  wire \la_iena_mprj[25] ;
+  wire \la_iena_mprj[26] ;
+  wire \la_iena_mprj[27] ;
+  wire \la_iena_mprj[28] ;
+  wire \la_iena_mprj[29] ;
+  wire \la_iena_mprj[2] ;
+  wire \la_iena_mprj[30] ;
+  wire \la_iena_mprj[31] ;
+  wire \la_iena_mprj[32] ;
+  wire \la_iena_mprj[33] ;
+  wire \la_iena_mprj[34] ;
+  wire \la_iena_mprj[35] ;
+  wire \la_iena_mprj[36] ;
+  wire \la_iena_mprj[37] ;
+  wire \la_iena_mprj[38] ;
+  wire \la_iena_mprj[39] ;
+  wire \la_iena_mprj[3] ;
+  wire \la_iena_mprj[40] ;
+  wire \la_iena_mprj[41] ;
+  wire \la_iena_mprj[42] ;
+  wire \la_iena_mprj[43] ;
+  wire \la_iena_mprj[44] ;
+  wire \la_iena_mprj[45] ;
+  wire \la_iena_mprj[46] ;
+  wire \la_iena_mprj[47] ;
+  wire \la_iena_mprj[48] ;
+  wire \la_iena_mprj[49] ;
+  wire \la_iena_mprj[4] ;
+  wire \la_iena_mprj[50] ;
+  wire \la_iena_mprj[51] ;
+  wire \la_iena_mprj[52] ;
+  wire \la_iena_mprj[53] ;
+  wire \la_iena_mprj[54] ;
+  wire \la_iena_mprj[55] ;
+  wire \la_iena_mprj[56] ;
+  wire \la_iena_mprj[57] ;
+  wire \la_iena_mprj[58] ;
+  wire \la_iena_mprj[59] ;
+  wire \la_iena_mprj[5] ;
+  wire \la_iena_mprj[60] ;
+  wire \la_iena_mprj[61] ;
+  wire \la_iena_mprj[62] ;
+  wire \la_iena_mprj[63] ;
+  wire \la_iena_mprj[64] ;
+  wire \la_iena_mprj[65] ;
+  wire \la_iena_mprj[66] ;
+  wire \la_iena_mprj[67] ;
+  wire \la_iena_mprj[68] ;
+  wire \la_iena_mprj[69] ;
+  wire \la_iena_mprj[6] ;
+  wire \la_iena_mprj[70] ;
+  wire \la_iena_mprj[71] ;
+  wire \la_iena_mprj[72] ;
+  wire \la_iena_mprj[73] ;
+  wire \la_iena_mprj[74] ;
+  wire \la_iena_mprj[75] ;
+  wire \la_iena_mprj[76] ;
+  wire \la_iena_mprj[77] ;
+  wire \la_iena_mprj[78] ;
+  wire \la_iena_mprj[79] ;
+  wire \la_iena_mprj[7] ;
+  wire \la_iena_mprj[80] ;
+  wire \la_iena_mprj[81] ;
+  wire \la_iena_mprj[82] ;
+  wire \la_iena_mprj[83] ;
+  wire \la_iena_mprj[84] ;
+  wire \la_iena_mprj[85] ;
+  wire \la_iena_mprj[86] ;
+  wire \la_iena_mprj[87] ;
+  wire \la_iena_mprj[88] ;
+  wire \la_iena_mprj[89] ;
+  wire \la_iena_mprj[8] ;
+  wire \la_iena_mprj[90] ;
+  wire \la_iena_mprj[91] ;
+  wire \la_iena_mprj[92] ;
+  wire \la_iena_mprj[93] ;
+  wire \la_iena_mprj[94] ;
+  wire \la_iena_mprj[95] ;
+  wire \la_iena_mprj[96] ;
+  wire \la_iena_mprj[97] ;
+  wire \la_iena_mprj[98] ;
+  wire \la_iena_mprj[99] ;
+  wire \la_iena_mprj[9] ;
+  wire \la_oenb_mprj[0] ;
+  wire \la_oenb_mprj[100] ;
+  wire \la_oenb_mprj[101] ;
+  wire \la_oenb_mprj[102] ;
+  wire \la_oenb_mprj[103] ;
+  wire \la_oenb_mprj[104] ;
+  wire \la_oenb_mprj[105] ;
+  wire \la_oenb_mprj[106] ;
+  wire \la_oenb_mprj[107] ;
+  wire \la_oenb_mprj[108] ;
+  wire \la_oenb_mprj[109] ;
+  wire \la_oenb_mprj[10] ;
+  wire \la_oenb_mprj[110] ;
+  wire \la_oenb_mprj[111] ;
+  wire \la_oenb_mprj[112] ;
+  wire \la_oenb_mprj[113] ;
+  wire \la_oenb_mprj[114] ;
+  wire \la_oenb_mprj[115] ;
+  wire \la_oenb_mprj[116] ;
+  wire \la_oenb_mprj[117] ;
+  wire \la_oenb_mprj[118] ;
+  wire \la_oenb_mprj[119] ;
+  wire \la_oenb_mprj[11] ;
+  wire \la_oenb_mprj[120] ;
+  wire \la_oenb_mprj[121] ;
+  wire \la_oenb_mprj[122] ;
+  wire \la_oenb_mprj[123] ;
+  wire \la_oenb_mprj[124] ;
+  wire \la_oenb_mprj[125] ;
+  wire \la_oenb_mprj[126] ;
+  wire \la_oenb_mprj[127] ;
+  wire \la_oenb_mprj[12] ;
+  wire \la_oenb_mprj[13] ;
+  wire \la_oenb_mprj[14] ;
+  wire \la_oenb_mprj[15] ;
+  wire \la_oenb_mprj[16] ;
+  wire \la_oenb_mprj[17] ;
+  wire \la_oenb_mprj[18] ;
+  wire \la_oenb_mprj[19] ;
+  wire \la_oenb_mprj[1] ;
+  wire \la_oenb_mprj[20] ;
+  wire \la_oenb_mprj[21] ;
+  wire \la_oenb_mprj[22] ;
+  wire \la_oenb_mprj[23] ;
+  wire \la_oenb_mprj[24] ;
+  wire \la_oenb_mprj[25] ;
+  wire \la_oenb_mprj[26] ;
+  wire \la_oenb_mprj[27] ;
+  wire \la_oenb_mprj[28] ;
+  wire \la_oenb_mprj[29] ;
+  wire \la_oenb_mprj[2] ;
+  wire \la_oenb_mprj[30] ;
+  wire \la_oenb_mprj[31] ;
+  wire \la_oenb_mprj[32] ;
+  wire \la_oenb_mprj[33] ;
+  wire \la_oenb_mprj[34] ;
+  wire \la_oenb_mprj[35] ;
+  wire \la_oenb_mprj[36] ;
+  wire \la_oenb_mprj[37] ;
+  wire \la_oenb_mprj[38] ;
+  wire \la_oenb_mprj[39] ;
+  wire \la_oenb_mprj[3] ;
+  wire \la_oenb_mprj[40] ;
+  wire \la_oenb_mprj[41] ;
+  wire \la_oenb_mprj[42] ;
+  wire \la_oenb_mprj[43] ;
+  wire \la_oenb_mprj[44] ;
+  wire \la_oenb_mprj[45] ;
+  wire \la_oenb_mprj[46] ;
+  wire \la_oenb_mprj[47] ;
+  wire \la_oenb_mprj[48] ;
+  wire \la_oenb_mprj[49] ;
+  wire \la_oenb_mprj[4] ;
+  wire \la_oenb_mprj[50] ;
+  wire \la_oenb_mprj[51] ;
+  wire \la_oenb_mprj[52] ;
+  wire \la_oenb_mprj[53] ;
+  wire \la_oenb_mprj[54] ;
+  wire \la_oenb_mprj[55] ;
+  wire \la_oenb_mprj[56] ;
+  wire \la_oenb_mprj[57] ;
+  wire \la_oenb_mprj[58] ;
+  wire \la_oenb_mprj[59] ;
+  wire \la_oenb_mprj[5] ;
+  wire \la_oenb_mprj[60] ;
+  wire \la_oenb_mprj[61] ;
+  wire \la_oenb_mprj[62] ;
+  wire \la_oenb_mprj[63] ;
+  wire \la_oenb_mprj[64] ;
+  wire \la_oenb_mprj[65] ;
+  wire \la_oenb_mprj[66] ;
+  wire \la_oenb_mprj[67] ;
+  wire \la_oenb_mprj[68] ;
+  wire \la_oenb_mprj[69] ;
+  wire \la_oenb_mprj[6] ;
+  wire \la_oenb_mprj[70] ;
+  wire \la_oenb_mprj[71] ;
+  wire \la_oenb_mprj[72] ;
+  wire \la_oenb_mprj[73] ;
+  wire \la_oenb_mprj[74] ;
+  wire \la_oenb_mprj[75] ;
+  wire \la_oenb_mprj[76] ;
+  wire \la_oenb_mprj[77] ;
+  wire \la_oenb_mprj[78] ;
+  wire \la_oenb_mprj[79] ;
+  wire \la_oenb_mprj[7] ;
+  wire \la_oenb_mprj[80] ;
+  wire \la_oenb_mprj[81] ;
+  wire \la_oenb_mprj[82] ;
+  wire \la_oenb_mprj[83] ;
+  wire \la_oenb_mprj[84] ;
+  wire \la_oenb_mprj[85] ;
+  wire \la_oenb_mprj[86] ;
+  wire \la_oenb_mprj[87] ;
+  wire \la_oenb_mprj[88] ;
+  wire \la_oenb_mprj[89] ;
+  wire \la_oenb_mprj[8] ;
+  wire \la_oenb_mprj[90] ;
+  wire \la_oenb_mprj[91] ;
+  wire \la_oenb_mprj[92] ;
+  wire \la_oenb_mprj[93] ;
+  wire \la_oenb_mprj[94] ;
+  wire \la_oenb_mprj[95] ;
+  wire \la_oenb_mprj[96] ;
+  wire \la_oenb_mprj[97] ;
+  wire \la_oenb_mprj[98] ;
+  wire \la_oenb_mprj[99] ;
+  wire \la_oenb_mprj[9] ;
+  wire \la_oenb_user[0] ;
+  wire \la_oenb_user[100] ;
+  wire \la_oenb_user[101] ;
+  wire \la_oenb_user[102] ;
+  wire \la_oenb_user[103] ;
+  wire \la_oenb_user[104] ;
+  wire \la_oenb_user[105] ;
+  wire \la_oenb_user[106] ;
+  wire \la_oenb_user[107] ;
+  wire \la_oenb_user[108] ;
+  wire \la_oenb_user[109] ;
+  wire \la_oenb_user[10] ;
+  wire \la_oenb_user[110] ;
+  wire \la_oenb_user[111] ;
+  wire \la_oenb_user[112] ;
+  wire \la_oenb_user[113] ;
+  wire \la_oenb_user[114] ;
+  wire \la_oenb_user[115] ;
+  wire \la_oenb_user[116] ;
+  wire \la_oenb_user[117] ;
+  wire \la_oenb_user[118] ;
+  wire \la_oenb_user[119] ;
+  wire \la_oenb_user[11] ;
+  wire \la_oenb_user[120] ;
+  wire \la_oenb_user[121] ;
+  wire \la_oenb_user[122] ;
+  wire \la_oenb_user[123] ;
+  wire \la_oenb_user[124] ;
+  wire \la_oenb_user[125] ;
+  wire \la_oenb_user[126] ;
+  wire \la_oenb_user[127] ;
+  wire \la_oenb_user[12] ;
+  wire \la_oenb_user[13] ;
+  wire \la_oenb_user[14] ;
+  wire \la_oenb_user[15] ;
+  wire \la_oenb_user[16] ;
+  wire \la_oenb_user[17] ;
+  wire \la_oenb_user[18] ;
+  wire \la_oenb_user[19] ;
+  wire \la_oenb_user[1] ;
+  wire \la_oenb_user[20] ;
+  wire \la_oenb_user[21] ;
+  wire \la_oenb_user[22] ;
+  wire \la_oenb_user[23] ;
+  wire \la_oenb_user[24] ;
+  wire \la_oenb_user[25] ;
+  wire \la_oenb_user[26] ;
+  wire \la_oenb_user[27] ;
+  wire \la_oenb_user[28] ;
+  wire \la_oenb_user[29] ;
+  wire \la_oenb_user[2] ;
+  wire \la_oenb_user[30] ;
+  wire \la_oenb_user[31] ;
+  wire \la_oenb_user[32] ;
+  wire \la_oenb_user[33] ;
+  wire \la_oenb_user[34] ;
+  wire \la_oenb_user[35] ;
+  wire \la_oenb_user[36] ;
+  wire \la_oenb_user[37] ;
+  wire \la_oenb_user[38] ;
+  wire \la_oenb_user[39] ;
+  wire \la_oenb_user[3] ;
+  wire \la_oenb_user[40] ;
+  wire \la_oenb_user[41] ;
+  wire \la_oenb_user[42] ;
+  wire \la_oenb_user[43] ;
+  wire \la_oenb_user[44] ;
+  wire \la_oenb_user[45] ;
+  wire \la_oenb_user[46] ;
+  wire \la_oenb_user[47] ;
+  wire \la_oenb_user[48] ;
+  wire \la_oenb_user[49] ;
+  wire \la_oenb_user[4] ;
+  wire \la_oenb_user[50] ;
+  wire \la_oenb_user[51] ;
+  wire \la_oenb_user[52] ;
+  wire \la_oenb_user[53] ;
+  wire \la_oenb_user[54] ;
+  wire \la_oenb_user[55] ;
+  wire \la_oenb_user[56] ;
+  wire \la_oenb_user[57] ;
+  wire \la_oenb_user[58] ;
+  wire \la_oenb_user[59] ;
+  wire \la_oenb_user[5] ;
+  wire \la_oenb_user[60] ;
+  wire \la_oenb_user[61] ;
+  wire \la_oenb_user[62] ;
+  wire \la_oenb_user[63] ;
+  wire \la_oenb_user[64] ;
+  wire \la_oenb_user[65] ;
+  wire \la_oenb_user[66] ;
+  wire \la_oenb_user[67] ;
+  wire \la_oenb_user[68] ;
+  wire \la_oenb_user[69] ;
+  wire \la_oenb_user[6] ;
+  wire \la_oenb_user[70] ;
+  wire \la_oenb_user[71] ;
+  wire \la_oenb_user[72] ;
+  wire \la_oenb_user[73] ;
+  wire \la_oenb_user[74] ;
+  wire \la_oenb_user[75] ;
+  wire \la_oenb_user[76] ;
+  wire \la_oenb_user[77] ;
+  wire \la_oenb_user[78] ;
+  wire \la_oenb_user[79] ;
+  wire \la_oenb_user[7] ;
+  wire \la_oenb_user[80] ;
+  wire \la_oenb_user[81] ;
+  wire \la_oenb_user[82] ;
+  wire \la_oenb_user[83] ;
+  wire \la_oenb_user[84] ;
+  wire \la_oenb_user[85] ;
+  wire \la_oenb_user[86] ;
+  wire \la_oenb_user[87] ;
+  wire \la_oenb_user[88] ;
+  wire \la_oenb_user[89] ;
+  wire \la_oenb_user[8] ;
+  wire \la_oenb_user[90] ;
+  wire \la_oenb_user[91] ;
+  wire \la_oenb_user[92] ;
+  wire \la_oenb_user[93] ;
+  wire \la_oenb_user[94] ;
+  wire \la_oenb_user[95] ;
+  wire \la_oenb_user[96] ;
+  wire \la_oenb_user[97] ;
+  wire \la_oenb_user[98] ;
+  wire \la_oenb_user[99] ;
+  wire \la_oenb_user[9] ;
+  wire \mask_rev[0] ;
+  wire \mask_rev[10] ;
+  wire \mask_rev[11] ;
+  wire \mask_rev[12] ;
+  wire \mask_rev[13] ;
+  wire \mask_rev[14] ;
+  wire \mask_rev[15] ;
+  wire \mask_rev[16] ;
+  wire \mask_rev[17] ;
+  wire \mask_rev[18] ;
+  wire \mask_rev[19] ;
+  wire \mask_rev[1] ;
+  wire \mask_rev[20] ;
+  wire \mask_rev[21] ;
+  wire \mask_rev[22] ;
+  wire \mask_rev[23] ;
+  wire \mask_rev[24] ;
+  wire \mask_rev[25] ;
+  wire \mask_rev[26] ;
+  wire \mask_rev[27] ;
+  wire \mask_rev[28] ;
+  wire \mask_rev[29] ;
+  wire \mask_rev[2] ;
+  wire \mask_rev[30] ;
+  wire \mask_rev[31] ;
+  wire \mask_rev[3] ;
+  wire \mask_rev[4] ;
+  wire \mask_rev[5] ;
+  wire \mask_rev[6] ;
+  wire \mask_rev[7] ;
+  wire \mask_rev[8] ;
+  wire \mask_rev[9] ;
+  wire \mgmt_io_in[0] ;
+  wire \mgmt_io_in[10] ;
+  wire \mgmt_io_in[11] ;
+  wire \mgmt_io_in[12] ;
+  wire \mgmt_io_in[13] ;
+  wire \mgmt_io_in[14] ;
+  wire \mgmt_io_in[15] ;
+  wire \mgmt_io_in[16] ;
+  wire \mgmt_io_in[17] ;
+  wire \mgmt_io_in[18] ;
+  wire \mgmt_io_in[19] ;
+  wire \mgmt_io_in[1] ;
+  wire \mgmt_io_in[20] ;
+  wire \mgmt_io_in[21] ;
+  wire \mgmt_io_in[22] ;
+  wire \mgmt_io_in[23] ;
+  wire \mgmt_io_in[24] ;
+  wire \mgmt_io_in[25] ;
+  wire \mgmt_io_in[26] ;
+  wire \mgmt_io_in[27] ;
+  wire \mgmt_io_in[28] ;
+  wire \mgmt_io_in[29] ;
+  wire \mgmt_io_in[2] ;
+  wire \mgmt_io_in[30] ;
+  wire \mgmt_io_in[31] ;
+  wire \mgmt_io_in[32] ;
+  wire \mgmt_io_in[33] ;
+  wire \mgmt_io_in[34] ;
+  wire \mgmt_io_in[35] ;
+  wire \mgmt_io_in[36] ;
+  wire \mgmt_io_in[37] ;
+  wire \mgmt_io_in[3] ;
+  wire \mgmt_io_in[4] ;
+  wire \mgmt_io_in[5] ;
+  wire \mgmt_io_in[6] ;
+  wire \mgmt_io_in[7] ;
+  wire \mgmt_io_in[8] ;
+  wire \mgmt_io_in[9] ;
+  wire \mgmt_io_nc[0] ;
+  wire \mgmt_io_nc[10] ;
+  wire \mgmt_io_nc[11] ;
+  wire \mgmt_io_nc[12] ;
+  wire \mgmt_io_nc[13] ;
+  wire \mgmt_io_nc[14] ;
+  wire \mgmt_io_nc[15] ;
+  wire \mgmt_io_nc[16] ;
+  wire \mgmt_io_nc[17] ;
+  wire \mgmt_io_nc[18] ;
+  wire \mgmt_io_nc[19] ;
+  wire \mgmt_io_nc[1] ;
+  wire \mgmt_io_nc[20] ;
+  wire \mgmt_io_nc[21] ;
+  wire \mgmt_io_nc[22] ;
+  wire \mgmt_io_nc[23] ;
+  wire \mgmt_io_nc[24] ;
+  wire \mgmt_io_nc[25] ;
+  wire \mgmt_io_nc[26] ;
+  wire \mgmt_io_nc[27] ;
+  wire \mgmt_io_nc[28] ;
+  wire \mgmt_io_nc[29] ;
+  wire \mgmt_io_nc[2] ;
+  wire \mgmt_io_nc[30] ;
+  wire \mgmt_io_nc[31] ;
+  wire \mgmt_io_nc[32] ;
+  wire \mgmt_io_nc[33] ;
+  wire \mgmt_io_nc[3] ;
+  wire \mgmt_io_nc[4] ;
+  wire \mgmt_io_nc[5] ;
+  wire \mgmt_io_nc[6] ;
+  wire \mgmt_io_nc[7] ;
+  wire \mgmt_io_nc[8] ;
+  wire \mgmt_io_nc[9] ;
+  wire \mgmt_io_oeb[0] ;
+  wire \mgmt_io_oeb[1] ;
+  wire \mgmt_io_oeb[2] ;
+  wire \mgmt_io_oeb[3] ;
+  wire \mgmt_io_oeb[4] ;
+  wire \mgmt_io_out[0] ;
+  wire \mgmt_io_out[1] ;
+  wire \mgmt_io_out[2] ;
+  wire \mgmt_io_out[3] ;
+  wire \mgmt_io_out[4] ;
+  wire mprj2_vcc_pwrgood;
+  wire mprj2_vdd_pwrgood;
+  wire mprj_ack_i_core;
+  wire mprj_ack_i_user;
+  wire \mprj_adr_o_core[0] ;
+  wire \mprj_adr_o_core[10] ;
+  wire \mprj_adr_o_core[11] ;
+  wire \mprj_adr_o_core[12] ;
+  wire \mprj_adr_o_core[13] ;
+  wire \mprj_adr_o_core[14] ;
+  wire \mprj_adr_o_core[15] ;
+  wire \mprj_adr_o_core[16] ;
+  wire \mprj_adr_o_core[17] ;
+  wire \mprj_adr_o_core[18] ;
+  wire \mprj_adr_o_core[19] ;
+  wire \mprj_adr_o_core[1] ;
+  wire \mprj_adr_o_core[20] ;
+  wire \mprj_adr_o_core[21] ;
+  wire \mprj_adr_o_core[22] ;
+  wire \mprj_adr_o_core[23] ;
+  wire \mprj_adr_o_core[24] ;
+  wire \mprj_adr_o_core[25] ;
+  wire \mprj_adr_o_core[26] ;
+  wire \mprj_adr_o_core[27] ;
+  wire \mprj_adr_o_core[28] ;
+  wire \mprj_adr_o_core[29] ;
+  wire \mprj_adr_o_core[2] ;
+  wire \mprj_adr_o_core[30] ;
+  wire \mprj_adr_o_core[31] ;
+  wire \mprj_adr_o_core[3] ;
+  wire \mprj_adr_o_core[4] ;
+  wire \mprj_adr_o_core[5] ;
+  wire \mprj_adr_o_core[6] ;
+  wire \mprj_adr_o_core[7] ;
+  wire \mprj_adr_o_core[8] ;
+  wire \mprj_adr_o_core[9] ;
+  wire \mprj_adr_o_user[0] ;
+  wire \mprj_adr_o_user[10] ;
+  wire \mprj_adr_o_user[11] ;
+  wire \mprj_adr_o_user[12] ;
+  wire \mprj_adr_o_user[13] ;
+  wire \mprj_adr_o_user[14] ;
+  wire \mprj_adr_o_user[15] ;
+  wire \mprj_adr_o_user[16] ;
+  wire \mprj_adr_o_user[17] ;
+  wire \mprj_adr_o_user[18] ;
+  wire \mprj_adr_o_user[19] ;
+  wire \mprj_adr_o_user[1] ;
+  wire \mprj_adr_o_user[20] ;
+  wire \mprj_adr_o_user[21] ;
+  wire \mprj_adr_o_user[22] ;
+  wire \mprj_adr_o_user[23] ;
+  wire \mprj_adr_o_user[24] ;
+  wire \mprj_adr_o_user[25] ;
+  wire \mprj_adr_o_user[26] ;
+  wire \mprj_adr_o_user[27] ;
+  wire \mprj_adr_o_user[28] ;
+  wire \mprj_adr_o_user[29] ;
+  wire \mprj_adr_o_user[2] ;
+  wire \mprj_adr_o_user[30] ;
+  wire \mprj_adr_o_user[31] ;
+  wire \mprj_adr_o_user[3] ;
+  wire \mprj_adr_o_user[4] ;
+  wire \mprj_adr_o_user[5] ;
+  wire \mprj_adr_o_user[6] ;
+  wire \mprj_adr_o_user[7] ;
+  wire \mprj_adr_o_user[8] ;
+  wire \mprj_adr_o_user[9] ;
+  wire mprj_clock;
+  wire mprj_clock2;
+  wire mprj_cyc_o_core;
+  wire mprj_cyc_o_user;
+  wire \mprj_dat_i_core[0] ;
+  wire \mprj_dat_i_core[10] ;
+  wire \mprj_dat_i_core[11] ;
+  wire \mprj_dat_i_core[12] ;
+  wire \mprj_dat_i_core[13] ;
+  wire \mprj_dat_i_core[14] ;
+  wire \mprj_dat_i_core[15] ;
+  wire \mprj_dat_i_core[16] ;
+  wire \mprj_dat_i_core[17] ;
+  wire \mprj_dat_i_core[18] ;
+  wire \mprj_dat_i_core[19] ;
+  wire \mprj_dat_i_core[1] ;
+  wire \mprj_dat_i_core[20] ;
+  wire \mprj_dat_i_core[21] ;
+  wire \mprj_dat_i_core[22] ;
+  wire \mprj_dat_i_core[23] ;
+  wire \mprj_dat_i_core[24] ;
+  wire \mprj_dat_i_core[25] ;
+  wire \mprj_dat_i_core[26] ;
+  wire \mprj_dat_i_core[27] ;
+  wire \mprj_dat_i_core[28] ;
+  wire \mprj_dat_i_core[29] ;
+  wire \mprj_dat_i_core[2] ;
+  wire \mprj_dat_i_core[30] ;
+  wire \mprj_dat_i_core[31] ;
+  wire \mprj_dat_i_core[3] ;
+  wire \mprj_dat_i_core[4] ;
+  wire \mprj_dat_i_core[5] ;
+  wire \mprj_dat_i_core[6] ;
+  wire \mprj_dat_i_core[7] ;
+  wire \mprj_dat_i_core[8] ;
+  wire \mprj_dat_i_core[9] ;
+  wire \mprj_dat_i_user[0] ;
+  wire \mprj_dat_i_user[10] ;
+  wire \mprj_dat_i_user[11] ;
+  wire \mprj_dat_i_user[12] ;
+  wire \mprj_dat_i_user[13] ;
+  wire \mprj_dat_i_user[14] ;
+  wire \mprj_dat_i_user[15] ;
+  wire \mprj_dat_i_user[16] ;
+  wire \mprj_dat_i_user[17] ;
+  wire \mprj_dat_i_user[18] ;
+  wire \mprj_dat_i_user[19] ;
+  wire \mprj_dat_i_user[1] ;
+  wire \mprj_dat_i_user[20] ;
+  wire \mprj_dat_i_user[21] ;
+  wire \mprj_dat_i_user[22] ;
+  wire \mprj_dat_i_user[23] ;
+  wire \mprj_dat_i_user[24] ;
+  wire \mprj_dat_i_user[25] ;
+  wire \mprj_dat_i_user[26] ;
+  wire \mprj_dat_i_user[27] ;
+  wire \mprj_dat_i_user[28] ;
+  wire \mprj_dat_i_user[29] ;
+  wire \mprj_dat_i_user[2] ;
+  wire \mprj_dat_i_user[30] ;
+  wire \mprj_dat_i_user[31] ;
+  wire \mprj_dat_i_user[3] ;
+  wire \mprj_dat_i_user[4] ;
+  wire \mprj_dat_i_user[5] ;
+  wire \mprj_dat_i_user[6] ;
+  wire \mprj_dat_i_user[7] ;
+  wire \mprj_dat_i_user[8] ;
+  wire \mprj_dat_i_user[9] ;
+  wire \mprj_dat_o_core[0] ;
+  wire \mprj_dat_o_core[10] ;
+  wire \mprj_dat_o_core[11] ;
+  wire \mprj_dat_o_core[12] ;
+  wire \mprj_dat_o_core[13] ;
+  wire \mprj_dat_o_core[14] ;
+  wire \mprj_dat_o_core[15] ;
+  wire \mprj_dat_o_core[16] ;
+  wire \mprj_dat_o_core[17] ;
+  wire \mprj_dat_o_core[18] ;
+  wire \mprj_dat_o_core[19] ;
+  wire \mprj_dat_o_core[1] ;
+  wire \mprj_dat_o_core[20] ;
+  wire \mprj_dat_o_core[21] ;
+  wire \mprj_dat_o_core[22] ;
+  wire \mprj_dat_o_core[23] ;
+  wire \mprj_dat_o_core[24] ;
+  wire \mprj_dat_o_core[25] ;
+  wire \mprj_dat_o_core[26] ;
+  wire \mprj_dat_o_core[27] ;
+  wire \mprj_dat_o_core[28] ;
+  wire \mprj_dat_o_core[29] ;
+  wire \mprj_dat_o_core[2] ;
+  wire \mprj_dat_o_core[30] ;
+  wire \mprj_dat_o_core[31] ;
+  wire \mprj_dat_o_core[3] ;
+  wire \mprj_dat_o_core[4] ;
+  wire \mprj_dat_o_core[5] ;
+  wire \mprj_dat_o_core[6] ;
+  wire \mprj_dat_o_core[7] ;
+  wire \mprj_dat_o_core[8] ;
+  wire \mprj_dat_o_core[9] ;
+  wire \mprj_dat_o_user[0] ;
+  wire \mprj_dat_o_user[10] ;
+  wire \mprj_dat_o_user[11] ;
+  wire \mprj_dat_o_user[12] ;
+  wire \mprj_dat_o_user[13] ;
+  wire \mprj_dat_o_user[14] ;
+  wire \mprj_dat_o_user[15] ;
+  wire \mprj_dat_o_user[16] ;
+  wire \mprj_dat_o_user[17] ;
+  wire \mprj_dat_o_user[18] ;
+  wire \mprj_dat_o_user[19] ;
+  wire \mprj_dat_o_user[1] ;
+  wire \mprj_dat_o_user[20] ;
+  wire \mprj_dat_o_user[21] ;
+  wire \mprj_dat_o_user[22] ;
+  wire \mprj_dat_o_user[23] ;
+  wire \mprj_dat_o_user[24] ;
+  wire \mprj_dat_o_user[25] ;
+  wire \mprj_dat_o_user[26] ;
+  wire \mprj_dat_o_user[27] ;
+  wire \mprj_dat_o_user[28] ;
+  wire \mprj_dat_o_user[29] ;
+  wire \mprj_dat_o_user[2] ;
+  wire \mprj_dat_o_user[30] ;
+  wire \mprj_dat_o_user[31] ;
+  wire \mprj_dat_o_user[3] ;
+  wire \mprj_dat_o_user[4] ;
+  wire \mprj_dat_o_user[5] ;
+  wire \mprj_dat_o_user[6] ;
+  wire \mprj_dat_o_user[7] ;
+  wire \mprj_dat_o_user[8] ;
+  wire \mprj_dat_o_user[9] ;
+  wire mprj_iena_wb;
+  inout [37:0] mprj_io;
+  wire \mprj_io_analog_en[0] ;
+  wire \mprj_io_analog_en[10] ;
+  wire \mprj_io_analog_en[11] ;
+  wire \mprj_io_analog_en[12] ;
+  wire \mprj_io_analog_en[13] ;
+  wire \mprj_io_analog_en[14] ;
+  wire \mprj_io_analog_en[15] ;
+  wire \mprj_io_analog_en[16] ;
+  wire \mprj_io_analog_en[17] ;
+  wire \mprj_io_analog_en[18] ;
+  wire \mprj_io_analog_en[19] ;
+  wire \mprj_io_analog_en[1] ;
+  wire \mprj_io_analog_en[20] ;
+  wire \mprj_io_analog_en[21] ;
+  wire \mprj_io_analog_en[22] ;
+  wire \mprj_io_analog_en[23] ;
+  wire \mprj_io_analog_en[24] ;
+  wire \mprj_io_analog_en[25] ;
+  wire \mprj_io_analog_en[26] ;
+  wire \mprj_io_analog_en[27] ;
+  wire \mprj_io_analog_en[28] ;
+  wire \mprj_io_analog_en[29] ;
+  wire \mprj_io_analog_en[2] ;
+  wire \mprj_io_analog_en[30] ;
+  wire \mprj_io_analog_en[31] ;
+  wire \mprj_io_analog_en[32] ;
+  wire \mprj_io_analog_en[33] ;
+  wire \mprj_io_analog_en[34] ;
+  wire \mprj_io_analog_en[35] ;
+  wire \mprj_io_analog_en[36] ;
+  wire \mprj_io_analog_en[37] ;
+  wire \mprj_io_analog_en[3] ;
+  wire \mprj_io_analog_en[4] ;
+  wire \mprj_io_analog_en[5] ;
+  wire \mprj_io_analog_en[6] ;
+  wire \mprj_io_analog_en[7] ;
+  wire \mprj_io_analog_en[8] ;
+  wire \mprj_io_analog_en[9] ;
+  wire \mprj_io_analog_pol[0] ;
+  wire \mprj_io_analog_pol[10] ;
+  wire \mprj_io_analog_pol[11] ;
+  wire \mprj_io_analog_pol[12] ;
+  wire \mprj_io_analog_pol[13] ;
+  wire \mprj_io_analog_pol[14] ;
+  wire \mprj_io_analog_pol[15] ;
+  wire \mprj_io_analog_pol[16] ;
+  wire \mprj_io_analog_pol[17] ;
+  wire \mprj_io_analog_pol[18] ;
+  wire \mprj_io_analog_pol[19] ;
+  wire \mprj_io_analog_pol[1] ;
+  wire \mprj_io_analog_pol[20] ;
+  wire \mprj_io_analog_pol[21] ;
+  wire \mprj_io_analog_pol[22] ;
+  wire \mprj_io_analog_pol[23] ;
+  wire \mprj_io_analog_pol[24] ;
+  wire \mprj_io_analog_pol[25] ;
+  wire \mprj_io_analog_pol[26] ;
+  wire \mprj_io_analog_pol[27] ;
+  wire \mprj_io_analog_pol[28] ;
+  wire \mprj_io_analog_pol[29] ;
+  wire \mprj_io_analog_pol[2] ;
+  wire \mprj_io_analog_pol[30] ;
+  wire \mprj_io_analog_pol[31] ;
+  wire \mprj_io_analog_pol[32] ;
+  wire \mprj_io_analog_pol[33] ;
+  wire \mprj_io_analog_pol[34] ;
+  wire \mprj_io_analog_pol[35] ;
+  wire \mprj_io_analog_pol[36] ;
+  wire \mprj_io_analog_pol[37] ;
+  wire \mprj_io_analog_pol[3] ;
+  wire \mprj_io_analog_pol[4] ;
+  wire \mprj_io_analog_pol[5] ;
+  wire \mprj_io_analog_pol[6] ;
+  wire \mprj_io_analog_pol[7] ;
+  wire \mprj_io_analog_pol[8] ;
+  wire \mprj_io_analog_pol[9] ;
+  wire \mprj_io_analog_sel[0] ;
+  wire \mprj_io_analog_sel[10] ;
+  wire \mprj_io_analog_sel[11] ;
+  wire \mprj_io_analog_sel[12] ;
+  wire \mprj_io_analog_sel[13] ;
+  wire \mprj_io_analog_sel[14] ;
+  wire \mprj_io_analog_sel[15] ;
+  wire \mprj_io_analog_sel[16] ;
+  wire \mprj_io_analog_sel[17] ;
+  wire \mprj_io_analog_sel[18] ;
+  wire \mprj_io_analog_sel[19] ;
+  wire \mprj_io_analog_sel[1] ;
+  wire \mprj_io_analog_sel[20] ;
+  wire \mprj_io_analog_sel[21] ;
+  wire \mprj_io_analog_sel[22] ;
+  wire \mprj_io_analog_sel[23] ;
+  wire \mprj_io_analog_sel[24] ;
+  wire \mprj_io_analog_sel[25] ;
+  wire \mprj_io_analog_sel[26] ;
+  wire \mprj_io_analog_sel[27] ;
+  wire \mprj_io_analog_sel[28] ;
+  wire \mprj_io_analog_sel[29] ;
+  wire \mprj_io_analog_sel[2] ;
+  wire \mprj_io_analog_sel[30] ;
+  wire \mprj_io_analog_sel[31] ;
+  wire \mprj_io_analog_sel[32] ;
+  wire \mprj_io_analog_sel[33] ;
+  wire \mprj_io_analog_sel[34] ;
+  wire \mprj_io_analog_sel[35] ;
+  wire \mprj_io_analog_sel[36] ;
+  wire \mprj_io_analog_sel[37] ;
+  wire \mprj_io_analog_sel[3] ;
+  wire \mprj_io_analog_sel[4] ;
+  wire \mprj_io_analog_sel[5] ;
+  wire \mprj_io_analog_sel[6] ;
+  wire \mprj_io_analog_sel[7] ;
+  wire \mprj_io_analog_sel[8] ;
+  wire \mprj_io_analog_sel[9] ;
+  wire \mprj_io_dm[0] ;
+  wire \mprj_io_dm[100] ;
+  wire \mprj_io_dm[101] ;
+  wire \mprj_io_dm[102] ;
+  wire \mprj_io_dm[103] ;
+  wire \mprj_io_dm[104] ;
+  wire \mprj_io_dm[105] ;
+  wire \mprj_io_dm[106] ;
+  wire \mprj_io_dm[107] ;
+  wire \mprj_io_dm[108] ;
+  wire \mprj_io_dm[109] ;
+  wire \mprj_io_dm[10] ;
+  wire \mprj_io_dm[110] ;
+  wire \mprj_io_dm[111] ;
+  wire \mprj_io_dm[112] ;
+  wire \mprj_io_dm[113] ;
+  wire \mprj_io_dm[11] ;
+  wire \mprj_io_dm[12] ;
+  wire \mprj_io_dm[13] ;
+  wire \mprj_io_dm[14] ;
+  wire \mprj_io_dm[15] ;
+  wire \mprj_io_dm[16] ;
+  wire \mprj_io_dm[17] ;
+  wire \mprj_io_dm[18] ;
+  wire \mprj_io_dm[19] ;
+  wire \mprj_io_dm[1] ;
+  wire \mprj_io_dm[20] ;
+  wire \mprj_io_dm[21] ;
+  wire \mprj_io_dm[22] ;
+  wire \mprj_io_dm[23] ;
+  wire \mprj_io_dm[24] ;
+  wire \mprj_io_dm[25] ;
+  wire \mprj_io_dm[26] ;
+  wire \mprj_io_dm[27] ;
+  wire \mprj_io_dm[28] ;
+  wire \mprj_io_dm[29] ;
+  wire \mprj_io_dm[2] ;
+  wire \mprj_io_dm[30] ;
+  wire \mprj_io_dm[31] ;
+  wire \mprj_io_dm[32] ;
+  wire \mprj_io_dm[33] ;
+  wire \mprj_io_dm[34] ;
+  wire \mprj_io_dm[35] ;
+  wire \mprj_io_dm[36] ;
+  wire \mprj_io_dm[37] ;
+  wire \mprj_io_dm[38] ;
+  wire \mprj_io_dm[39] ;
+  wire \mprj_io_dm[3] ;
+  wire \mprj_io_dm[40] ;
+  wire \mprj_io_dm[41] ;
+  wire \mprj_io_dm[42] ;
+  wire \mprj_io_dm[43] ;
+  wire \mprj_io_dm[44] ;
+  wire \mprj_io_dm[45] ;
+  wire \mprj_io_dm[46] ;
+  wire \mprj_io_dm[47] ;
+  wire \mprj_io_dm[48] ;
+  wire \mprj_io_dm[49] ;
+  wire \mprj_io_dm[4] ;
+  wire \mprj_io_dm[50] ;
+  wire \mprj_io_dm[51] ;
+  wire \mprj_io_dm[52] ;
+  wire \mprj_io_dm[53] ;
+  wire \mprj_io_dm[54] ;
+  wire \mprj_io_dm[55] ;
+  wire \mprj_io_dm[56] ;
+  wire \mprj_io_dm[57] ;
+  wire \mprj_io_dm[58] ;
+  wire \mprj_io_dm[59] ;
+  wire \mprj_io_dm[5] ;
+  wire \mprj_io_dm[60] ;
+  wire \mprj_io_dm[61] ;
+  wire \mprj_io_dm[62] ;
+  wire \mprj_io_dm[63] ;
+  wire \mprj_io_dm[64] ;
+  wire \mprj_io_dm[65] ;
+  wire \mprj_io_dm[66] ;
+  wire \mprj_io_dm[67] ;
+  wire \mprj_io_dm[68] ;
+  wire \mprj_io_dm[69] ;
+  wire \mprj_io_dm[6] ;
+  wire \mprj_io_dm[70] ;
+  wire \mprj_io_dm[71] ;
+  wire \mprj_io_dm[72] ;
+  wire \mprj_io_dm[73] ;
+  wire \mprj_io_dm[74] ;
+  wire \mprj_io_dm[75] ;
+  wire \mprj_io_dm[76] ;
+  wire \mprj_io_dm[77] ;
+  wire \mprj_io_dm[78] ;
+  wire \mprj_io_dm[79] ;
+  wire \mprj_io_dm[7] ;
+  wire \mprj_io_dm[80] ;
+  wire \mprj_io_dm[81] ;
+  wire \mprj_io_dm[82] ;
+  wire \mprj_io_dm[83] ;
+  wire \mprj_io_dm[84] ;
+  wire \mprj_io_dm[85] ;
+  wire \mprj_io_dm[86] ;
+  wire \mprj_io_dm[87] ;
+  wire \mprj_io_dm[88] ;
+  wire \mprj_io_dm[89] ;
+  wire \mprj_io_dm[8] ;
+  wire \mprj_io_dm[90] ;
+  wire \mprj_io_dm[91] ;
+  wire \mprj_io_dm[92] ;
+  wire \mprj_io_dm[93] ;
+  wire \mprj_io_dm[94] ;
+  wire \mprj_io_dm[95] ;
+  wire \mprj_io_dm[96] ;
+  wire \mprj_io_dm[97] ;
+  wire \mprj_io_dm[98] ;
+  wire \mprj_io_dm[99] ;
+  wire \mprj_io_dm[9] ;
+  wire \mprj_io_holdover[0] ;
+  wire \mprj_io_holdover[10] ;
+  wire \mprj_io_holdover[11] ;
+  wire \mprj_io_holdover[12] ;
+  wire \mprj_io_holdover[13] ;
+  wire \mprj_io_holdover[14] ;
+  wire \mprj_io_holdover[15] ;
+  wire \mprj_io_holdover[16] ;
+  wire \mprj_io_holdover[17] ;
+  wire \mprj_io_holdover[18] ;
+  wire \mprj_io_holdover[19] ;
+  wire \mprj_io_holdover[1] ;
+  wire \mprj_io_holdover[20] ;
+  wire \mprj_io_holdover[21] ;
+  wire \mprj_io_holdover[22] ;
+  wire \mprj_io_holdover[23] ;
+  wire \mprj_io_holdover[24] ;
+  wire \mprj_io_holdover[25] ;
+  wire \mprj_io_holdover[26] ;
+  wire \mprj_io_holdover[27] ;
+  wire \mprj_io_holdover[28] ;
+  wire \mprj_io_holdover[29] ;
+  wire \mprj_io_holdover[2] ;
+  wire \mprj_io_holdover[30] ;
+  wire \mprj_io_holdover[31] ;
+  wire \mprj_io_holdover[32] ;
+  wire \mprj_io_holdover[33] ;
+  wire \mprj_io_holdover[34] ;
+  wire \mprj_io_holdover[35] ;
+  wire \mprj_io_holdover[36] ;
+  wire \mprj_io_holdover[37] ;
+  wire \mprj_io_holdover[3] ;
+  wire \mprj_io_holdover[4] ;
+  wire \mprj_io_holdover[5] ;
+  wire \mprj_io_holdover[6] ;
+  wire \mprj_io_holdover[7] ;
+  wire \mprj_io_holdover[8] ;
+  wire \mprj_io_holdover[9] ;
+  wire \mprj_io_ib_mode_sel[0] ;
+  wire \mprj_io_ib_mode_sel[10] ;
+  wire \mprj_io_ib_mode_sel[11] ;
+  wire \mprj_io_ib_mode_sel[12] ;
+  wire \mprj_io_ib_mode_sel[13] ;
+  wire \mprj_io_ib_mode_sel[14] ;
+  wire \mprj_io_ib_mode_sel[15] ;
+  wire \mprj_io_ib_mode_sel[16] ;
+  wire \mprj_io_ib_mode_sel[17] ;
+  wire \mprj_io_ib_mode_sel[18] ;
+  wire \mprj_io_ib_mode_sel[19] ;
+  wire \mprj_io_ib_mode_sel[1] ;
+  wire \mprj_io_ib_mode_sel[20] ;
+  wire \mprj_io_ib_mode_sel[21] ;
+  wire \mprj_io_ib_mode_sel[22] ;
+  wire \mprj_io_ib_mode_sel[23] ;
+  wire \mprj_io_ib_mode_sel[24] ;
+  wire \mprj_io_ib_mode_sel[25] ;
+  wire \mprj_io_ib_mode_sel[26] ;
+  wire \mprj_io_ib_mode_sel[27] ;
+  wire \mprj_io_ib_mode_sel[28] ;
+  wire \mprj_io_ib_mode_sel[29] ;
+  wire \mprj_io_ib_mode_sel[2] ;
+  wire \mprj_io_ib_mode_sel[30] ;
+  wire \mprj_io_ib_mode_sel[31] ;
+  wire \mprj_io_ib_mode_sel[32] ;
+  wire \mprj_io_ib_mode_sel[33] ;
+  wire \mprj_io_ib_mode_sel[34] ;
+  wire \mprj_io_ib_mode_sel[35] ;
+  wire \mprj_io_ib_mode_sel[36] ;
+  wire \mprj_io_ib_mode_sel[37] ;
+  wire \mprj_io_ib_mode_sel[3] ;
+  wire \mprj_io_ib_mode_sel[4] ;
+  wire \mprj_io_ib_mode_sel[5] ;
+  wire \mprj_io_ib_mode_sel[6] ;
+  wire \mprj_io_ib_mode_sel[7] ;
+  wire \mprj_io_ib_mode_sel[8] ;
+  wire \mprj_io_ib_mode_sel[9] ;
+  wire \mprj_io_in[0] ;
+  wire \mprj_io_in[10] ;
+  wire \mprj_io_in[11] ;
+  wire \mprj_io_in[12] ;
+  wire \mprj_io_in[13] ;
+  wire \mprj_io_in[14] ;
+  wire \mprj_io_in[15] ;
+  wire \mprj_io_in[16] ;
+  wire \mprj_io_in[17] ;
+  wire \mprj_io_in[18] ;
+  wire \mprj_io_in[19] ;
+  wire \mprj_io_in[1] ;
+  wire \mprj_io_in[20] ;
+  wire \mprj_io_in[21] ;
+  wire \mprj_io_in[22] ;
+  wire \mprj_io_in[23] ;
+  wire \mprj_io_in[24] ;
+  wire \mprj_io_in[25] ;
+  wire \mprj_io_in[26] ;
+  wire \mprj_io_in[27] ;
+  wire \mprj_io_in[28] ;
+  wire \mprj_io_in[29] ;
+  wire \mprj_io_in[2] ;
+  wire \mprj_io_in[30] ;
+  wire \mprj_io_in[31] ;
+  wire \mprj_io_in[32] ;
+  wire \mprj_io_in[33] ;
+  wire \mprj_io_in[34] ;
+  wire \mprj_io_in[35] ;
+  wire \mprj_io_in[36] ;
+  wire \mprj_io_in[37] ;
+  wire \mprj_io_in[3] ;
+  wire \mprj_io_in[4] ;
+  wire \mprj_io_in[5] ;
+  wire \mprj_io_in[6] ;
+  wire \mprj_io_in[7] ;
+  wire \mprj_io_in[8] ;
+  wire \mprj_io_in[9] ;
+  wire \mprj_io_inp_dis[0] ;
+  wire \mprj_io_inp_dis[10] ;
+  wire \mprj_io_inp_dis[11] ;
+  wire \mprj_io_inp_dis[12] ;
+  wire \mprj_io_inp_dis[13] ;
+  wire \mprj_io_inp_dis[14] ;
+  wire \mprj_io_inp_dis[15] ;
+  wire \mprj_io_inp_dis[16] ;
+  wire \mprj_io_inp_dis[17] ;
+  wire \mprj_io_inp_dis[18] ;
+  wire \mprj_io_inp_dis[19] ;
+  wire \mprj_io_inp_dis[1] ;
+  wire \mprj_io_inp_dis[20] ;
+  wire \mprj_io_inp_dis[21] ;
+  wire \mprj_io_inp_dis[22] ;
+  wire \mprj_io_inp_dis[23] ;
+  wire \mprj_io_inp_dis[24] ;
+  wire \mprj_io_inp_dis[25] ;
+  wire \mprj_io_inp_dis[26] ;
+  wire \mprj_io_inp_dis[27] ;
+  wire \mprj_io_inp_dis[28] ;
+  wire \mprj_io_inp_dis[29] ;
+  wire \mprj_io_inp_dis[2] ;
+  wire \mprj_io_inp_dis[30] ;
+  wire \mprj_io_inp_dis[31] ;
+  wire \mprj_io_inp_dis[32] ;
+  wire \mprj_io_inp_dis[33] ;
+  wire \mprj_io_inp_dis[34] ;
+  wire \mprj_io_inp_dis[35] ;
+  wire \mprj_io_inp_dis[36] ;
+  wire \mprj_io_inp_dis[37] ;
+  wire \mprj_io_inp_dis[3] ;
+  wire \mprj_io_inp_dis[4] ;
+  wire \mprj_io_inp_dis[5] ;
+  wire \mprj_io_inp_dis[6] ;
+  wire \mprj_io_inp_dis[7] ;
+  wire \mprj_io_inp_dis[8] ;
+  wire \mprj_io_inp_dis[9] ;
+  wire mprj_io_loader_clock;
+  wire mprj_io_loader_data_1;
+  wire mprj_io_loader_data_2;
+  wire mprj_io_loader_resetn;
+  wire mprj_io_loader_strobe;
+  wire \mprj_io_oeb[0] ;
+  wire \mprj_io_oeb[10] ;
+  wire \mprj_io_oeb[11] ;
+  wire \mprj_io_oeb[12] ;
+  wire \mprj_io_oeb[13] ;
+  wire \mprj_io_oeb[14] ;
+  wire \mprj_io_oeb[15] ;
+  wire \mprj_io_oeb[16] ;
+  wire \mprj_io_oeb[17] ;
+  wire \mprj_io_oeb[18] ;
+  wire \mprj_io_oeb[19] ;
+  wire \mprj_io_oeb[1] ;
+  wire \mprj_io_oeb[20] ;
+  wire \mprj_io_oeb[21] ;
+  wire \mprj_io_oeb[22] ;
+  wire \mprj_io_oeb[23] ;
+  wire \mprj_io_oeb[24] ;
+  wire \mprj_io_oeb[25] ;
+  wire \mprj_io_oeb[26] ;
+  wire \mprj_io_oeb[27] ;
+  wire \mprj_io_oeb[28] ;
+  wire \mprj_io_oeb[29] ;
+  wire \mprj_io_oeb[2] ;
+  wire \mprj_io_oeb[30] ;
+  wire \mprj_io_oeb[31] ;
+  wire \mprj_io_oeb[32] ;
+  wire \mprj_io_oeb[33] ;
+  wire \mprj_io_oeb[34] ;
+  wire \mprj_io_oeb[35] ;
+  wire \mprj_io_oeb[36] ;
+  wire \mprj_io_oeb[37] ;
+  wire \mprj_io_oeb[3] ;
+  wire \mprj_io_oeb[4] ;
+  wire \mprj_io_oeb[5] ;
+  wire \mprj_io_oeb[6] ;
+  wire \mprj_io_oeb[7] ;
+  wire \mprj_io_oeb[8] ;
+  wire \mprj_io_oeb[9] ;
+  wire \mprj_io_out[0] ;
+  wire \mprj_io_out[10] ;
+  wire \mprj_io_out[11] ;
+  wire \mprj_io_out[12] ;
+  wire \mprj_io_out[13] ;
+  wire \mprj_io_out[14] ;
+  wire \mprj_io_out[15] ;
+  wire \mprj_io_out[16] ;
+  wire \mprj_io_out[17] ;
+  wire \mprj_io_out[18] ;
+  wire \mprj_io_out[19] ;
+  wire \mprj_io_out[1] ;
+  wire \mprj_io_out[20] ;
+  wire \mprj_io_out[21] ;
+  wire \mprj_io_out[22] ;
+  wire \mprj_io_out[23] ;
+  wire \mprj_io_out[24] ;
+  wire \mprj_io_out[25] ;
+  wire \mprj_io_out[26] ;
+  wire \mprj_io_out[27] ;
+  wire \mprj_io_out[28] ;
+  wire \mprj_io_out[29] ;
+  wire \mprj_io_out[2] ;
+  wire \mprj_io_out[30] ;
+  wire \mprj_io_out[31] ;
+  wire \mprj_io_out[32] ;
+  wire \mprj_io_out[33] ;
+  wire \mprj_io_out[34] ;
+  wire \mprj_io_out[35] ;
+  wire \mprj_io_out[36] ;
+  wire \mprj_io_out[37] ;
+  wire \mprj_io_out[3] ;
+  wire \mprj_io_out[4] ;
+  wire \mprj_io_out[5] ;
+  wire \mprj_io_out[6] ;
+  wire \mprj_io_out[7] ;
+  wire \mprj_io_out[8] ;
+  wire \mprj_io_out[9] ;
+  wire \mprj_io_slow_sel[0] ;
+  wire \mprj_io_slow_sel[10] ;
+  wire \mprj_io_slow_sel[11] ;
+  wire \mprj_io_slow_sel[12] ;
+  wire \mprj_io_slow_sel[13] ;
+  wire \mprj_io_slow_sel[14] ;
+  wire \mprj_io_slow_sel[15] ;
+  wire \mprj_io_slow_sel[16] ;
+  wire \mprj_io_slow_sel[17] ;
+  wire \mprj_io_slow_sel[18] ;
+  wire \mprj_io_slow_sel[19] ;
+  wire \mprj_io_slow_sel[1] ;
+  wire \mprj_io_slow_sel[20] ;
+  wire \mprj_io_slow_sel[21] ;
+  wire \mprj_io_slow_sel[22] ;
+  wire \mprj_io_slow_sel[23] ;
+  wire \mprj_io_slow_sel[24] ;
+  wire \mprj_io_slow_sel[25] ;
+  wire \mprj_io_slow_sel[26] ;
+  wire \mprj_io_slow_sel[27] ;
+  wire \mprj_io_slow_sel[28] ;
+  wire \mprj_io_slow_sel[29] ;
+  wire \mprj_io_slow_sel[2] ;
+  wire \mprj_io_slow_sel[30] ;
+  wire \mprj_io_slow_sel[31] ;
+  wire \mprj_io_slow_sel[32] ;
+  wire \mprj_io_slow_sel[33] ;
+  wire \mprj_io_slow_sel[34] ;
+  wire \mprj_io_slow_sel[35] ;
+  wire \mprj_io_slow_sel[36] ;
+  wire \mprj_io_slow_sel[37] ;
+  wire \mprj_io_slow_sel[3] ;
+  wire \mprj_io_slow_sel[4] ;
+  wire \mprj_io_slow_sel[5] ;
+  wire \mprj_io_slow_sel[6] ;
+  wire \mprj_io_slow_sel[7] ;
+  wire \mprj_io_slow_sel[8] ;
+  wire \mprj_io_slow_sel[9] ;
+  wire \mprj_io_vtrip_sel[0] ;
+  wire \mprj_io_vtrip_sel[10] ;
+  wire \mprj_io_vtrip_sel[11] ;
+  wire \mprj_io_vtrip_sel[12] ;
+  wire \mprj_io_vtrip_sel[13] ;
+  wire \mprj_io_vtrip_sel[14] ;
+  wire \mprj_io_vtrip_sel[15] ;
+  wire \mprj_io_vtrip_sel[16] ;
+  wire \mprj_io_vtrip_sel[17] ;
+  wire \mprj_io_vtrip_sel[18] ;
+  wire \mprj_io_vtrip_sel[19] ;
+  wire \mprj_io_vtrip_sel[1] ;
+  wire \mprj_io_vtrip_sel[20] ;
+  wire \mprj_io_vtrip_sel[21] ;
+  wire \mprj_io_vtrip_sel[22] ;
+  wire \mprj_io_vtrip_sel[23] ;
+  wire \mprj_io_vtrip_sel[24] ;
+  wire \mprj_io_vtrip_sel[25] ;
+  wire \mprj_io_vtrip_sel[26] ;
+  wire \mprj_io_vtrip_sel[27] ;
+  wire \mprj_io_vtrip_sel[28] ;
+  wire \mprj_io_vtrip_sel[29] ;
+  wire \mprj_io_vtrip_sel[2] ;
+  wire \mprj_io_vtrip_sel[30] ;
+  wire \mprj_io_vtrip_sel[31] ;
+  wire \mprj_io_vtrip_sel[32] ;
+  wire \mprj_io_vtrip_sel[33] ;
+  wire \mprj_io_vtrip_sel[34] ;
+  wire \mprj_io_vtrip_sel[35] ;
+  wire \mprj_io_vtrip_sel[36] ;
+  wire \mprj_io_vtrip_sel[37] ;
+  wire \mprj_io_vtrip_sel[3] ;
+  wire \mprj_io_vtrip_sel[4] ;
+  wire \mprj_io_vtrip_sel[5] ;
+  wire \mprj_io_vtrip_sel[6] ;
+  wire \mprj_io_vtrip_sel[7] ;
+  wire \mprj_io_vtrip_sel[8] ;
+  wire \mprj_io_vtrip_sel[9] ;
+  wire mprj_reset;
+  wire \mprj_sel_o_core[0] ;
+  wire \mprj_sel_o_core[1] ;
+  wire \mprj_sel_o_core[2] ;
+  wire \mprj_sel_o_core[3] ;
+  wire \mprj_sel_o_user[0] ;
+  wire \mprj_sel_o_user[1] ;
+  wire \mprj_sel_o_user[2] ;
+  wire \mprj_sel_o_user[3] ;
+  wire mprj_stb_o_core;
+  wire mprj_stb_o_user;
+  wire mprj_vcc_pwrgood;
+  wire mprj_vdd_pwrgood;
+  wire mprj_we_o_core;
+  wire mprj_we_o_user;
+  wire \one_loop1[10] ;
+  wire \one_loop1[11] ;
+  wire \one_loop1[12] ;
+  wire \one_loop1[13] ;
+  wire \one_loop1[14] ;
+  wire \one_loop1[15] ;
+  wire \one_loop1[16] ;
+  wire \one_loop1[17] ;
+  wire \one_loop1[18] ;
+  wire \one_loop1[2] ;
+  wire \one_loop1[3] ;
+  wire \one_loop1[4] ;
+  wire \one_loop1[5] ;
+  wire \one_loop1[6] ;
+  wire \one_loop1[7] ;
+  wire \one_loop1[8] ;
+  wire \one_loop1[9] ;
+  wire \one_loop2[0] ;
+  wire \one_loop2[10] ;
+  wire \one_loop2[11] ;
+  wire \one_loop2[12] ;
+  wire \one_loop2[13] ;
+  wire \one_loop2[14] ;
+  wire \one_loop2[15] ;
+  wire \one_loop2[1] ;
+  wire \one_loop2[2] ;
+  wire \one_loop2[3] ;
+  wire \one_loop2[4] ;
+  wire \one_loop2[5] ;
+  wire \one_loop2[6] ;
+  wire \one_loop2[7] ;
+  wire \one_loop2[8] ;
+  wire \one_loop2[9] ;
+  wire pll_clk;
+  wire pll_clk90;
+  wire por_l;
+  wire porb_h;
+  wire porb_l;
+  wire qspi_enabled;
+  input resetb;
+  wire rstb_h;
+  wire rstb_l;
+  wire ser_rx;
+  wire ser_tx;
+  wire spi_csb;
+  wire spi_enabled;
+  wire \spi_pll90_sel[0] ;
+  wire \spi_pll90_sel[1] ;
+  wire \spi_pll90_sel[2] ;
+  wire spi_pll_dco_ena;
+  wire \spi_pll_div[0] ;
+  wire \spi_pll_div[1] ;
+  wire \spi_pll_div[2] ;
+  wire \spi_pll_div[3] ;
+  wire \spi_pll_div[4] ;
+  wire spi_pll_ena;
+  wire \spi_pll_sel[0] ;
+  wire \spi_pll_sel[1] ;
+  wire \spi_pll_sel[2] ;
+  wire \spi_pll_trim[0] ;
+  wire \spi_pll_trim[10] ;
+  wire \spi_pll_trim[11] ;
+  wire \spi_pll_trim[12] ;
+  wire \spi_pll_trim[13] ;
+  wire \spi_pll_trim[14] ;
+  wire \spi_pll_trim[15] ;
+  wire \spi_pll_trim[16] ;
+  wire \spi_pll_trim[17] ;
+  wire \spi_pll_trim[18] ;
+  wire \spi_pll_trim[19] ;
+  wire \spi_pll_trim[1] ;
+  wire \spi_pll_trim[20] ;
+  wire \spi_pll_trim[21] ;
+  wire \spi_pll_trim[22] ;
+  wire \spi_pll_trim[23] ;
+  wire \spi_pll_trim[24] ;
+  wire \spi_pll_trim[25] ;
+  wire \spi_pll_trim[2] ;
+  wire \spi_pll_trim[3] ;
+  wire \spi_pll_trim[4] ;
+  wire \spi_pll_trim[5] ;
+  wire \spi_pll_trim[6] ;
+  wire \spi_pll_trim[7] ;
+  wire \spi_pll_trim[8] ;
+  wire \spi_pll_trim[9] ;
+  wire spi_sck;
+  wire spi_sdi;
+  wire spi_sdo;
+  wire spi_sdoenb;
+  wire trap;
+  wire uart_enabled;
+  wire \user_analog_io[0] ;
+  wire \user_analog_io[10] ;
+  wire \user_analog_io[11] ;
+  wire \user_analog_io[12] ;
+  wire \user_analog_io[13] ;
+  wire \user_analog_io[14] ;
+  wire \user_analog_io[15] ;
+  wire \user_analog_io[16] ;
+  wire \user_analog_io[17] ;
+  wire \user_analog_io[18] ;
+  wire \user_analog_io[19] ;
+  wire \user_analog_io[1] ;
+  wire \user_analog_io[20] ;
+  wire \user_analog_io[21] ;
+  wire \user_analog_io[22] ;
+  wire \user_analog_io[23] ;
+  wire \user_analog_io[24] ;
+  wire \user_analog_io[25] ;
+  wire \user_analog_io[26] ;
+  wire \user_analog_io[27] ;
+  wire \user_analog_io[28] ;
+  wire \user_analog_io[2] ;
+  wire \user_analog_io[3] ;
+  wire \user_analog_io[4] ;
+  wire \user_analog_io[5] ;
+  wire \user_analog_io[6] ;
+  wire \user_analog_io[7] ;
+  wire \user_analog_io[8] ;
+  wire \user_analog_io[9] ;
+  wire \user_io_in[0] ;
+  wire \user_io_in[10] ;
+  wire \user_io_in[11] ;
+  wire \user_io_in[12] ;
+  wire \user_io_in[13] ;
+  wire \user_io_in[14] ;
+  wire \user_io_in[15] ;
+  wire \user_io_in[16] ;
+  wire \user_io_in[17] ;
+  wire \user_io_in[18] ;
+  wire \user_io_in[19] ;
+  wire \user_io_in[1] ;
+  wire \user_io_in[20] ;
+  wire \user_io_in[21] ;
+  wire \user_io_in[22] ;
+  wire \user_io_in[23] ;
+  wire \user_io_in[24] ;
+  wire \user_io_in[25] ;
+  wire \user_io_in[26] ;
+  wire \user_io_in[27] ;
+  wire \user_io_in[28] ;
+  wire \user_io_in[29] ;
+  wire \user_io_in[2] ;
+  wire \user_io_in[30] ;
+  wire \user_io_in[31] ;
+  wire \user_io_in[32] ;
+  wire \user_io_in[33] ;
+  wire \user_io_in[34] ;
+  wire \user_io_in[35] ;
+  wire \user_io_in[36] ;
+  wire \user_io_in[37] ;
+  wire \user_io_in[3] ;
+  wire \user_io_in[4] ;
+  wire \user_io_in[5] ;
+  wire \user_io_in[6] ;
+  wire \user_io_in[7] ;
+  wire \user_io_in[8] ;
+  wire \user_io_in[9] ;
+  wire \user_io_oeb[0] ;
+  wire \user_io_oeb[10] ;
+  wire \user_io_oeb[11] ;
+  wire \user_io_oeb[12] ;
+  wire \user_io_oeb[13] ;
+  wire \user_io_oeb[14] ;
+  wire \user_io_oeb[15] ;
+  wire \user_io_oeb[16] ;
+  wire \user_io_oeb[17] ;
+  wire \user_io_oeb[18] ;
+  wire \user_io_oeb[19] ;
+  wire \user_io_oeb[1] ;
+  wire \user_io_oeb[20] ;
+  wire \user_io_oeb[21] ;
+  wire \user_io_oeb[22] ;
+  wire \user_io_oeb[23] ;
+  wire \user_io_oeb[24] ;
+  wire \user_io_oeb[25] ;
+  wire \user_io_oeb[26] ;
+  wire \user_io_oeb[27] ;
+  wire \user_io_oeb[28] ;
+  wire \user_io_oeb[29] ;
+  wire \user_io_oeb[2] ;
+  wire \user_io_oeb[30] ;
+  wire \user_io_oeb[31] ;
+  wire \user_io_oeb[32] ;
+  wire \user_io_oeb[33] ;
+  wire \user_io_oeb[34] ;
+  wire \user_io_oeb[35] ;
+  wire \user_io_oeb[36] ;
+  wire \user_io_oeb[37] ;
+  wire \user_io_oeb[3] ;
+  wire \user_io_oeb[4] ;
+  wire \user_io_oeb[5] ;
+  wire \user_io_oeb[6] ;
+  wire \user_io_oeb[7] ;
+  wire \user_io_oeb[8] ;
+  wire \user_io_oeb[9] ;
+  wire \user_io_out[0] ;
+  wire \user_io_out[10] ;
+  wire \user_io_out[11] ;
+  wire \user_io_out[12] ;
+  wire \user_io_out[13] ;
+  wire \user_io_out[14] ;
+  wire \user_io_out[15] ;
+  wire \user_io_out[16] ;
+  wire \user_io_out[17] ;
+  wire \user_io_out[18] ;
+  wire \user_io_out[19] ;
+  wire \user_io_out[1] ;
+  wire \user_io_out[20] ;
+  wire \user_io_out[21] ;
+  wire \user_io_out[22] ;
+  wire \user_io_out[23] ;
+  wire \user_io_out[24] ;
+  wire \user_io_out[25] ;
+  wire \user_io_out[26] ;
+  wire \user_io_out[27] ;
+  wire \user_io_out[28] ;
+  wire \user_io_out[29] ;
+  wire \user_io_out[2] ;
+  wire \user_io_out[30] ;
+  wire \user_io_out[31] ;
+  wire \user_io_out[32] ;
+  wire \user_io_out[33] ;
+  wire \user_io_out[34] ;
+  wire \user_io_out[35] ;
+  wire \user_io_out[36] ;
+  wire \user_io_out[37] ;
+  wire \user_io_out[3] ;
+  wire \user_io_out[4] ;
+  wire \user_io_out[5] ;
+  wire \user_io_out[6] ;
+  wire \user_io_out[7] ;
+  wire \user_io_out[8] ;
+  wire \user_io_out[9] ;
+  wire \user_irq[0] ;
+  wire \user_irq[1] ;
+  wire \user_irq[2] ;
+  wire \user_irq_core[0] ;
+  wire \user_irq_core[1] ;
+  wire \user_irq_core[2] ;
+  wire \user_irq_ena[0] ;
+  wire \user_irq_ena[1] ;
+  wire \user_irq_ena[2] ;
+  inout vccd;
+  inout vccd1;
+  wire vccd1_core;
+  inout vccd2;
+  wire vccd2_core;
+  wire vccd_core;
+  inout vdda;
+  inout vdda1;
+  inout vdda1_2;
+  wire vdda1_core;
+  inout vdda2;
+  wire vdda2_core;
+  wire vdda_core;
+  inout vddio;
+  inout vddio_2;
+  wire vddio_core;
+  inout vssa;
+  inout vssa1;
+  inout vssa1_2;
+  wire vssa1_core;
+  inout vssa2;
+  wire vssa2_core;
+  wire vssa_core;
+  inout vssd;
+  inout vssd1;
+  wire vssd1_core;
+  inout vssd2;
+  wire vssd2_core;
+  wire vssd_core;
+  inout vssio;
+  inout vssio_2;
+  wire vssio_core;
+  caravel_clocking \clocking  (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .core_clk(caravel_clk),
+    .ext_clk(clock_core),
+    .ext_clk_sel(ext_clk_sel),
+    .ext_reset(ext_reset),
+    .pll_clk(pll_clk),
+    .pll_clk90(pll_clk90),
+    .resetb(rstb_l),
+    .resetb_sync(caravel_rstn),
+    .sel({ \spi_pll_sel[2] , \spi_pll_sel[1] , \spi_pll_sel[0]  }),
+    .sel2({ \spi_pll90_sel[2] , \spi_pll90_sel[1] , \spi_pll90_sel[0]  }),
+    .user_clk(caravel_clk2)
+  );
+  gpio_defaults_block_1803 gpio_defaults_block_0  (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0]  })
+  );
+  gpio_defaults_block_1803 \gpio_defaults_block_1  (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_10 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_11 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_12 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_13 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_14 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_15 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_16 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_17 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_18 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_19 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_20 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_21 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_22 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286]  })
+  );
+  gpio_defaults_block_0403 gpio_defaults_block_2 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26]  })
+  );
+  gpio_defaults_block_0403 gpio_defaults_block_3 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39]  })
+  );
+  gpio_defaults_block_0403 gpio_defaults_block_4 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_23 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_24 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_25 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_26 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_27 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[363] , \gpio_defaults[362] , \gpio_defaults[361] , \gpio_defaults[360] , \gpio_defaults[359] , \gpio_defaults[358] , \gpio_defaults[357] , \gpio_defaults[356] , \gpio_defaults[355] , \gpio_defaults[354] , \gpio_defaults[353] , \gpio_defaults[352] , \gpio_defaults[351]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_28 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[376] , \gpio_defaults[375] , \gpio_defaults[374] , \gpio_defaults[373] , \gpio_defaults[372] , \gpio_defaults[371] , \gpio_defaults[370] , \gpio_defaults[369] , \gpio_defaults[368] , \gpio_defaults[367] , \gpio_defaults[366] , \gpio_defaults[365] , \gpio_defaults[364]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_29 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[389] , \gpio_defaults[388] , \gpio_defaults[387] , \gpio_defaults[386] , \gpio_defaults[385] , \gpio_defaults[384] , \gpio_defaults[383] , \gpio_defaults[382] , \gpio_defaults[381] , \gpio_defaults[380] , \gpio_defaults[379] , \gpio_defaults[378] , \gpio_defaults[377]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_30 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[402] , \gpio_defaults[401] , \gpio_defaults[400] , \gpio_defaults[399] , \gpio_defaults[398] , \gpio_defaults[397] , \gpio_defaults[396] , \gpio_defaults[395] , \gpio_defaults[394] , \gpio_defaults[393] , \gpio_defaults[392] , \gpio_defaults[391] , \gpio_defaults[390]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_31 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[415] , \gpio_defaults[414] , \gpio_defaults[413] , \gpio_defaults[412] , \gpio_defaults[411] , \gpio_defaults[410] , \gpio_defaults[409] , \gpio_defaults[408] , \gpio_defaults[407] , \gpio_defaults[406] , \gpio_defaults[405] , \gpio_defaults[404] , \gpio_defaults[403]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_32 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[428] , \gpio_defaults[427] , \gpio_defaults[426] , \gpio_defaults[425] , \gpio_defaults[424] , \gpio_defaults[423] , \gpio_defaults[422] , \gpio_defaults[421] , \gpio_defaults[420] , \gpio_defaults[419] , \gpio_defaults[418] , \gpio_defaults[417] , \gpio_defaults[416]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_33 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[441] , \gpio_defaults[440] , \gpio_defaults[439] , \gpio_defaults[438] , \gpio_defaults[437] , \gpio_defaults[436] , \gpio_defaults[435] , \gpio_defaults[434] , \gpio_defaults[433] , \gpio_defaults[432] , \gpio_defaults[431] , \gpio_defaults[430] , \gpio_defaults[429]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_34 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[454] , \gpio_defaults[453] , \gpio_defaults[452] , \gpio_defaults[451] , \gpio_defaults[450] , \gpio_defaults[449] , \gpio_defaults[448] , \gpio_defaults[447] , \gpio_defaults[446] , \gpio_defaults[445] , \gpio_defaults[444] , \gpio_defaults[443] , \gpio_defaults[442]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_35 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[467] , \gpio_defaults[466] , \gpio_defaults[465] , \gpio_defaults[464] , \gpio_defaults[463] , \gpio_defaults[462] , \gpio_defaults[461] , \gpio_defaults[460] , \gpio_defaults[459] , \gpio_defaults[458] , \gpio_defaults[457] , \gpio_defaults[456] , \gpio_defaults[455]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_36 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[480] , \gpio_defaults[479] , \gpio_defaults[478] , \gpio_defaults[477] , \gpio_defaults[476] , \gpio_defaults[475] , \gpio_defaults[474] , \gpio_defaults[473] , \gpio_defaults[472] , \gpio_defaults[471] , \gpio_defaults[470] , \gpio_defaults[469] , \gpio_defaults[468]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_37 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[493] , \gpio_defaults[492] , \gpio_defaults[491] , \gpio_defaults[490] , \gpio_defaults[489] , \gpio_defaults[488] , \gpio_defaults[487] , \gpio_defaults[486] , \gpio_defaults[485] , \gpio_defaults[484] , \gpio_defaults[483] , \gpio_defaults[482] , \gpio_defaults[481]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_5 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_6 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_7 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_8 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_9 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117]  })
+  );
+  gpio_control_block \gpio_control_bidir_1[0]  (
+    .gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0]  }),
+    .mgmt_gpio_in(\mgmt_io_in[0] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[0] ),
+    .mgmt_gpio_out(\mgmt_io_out[0] ),
+    .one(),
+    .pad_gpio_ana_en(\mprj_io_analog_en[0] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[0] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[0] ),
+    .pad_gpio_dm({ \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[0] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[0] ),
+    .pad_gpio_in(\mprj_io_in[0] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[0] ),
+    .pad_gpio_out(\mprj_io_out[0] ),
+    .pad_gpio_outenb(\mprj_io_oeb[0] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[0] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[0] ),
+    .resetn(\gpio_resetn_1_shifted[0] ),
+    .resetn_out(\gpio_resetn_1[0] ),
+    .serial_clock(\gpio_clock_1_shifted[0] ),
+    .serial_clock_out(\gpio_clock_1[0] ),
+    .serial_data_in(\gpio_serial_link_1_shifted[0] ),
+    .serial_data_out(\gpio_serial_link_1[0] ),
+    .serial_load(\gpio_load_1_shifted[0] ),
+    .serial_load_out(\gpio_load_1[0] ),
+    .user_gpio_in(\user_io_in[0] ),
+    .user_gpio_oeb(\user_io_oeb[0] ),
+    .user_gpio_out(\user_io_out[0] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_1[1]  (
+    .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13]  }),
+    .mgmt_gpio_in(\mgmt_io_in[1] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[1] ),
+    .mgmt_gpio_out(\mgmt_io_out[1] ),
+    .one(),
+    .pad_gpio_ana_en(\mprj_io_analog_en[1] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[1] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[1] ),
+    .pad_gpio_dm({ \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[1] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[1] ),
+    .pad_gpio_in(\mprj_io_in[1] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[1] ),
+    .pad_gpio_out(\mprj_io_out[1] ),
+    .pad_gpio_outenb(\mprj_io_oeb[1] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[1] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[1] ),
+    .resetn(\gpio_resetn_1[0] ),
+    .resetn_out(\gpio_resetn_1[1] ),
+    .serial_clock(\gpio_clock_1[0] ),
+    .serial_clock_out(\gpio_clock_1[1] ),
+    .serial_data_in(\gpio_serial_link_1[0] ),
+    .serial_data_out(\gpio_serial_link_1[1] ),
+    .serial_load(\gpio_load_1[0] ),
+    .serial_load_out(\gpio_load_1[1] ),
+    .user_gpio_in(\user_io_in[1] ),
+    .user_gpio_oeb(\user_io_oeb[1] ),
+    .user_gpio_out(\user_io_out[1] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_2[0]  (
+    .gpio_defaults({ \gpio_defaults[467] , \gpio_defaults[466] , \gpio_defaults[465] , \gpio_defaults[464] , \gpio_defaults[463] , \gpio_defaults[462] , \gpio_defaults[461] , \gpio_defaults[460] , \gpio_defaults[459] , \gpio_defaults[458] , \gpio_defaults[457] , \gpio_defaults[456] , \gpio_defaults[455]  }),
+    .mgmt_gpio_in(\mgmt_io_in[35] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[2] ),
+    .mgmt_gpio_out(\mgmt_io_out[2] ),
+    .one(),
+    .pad_gpio_ana_en(\mprj_io_analog_en[35] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[35] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[35] ),
+    .pad_gpio_dm({ \mprj_io_dm[107] , \mprj_io_dm[106] , \mprj_io_dm[105]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[35] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[35] ),
+    .pad_gpio_in(\mprj_io_in[35] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[35] ),
+    .pad_gpio_out(\mprj_io_out[35] ),
+    .pad_gpio_outenb(\mprj_io_oeb[35] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[35] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[35] ),
+    .resetn(\gpio_resetn_2[17] ),
+    .resetn_out(\gpio_resetn_2[16] ),
+    .serial_clock(\gpio_clock_2[17] ),
+    .serial_clock_out(\gpio_clock_2[16] ),
+    .serial_data_in(\gpio_serial_link_2[17] ),
+    .serial_data_out(\gpio_serial_link_2[16] ),
+    .serial_load(\gpio_load_2[17] ),
+    .serial_load_out(\gpio_load_2[16] ),
+    .user_gpio_in(\user_io_in[35] ),
+    .user_gpio_oeb(\user_io_oeb[35] ),
+    .user_gpio_out(\user_io_out[35] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_2[1]  (
+    .gpio_defaults({ \gpio_defaults[480] , \gpio_defaults[479] , \gpio_defaults[478] , \gpio_defaults[477] , \gpio_defaults[476] , \gpio_defaults[475] , \gpio_defaults[474] , \gpio_defaults[473] , \gpio_defaults[472] , \gpio_defaults[471] , \gpio_defaults[470] , \gpio_defaults[469] , \gpio_defaults[468]  }),
+    .mgmt_gpio_in(\mgmt_io_in[36] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[3] ),
+    .mgmt_gpio_out(\mgmt_io_out[3] ),
+    .one(),
+    .pad_gpio_ana_en(\mprj_io_analog_en[36] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[36] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[36] ),
+    .pad_gpio_dm({ \mprj_io_dm[110] , \mprj_io_dm[109] , \mprj_io_dm[108]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[36] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[36] ),
+    .pad_gpio_in(\mprj_io_in[36] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[36] ),
+    .pad_gpio_out(\mprj_io_out[36] ),
+    .pad_gpio_outenb(\mprj_io_oeb[36] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[36] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[36] ),
+    .resetn(\gpio_resetn_2[18] ),
+    .resetn_out(\gpio_resetn_2[17] ),
+    .serial_clock(\gpio_clock_2[18] ),
+    .serial_clock_out(\gpio_clock_2[17] ),
+    .serial_data_in(\gpio_serial_link_2[18] ),
+    .serial_data_out(\gpio_serial_link_2[17] ),
+    .serial_load(\gpio_load_2[18] ),
+    .serial_load_out(\gpio_load_2[17] ),
+    .user_gpio_in(\user_io_in[36] ),
+    .user_gpio_oeb(\user_io_oeb[36] ),
+    .user_gpio_out(\user_io_out[36] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_2[2]  (
+    .gpio_defaults({ \gpio_defaults[493] , \gpio_defaults[492] , \gpio_defaults[491] , \gpio_defaults[490] , \gpio_defaults[489] , \gpio_defaults[488] , \gpio_defaults[487] , \gpio_defaults[486] , \gpio_defaults[485] , \gpio_defaults[484] , \gpio_defaults[483] , \gpio_defaults[482] , \gpio_defaults[481]  }),
+    .mgmt_gpio_in(\mgmt_io_in[37] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[4] ),
+    .mgmt_gpio_out(\mgmt_io_out[4] ),
+    .one(),
+    .pad_gpio_ana_en(\mprj_io_analog_en[37] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[37] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[37] ),
+    .pad_gpio_dm({ \mprj_io_dm[113] , \mprj_io_dm[112] , \mprj_io_dm[111]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[37] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[37] ),
+    .pad_gpio_in(\mprj_io_in[37] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[37] ),
+    .pad_gpio_out(\mprj_io_out[37] ),
+    .pad_gpio_outenb(\mprj_io_oeb[37] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[37] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[37] ),
+    .resetn(\gpio_resetn_2_shifted[18] ),
+    .resetn_out(\gpio_resetn_2[18] ),
+    .serial_clock(\gpio_clock_2_shifted[18] ),
+    .serial_clock_out(\gpio_clock_2[18] ),
+    .serial_data_in(\gpio_serial_link_2_shifted[18] ),
+    .serial_data_out(\gpio_serial_link_2[18] ),
+    .serial_load(\gpio_load_2_shifted[18] ),
+    .serial_load_out(\gpio_load_2[18] ),
+    .user_gpio_in(\user_io_in[37] ),
+    .user_gpio_oeb(\user_io_oeb[37] ),
+    .user_gpio_out(\user_io_out[37] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[0]  (
+    .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104]  }),
+    .mgmt_gpio_in(\mgmt_io_in[8] ),
+    .mgmt_gpio_oeb(\one_loop1[8] ),
+    .mgmt_gpio_out(\mgmt_io_in[8] ),
+    .one(\one_loop1[8] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[8] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[8] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[8] ),
+    .pad_gpio_dm({ \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[8] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[8] ),
+    .pad_gpio_in(\mprj_io_in[8] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[8] ),
+    .pad_gpio_out(\mprj_io_out[8] ),
+    .pad_gpio_outenb(\mprj_io_oeb[8] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[8] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[8] ),
+    .resetn(\gpio_resetn_1[7] ),
+    .resetn_out(\gpio_resetn_1[8] ),
+    .serial_clock(\gpio_clock_1[7] ),
+    .serial_clock_out(\gpio_clock_1[8] ),
+    .serial_data_in(\gpio_serial_link_1[7] ),
+    .serial_data_out(\gpio_serial_link_1[8] ),
+    .serial_load(\gpio_load_1[7] ),
+    .serial_load_out(\gpio_load_1[8] ),
+    .user_gpio_in(\user_io_in[8] ),
+    .user_gpio_oeb(\user_io_oeb[8] ),
+    .user_gpio_out(\user_io_out[8] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[10]  (
+    .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234]  }),
+    .mgmt_gpio_in(\mgmt_io_in[18] ),
+    .mgmt_gpio_oeb(\one_loop1[18] ),
+    .mgmt_gpio_out(\mgmt_io_in[18] ),
+    .one(\one_loop1[18] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[18] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[18] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[18] ),
+    .pad_gpio_dm({ \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[18] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[18] ),
+    .pad_gpio_in(\mprj_io_in[18] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[18] ),
+    .pad_gpio_out(\mprj_io_out[18] ),
+    .pad_gpio_outenb(\mprj_io_oeb[18] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[18] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[18] ),
+    .resetn(\gpio_resetn_1[17] ),
+    .resetn_out(\gpio_resetn_1[18] ),
+    .serial_clock(\gpio_clock_1[17] ),
+    .serial_clock_out(\gpio_clock_1[18] ),
+    .serial_data_in(\gpio_serial_link_1[17] ),
+    .serial_data_out(\gpio_serial_link_1[18] ),
+    .serial_load(\gpio_load_1[17] ),
+    .serial_load_out(\gpio_load_1[18] ),
+    .user_gpio_in(\user_io_in[18] ),
+    .user_gpio_oeb(\user_io_oeb[18] ),
+    .user_gpio_out(\user_io_out[18] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[1]  (
+    .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117]  }),
+    .mgmt_gpio_in(\mgmt_io_in[9] ),
+    .mgmt_gpio_oeb(\one_loop1[9] ),
+    .mgmt_gpio_out(\mgmt_io_in[9] ),
+    .one(\one_loop1[9] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[9] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[9] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[9] ),
+    .pad_gpio_dm({ \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[9] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[9] ),
+    .pad_gpio_in(\mprj_io_in[9] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[9] ),
+    .pad_gpio_out(\mprj_io_out[9] ),
+    .pad_gpio_outenb(\mprj_io_oeb[9] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[9] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[9] ),
+    .resetn(\gpio_resetn_1[8] ),
+    .resetn_out(\gpio_resetn_1[9] ),
+    .serial_clock(\gpio_clock_1[8] ),
+    .serial_clock_out(\gpio_clock_1[9] ),
+    .serial_data_in(\gpio_serial_link_1[8] ),
+    .serial_data_out(\gpio_serial_link_1[9] ),
+    .serial_load(\gpio_load_1[8] ),
+    .serial_load_out(\gpio_load_1[9] ),
+    .user_gpio_in(\user_io_in[9] ),
+    .user_gpio_oeb(\user_io_oeb[9] ),
+    .user_gpio_out(\user_io_out[9] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[2]  (
+    .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130]  }),
+    .mgmt_gpio_in(\mgmt_io_in[10] ),
+    .mgmt_gpio_oeb(\one_loop1[10] ),
+    .mgmt_gpio_out(\mgmt_io_in[10] ),
+    .one(\one_loop1[10] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[10] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[10] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[10] ),
+    .pad_gpio_dm({ \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[10] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[10] ),
+    .pad_gpio_in(\mprj_io_in[10] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[10] ),
+    .pad_gpio_out(\mprj_io_out[10] ),
+    .pad_gpio_outenb(\mprj_io_oeb[10] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[10] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[10] ),
+    .resetn(\gpio_resetn_1[9] ),
+    .resetn_out(\gpio_resetn_1[10] ),
+    .serial_clock(\gpio_clock_1[9] ),
+    .serial_clock_out(\gpio_clock_1[10] ),
+    .serial_data_in(\gpio_serial_link_1[9] ),
+    .serial_data_out(\gpio_serial_link_1[10] ),
+    .serial_load(\gpio_load_1[9] ),
+    .serial_load_out(\gpio_load_1[10] ),
+    .user_gpio_in(\user_io_in[10] ),
+    .user_gpio_oeb(\user_io_oeb[10] ),
+    .user_gpio_out(\user_io_out[10] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[3]  (
+    .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143]  }),
+    .mgmt_gpio_in(\mgmt_io_in[11] ),
+    .mgmt_gpio_oeb(\one_loop1[11] ),
+    .mgmt_gpio_out(\mgmt_io_in[11] ),
+    .one(\one_loop1[11] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[11] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[11] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[11] ),
+    .pad_gpio_dm({ \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[11] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[11] ),
+    .pad_gpio_in(\mprj_io_in[11] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[11] ),
+    .pad_gpio_out(\mprj_io_out[11] ),
+    .pad_gpio_outenb(\mprj_io_oeb[11] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[11] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[11] ),
+    .resetn(\gpio_resetn_1[10] ),
+    .resetn_out(\gpio_resetn_1[11] ),
+    .serial_clock(\gpio_clock_1[10] ),
+    .serial_clock_out(\gpio_clock_1[11] ),
+    .serial_data_in(\gpio_serial_link_1[10] ),
+    .serial_data_out(\gpio_serial_link_1[11] ),
+    .serial_load(\gpio_load_1[10] ),
+    .serial_load_out(\gpio_load_1[11] ),
+    .user_gpio_in(\user_io_in[11] ),
+    .user_gpio_oeb(\user_io_oeb[11] ),
+    .user_gpio_out(\user_io_out[11] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[4]  (
+    .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156]  }),
+    .mgmt_gpio_in(\mgmt_io_in[12] ),
+    .mgmt_gpio_oeb(\one_loop1[12] ),
+    .mgmt_gpio_out(\mgmt_io_in[12] ),
+    .one(\one_loop1[12] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[12] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[12] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[12] ),
+    .pad_gpio_dm({ \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[12] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[12] ),
+    .pad_gpio_in(\mprj_io_in[12] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[12] ),
+    .pad_gpio_out(\mprj_io_out[12] ),
+    .pad_gpio_outenb(\mprj_io_oeb[12] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[12] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[12] ),
+    .resetn(\gpio_resetn_1[11] ),
+    .resetn_out(\gpio_resetn_1[12] ),
+    .serial_clock(\gpio_clock_1[11] ),
+    .serial_clock_out(\gpio_clock_1[12] ),
+    .serial_data_in(\gpio_serial_link_1[11] ),
+    .serial_data_out(\gpio_serial_link_1[12] ),
+    .serial_load(\gpio_load_1[11] ),
+    .serial_load_out(\gpio_load_1[12] ),
+    .user_gpio_in(\user_io_in[12] ),
+    .user_gpio_oeb(\user_io_oeb[12] ),
+    .user_gpio_out(\user_io_out[12] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[5]  (
+    .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169]  }),
+    .mgmt_gpio_in(\mgmt_io_in[13] ),
+    .mgmt_gpio_oeb(\one_loop1[13] ),
+    .mgmt_gpio_out(\mgmt_io_in[13] ),
+    .one(\one_loop1[13] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[13] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[13] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[13] ),
+    .pad_gpio_dm({ \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[13] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[13] ),
+    .pad_gpio_in(\mprj_io_in[13] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[13] ),
+    .pad_gpio_out(\mprj_io_out[13] ),
+    .pad_gpio_outenb(\mprj_io_oeb[13] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[13] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[13] ),
+    .resetn(\gpio_resetn_1[12] ),
+    .resetn_out(\gpio_resetn_1[13] ),
+    .serial_clock(\gpio_clock_1[12] ),
+    .serial_clock_out(\gpio_clock_1[13] ),
+    .serial_data_in(\gpio_serial_link_1[12] ),
+    .serial_data_out(\gpio_serial_link_1[13] ),
+    .serial_load(\gpio_load_1[12] ),
+    .serial_load_out(\gpio_load_1[13] ),
+    .user_gpio_in(\user_io_in[13] ),
+    .user_gpio_oeb(\user_io_oeb[13] ),
+    .user_gpio_out(\user_io_out[13] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[6]  (
+    .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182]  }),
+    .mgmt_gpio_in(\mgmt_io_in[14] ),
+    .mgmt_gpio_oeb(\one_loop1[14] ),
+    .mgmt_gpio_out(\mgmt_io_in[14] ),
+    .one(\one_loop1[14] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[14] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[14] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[14] ),
+    .pad_gpio_dm({ \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[14] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[14] ),
+    .pad_gpio_in(\mprj_io_in[14] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[14] ),
+    .pad_gpio_out(\mprj_io_out[14] ),
+    .pad_gpio_outenb(\mprj_io_oeb[14] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[14] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[14] ),
+    .resetn(\gpio_resetn_1[13] ),
+    .resetn_out(\gpio_resetn_1[14] ),
+    .serial_clock(\gpio_clock_1[13] ),
+    .serial_clock_out(\gpio_clock_1[14] ),
+    .serial_data_in(\gpio_serial_link_1[13] ),
+    .serial_data_out(\gpio_serial_link_1[14] ),
+    .serial_load(\gpio_load_1[13] ),
+    .serial_load_out(\gpio_load_1[14] ),
+    .user_gpio_in(\user_io_in[14] ),
+    .user_gpio_oeb(\user_io_oeb[14] ),
+    .user_gpio_out(\user_io_out[14] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[7]  (
+    .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195]  }),
+    .mgmt_gpio_in(\mgmt_io_in[15] ),
+    .mgmt_gpio_oeb(\one_loop1[15] ),
+    .mgmt_gpio_out(\mgmt_io_in[15] ),
+    .one(\one_loop1[15] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[15] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[15] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[15] ),
+    .pad_gpio_dm({ \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[15] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[15] ),
+    .pad_gpio_in(\mprj_io_in[15] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[15] ),
+    .pad_gpio_out(\mprj_io_out[15] ),
+    .pad_gpio_outenb(\mprj_io_oeb[15] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[15] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[15] ),
+    .resetn(\gpio_resetn_1[14] ),
+    .resetn_out(\gpio_resetn_1[15] ),
+    .serial_clock(\gpio_clock_1[14] ),
+    .serial_clock_out(\gpio_clock_1[15] ),
+    .serial_data_in(\gpio_serial_link_1[14] ),
+    .serial_data_out(\gpio_serial_link_1[15] ),
+    .serial_load(\gpio_load_1[14] ),
+    .serial_load_out(\gpio_load_1[15] ),
+    .user_gpio_in(\user_io_in[15] ),
+    .user_gpio_oeb(\user_io_oeb[15] ),
+    .user_gpio_out(\user_io_out[15] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[8]  (
+    .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208]  }),
+    .mgmt_gpio_in(\mgmt_io_in[16] ),
+    .mgmt_gpio_oeb(\one_loop1[16] ),
+    .mgmt_gpio_out(\mgmt_io_in[16] ),
+    .one(\one_loop1[16] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[16] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[16] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[16] ),
+    .pad_gpio_dm({ \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[16] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[16] ),
+    .pad_gpio_in(\mprj_io_in[16] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[16] ),
+    .pad_gpio_out(\mprj_io_out[16] ),
+    .pad_gpio_outenb(\mprj_io_oeb[16] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[16] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[16] ),
+    .resetn(\gpio_resetn_1[15] ),
+    .resetn_out(\gpio_resetn_1[16] ),
+    .serial_clock(\gpio_clock_1[15] ),
+    .serial_clock_out(\gpio_clock_1[16] ),
+    .serial_data_in(\gpio_serial_link_1[15] ),
+    .serial_data_out(\gpio_serial_link_1[16] ),
+    .serial_load(\gpio_load_1[15] ),
+    .serial_load_out(\gpio_load_1[16] ),
+    .user_gpio_in(\user_io_in[16] ),
+    .user_gpio_oeb(\user_io_oeb[16] ),
+    .user_gpio_out(\user_io_out[16] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[9]  (
+    .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221]  }),
+    .mgmt_gpio_in(\mgmt_io_in[17] ),
+    .mgmt_gpio_oeb(\one_loop1[17] ),
+    .mgmt_gpio_out(\mgmt_io_in[17] ),
+    .one(\one_loop1[17] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[17] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[17] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[17] ),
+    .pad_gpio_dm({ \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[17] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[17] ),
+    .pad_gpio_in(\mprj_io_in[17] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[17] ),
+    .pad_gpio_out(\mprj_io_out[17] ),
+    .pad_gpio_outenb(\mprj_io_oeb[17] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[17] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[17] ),
+    .resetn(\gpio_resetn_1[16] ),
+    .resetn_out(\gpio_resetn_1[17] ),
+    .serial_clock(\gpio_clock_1[16] ),
+    .serial_clock_out(\gpio_clock_1[17] ),
+    .serial_data_in(\gpio_serial_link_1[16] ),
+    .serial_data_out(\gpio_serial_link_1[17] ),
+    .serial_load(\gpio_load_1[16] ),
+    .serial_load_out(\gpio_load_1[17] ),
+    .user_gpio_in(\user_io_in[17] ),
+    .user_gpio_oeb(\user_io_oeb[17] ),
+    .user_gpio_out(\user_io_out[17] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[0]  (
+    .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26]  }),
+    .mgmt_gpio_in(\mgmt_io_in[2] ),
+    .mgmt_gpio_oeb(\one_loop1[2] ),
+    .mgmt_gpio_out(\mgmt_io_in[2] ),
+    .one(\one_loop1[2] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[2] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[2] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[2] ),
+    .pad_gpio_dm({ \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[2] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[2] ),
+    .pad_gpio_in(\mprj_io_in[2] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[2] ),
+    .pad_gpio_out(\mprj_io_out[2] ),
+    .pad_gpio_outenb(\mprj_io_oeb[2] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[2] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[2] ),
+    .resetn(\gpio_resetn_1[1] ),
+    .resetn_out(\gpio_resetn_1[2] ),
+    .serial_clock(\gpio_clock_1[1] ),
+    .serial_clock_out(\gpio_clock_1[2] ),
+    .serial_data_in(\gpio_serial_link_1[1] ),
+    .serial_data_out(\gpio_serial_link_1[2] ),
+    .serial_load(\gpio_load_1[1] ),
+    .serial_load_out(\gpio_load_1[2] ),
+    .user_gpio_in(\user_io_in[2] ),
+    .user_gpio_oeb(\user_io_oeb[2] ),
+    .user_gpio_out(\user_io_out[2] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[1]  (
+    .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39]  }),
+    .mgmt_gpio_in(\mgmt_io_in[3] ),
+    .mgmt_gpio_oeb(\one_loop1[3] ),
+    .mgmt_gpio_out(\mgmt_io_in[3] ),
+    .one(\one_loop1[3] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[3] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[3] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[3] ),
+    .pad_gpio_dm({ \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[3] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[3] ),
+    .pad_gpio_in(\mprj_io_in[3] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[3] ),
+    .pad_gpio_out(\mprj_io_out[3] ),
+    .pad_gpio_outenb(\mprj_io_oeb[3] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[3] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[3] ),
+    .resetn(\gpio_resetn_1[2] ),
+    .resetn_out(\gpio_resetn_1[3] ),
+    .serial_clock(\gpio_clock_1[2] ),
+    .serial_clock_out(\gpio_clock_1[3] ),
+    .serial_data_in(\gpio_serial_link_1[2] ),
+    .serial_data_out(\gpio_serial_link_1[3] ),
+    .serial_load(\gpio_load_1[2] ),
+    .serial_load_out(\gpio_load_1[3] ),
+    .user_gpio_in(\user_io_in[3] ),
+    .user_gpio_oeb(\user_io_oeb[3] ),
+    .user_gpio_out(\user_io_out[3] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[2]  (
+    .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52]  }),
+    .mgmt_gpio_in(\mgmt_io_in[4] ),
+    .mgmt_gpio_oeb(\one_loop1[4] ),
+    .mgmt_gpio_out(\mgmt_io_in[4] ),
+    .one(\one_loop1[4] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[4] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[4] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[4] ),
+    .pad_gpio_dm({ \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[4] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[4] ),
+    .pad_gpio_in(\mprj_io_in[4] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[4] ),
+    .pad_gpio_out(\mprj_io_out[4] ),
+    .pad_gpio_outenb(\mprj_io_oeb[4] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[4] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[4] ),
+    .resetn(\gpio_resetn_1[3] ),
+    .resetn_out(\gpio_resetn_1[4] ),
+    .serial_clock(\gpio_clock_1[3] ),
+    .serial_clock_out(\gpio_clock_1[4] ),
+    .serial_data_in(\gpio_serial_link_1[3] ),
+    .serial_data_out(\gpio_serial_link_1[4] ),
+    .serial_load(\gpio_load_1[3] ),
+    .serial_load_out(\gpio_load_1[4] ),
+    .user_gpio_in(\user_io_in[4] ),
+    .user_gpio_oeb(\user_io_oeb[4] ),
+    .user_gpio_out(\user_io_out[4] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[3]  (
+    .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65]  }),
+    .mgmt_gpio_in(\mgmt_io_in[5] ),
+    .mgmt_gpio_oeb(\one_loop1[5] ),
+    .mgmt_gpio_out(\mgmt_io_in[5] ),
+    .one(\one_loop1[5] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[5] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[5] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[5] ),
+    .pad_gpio_dm({ \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[5] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[5] ),
+    .pad_gpio_in(\mprj_io_in[5] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[5] ),
+    .pad_gpio_out(\mprj_io_out[5] ),
+    .pad_gpio_outenb(\mprj_io_oeb[5] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[5] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[5] ),
+    .resetn(\gpio_resetn_1[4] ),
+    .resetn_out(\gpio_resetn_1[5] ),
+    .serial_clock(\gpio_clock_1[4] ),
+    .serial_clock_out(\gpio_clock_1[5] ),
+    .serial_data_in(\gpio_serial_link_1[4] ),
+    .serial_data_out(\gpio_serial_link_1[5] ),
+    .serial_load(\gpio_load_1[4] ),
+    .serial_load_out(\gpio_load_1[5] ),
+    .user_gpio_in(\user_io_in[5] ),
+    .user_gpio_oeb(\user_io_oeb[5] ),
+    .user_gpio_out(\user_io_out[5] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[4]  (
+    .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78]  }),
+    .mgmt_gpio_in(\mgmt_io_in[6] ),
+    .mgmt_gpio_oeb(\one_loop1[6] ),
+    .mgmt_gpio_out(\mgmt_io_in[6] ),
+    .one(\one_loop1[6] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[6] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[6] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[6] ),
+    .pad_gpio_dm({ \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[6] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[6] ),
+    .pad_gpio_in(\mprj_io_in[6] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[6] ),
+    .pad_gpio_out(\mprj_io_out[6] ),
+    .pad_gpio_outenb(\mprj_io_oeb[6] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[6] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[6] ),
+    .resetn(\gpio_resetn_1[5] ),
+    .resetn_out(\gpio_resetn_1[6] ),
+    .serial_clock(\gpio_clock_1[5] ),
+    .serial_clock_out(\gpio_clock_1[6] ),
+    .serial_data_in(\gpio_serial_link_1[5] ),
+    .serial_data_out(\gpio_serial_link_1[6] ),
+    .serial_load(\gpio_load_1[5] ),
+    .serial_load_out(\gpio_load_1[6] ),
+    .user_gpio_in(\user_io_in[6] ),
+    .user_gpio_oeb(\user_io_oeb[6] ),
+    .user_gpio_out(\user_io_out[6] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[5]  (
+    .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91]  }),
+    .mgmt_gpio_in(\mgmt_io_in[7] ),
+    .mgmt_gpio_oeb(\one_loop1[7] ),
+    .mgmt_gpio_out(\mgmt_io_in[7] ),
+    .one(\one_loop1[7] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[7] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[7] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[7] ),
+    .pad_gpio_dm({ \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[7] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[7] ),
+    .pad_gpio_in(\mprj_io_in[7] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[7] ),
+    .pad_gpio_out(\mprj_io_out[7] ),
+    .pad_gpio_outenb(\mprj_io_oeb[7] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[7] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[7] ),
+    .resetn(\gpio_resetn_1[6] ),
+    .resetn_out(\gpio_resetn_1[7] ),
+    .serial_clock(\gpio_clock_1[6] ),
+    .serial_clock_out(\gpio_clock_1[7] ),
+    .serial_data_in(\gpio_serial_link_1[6] ),
+    .serial_data_out(\gpio_serial_link_1[7] ),
+    .serial_load(\gpio_load_1[6] ),
+    .serial_load_out(\gpio_load_1[7] ),
+    .user_gpio_in(\user_io_in[7] ),
+    .user_gpio_oeb(\user_io_oeb[7] ),
+    .user_gpio_out(\user_io_out[7] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[0]  (
+    .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247]  }),
+    .mgmt_gpio_in(\mgmt_io_in[19] ),
+    .mgmt_gpio_oeb(\one_loop2[0] ),
+    .mgmt_gpio_out(\mgmt_io_in[19] ),
+    .one(\one_loop2[0] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[19] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[19] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[19] ),
+    .pad_gpio_dm({ \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[19] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[19] ),
+    .pad_gpio_in(\mprj_io_in[19] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[19] ),
+    .pad_gpio_out(\mprj_io_out[19] ),
+    .pad_gpio_outenb(\mprj_io_oeb[19] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[19] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[19] ),
+    .resetn(\gpio_resetn_2[1] ),
+    .resetn_out(\gpio_resetn_2[0] ),
+    .serial_clock(\gpio_clock_2[1] ),
+    .serial_clock_out(\gpio_clock_2[0] ),
+    .serial_data_in(\gpio_serial_link_2[1] ),
+    .serial_data_out(\gpio_serial_link_2[0] ),
+    .serial_load(\gpio_load_2[1] ),
+    .serial_load_out(\gpio_load_2[0] ),
+    .user_gpio_in(\user_io_in[19] ),
+    .user_gpio_oeb(\user_io_oeb[19] ),
+    .user_gpio_out(\user_io_out[19] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[10]  (
+    .gpio_defaults({ \gpio_defaults[389] , \gpio_defaults[388] , \gpio_defaults[387] , \gpio_defaults[386] , \gpio_defaults[385] , \gpio_defaults[384] , \gpio_defaults[383] , \gpio_defaults[382] , \gpio_defaults[381] , \gpio_defaults[380] , \gpio_defaults[379] , \gpio_defaults[378] , \gpio_defaults[377]  }),
+    .mgmt_gpio_in(\mgmt_io_in[29] ),
+    .mgmt_gpio_oeb(\one_loop2[10] ),
+    .mgmt_gpio_out(\mgmt_io_in[29] ),
+    .one(\one_loop2[10] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[29] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[29] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[29] ),
+    .pad_gpio_dm({ \mprj_io_dm[89] , \mprj_io_dm[88] , \mprj_io_dm[87]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[29] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[29] ),
+    .pad_gpio_in(\mprj_io_in[29] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[29] ),
+    .pad_gpio_out(\mprj_io_out[29] ),
+    .pad_gpio_outenb(\mprj_io_oeb[29] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[29] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[29] ),
+    .resetn(\gpio_resetn_2[11] ),
+    .resetn_out(\gpio_resetn_2[10] ),
+    .serial_clock(\gpio_clock_2[11] ),
+    .serial_clock_out(\gpio_clock_2[10] ),
+    .serial_data_in(\gpio_serial_link_2[11] ),
+    .serial_data_out(\gpio_serial_link_2[10] ),
+    .serial_load(\gpio_load_2[11] ),
+    .serial_load_out(\gpio_load_2[10] ),
+    .user_gpio_in(\user_io_in[29] ),
+    .user_gpio_oeb(\user_io_oeb[29] ),
+    .user_gpio_out(\user_io_out[29] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[11]  (
+    .gpio_defaults({ \gpio_defaults[402] , \gpio_defaults[401] , \gpio_defaults[400] , \gpio_defaults[399] , \gpio_defaults[398] , \gpio_defaults[397] , \gpio_defaults[396] , \gpio_defaults[395] , \gpio_defaults[394] , \gpio_defaults[393] , \gpio_defaults[392] , \gpio_defaults[391] , \gpio_defaults[390]  }),
+    .mgmt_gpio_in(\mgmt_io_in[30] ),
+    .mgmt_gpio_oeb(\one_loop2[11] ),
+    .mgmt_gpio_out(\mgmt_io_in[30] ),
+    .one(\one_loop2[11] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[30] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[30] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[30] ),
+    .pad_gpio_dm({ \mprj_io_dm[92] , \mprj_io_dm[91] , \mprj_io_dm[90]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[30] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[30] ),
+    .pad_gpio_in(\mprj_io_in[30] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[30] ),
+    .pad_gpio_out(\mprj_io_out[30] ),
+    .pad_gpio_outenb(\mprj_io_oeb[30] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[30] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[30] ),
+    .resetn(\gpio_resetn_2[12] ),
+    .resetn_out(\gpio_resetn_2[11] ),
+    .serial_clock(\gpio_clock_2[12] ),
+    .serial_clock_out(\gpio_clock_2[11] ),
+    .serial_data_in(\gpio_serial_link_2[12] ),
+    .serial_data_out(\gpio_serial_link_2[11] ),
+    .serial_load(\gpio_load_2[12] ),
+    .serial_load_out(\gpio_load_2[11] ),
+    .user_gpio_in(\user_io_in[30] ),
+    .user_gpio_oeb(\user_io_oeb[30] ),
+    .user_gpio_out(\user_io_out[30] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[12]  (
+    .gpio_defaults({ \gpio_defaults[415] , \gpio_defaults[414] , \gpio_defaults[413] , \gpio_defaults[412] , \gpio_defaults[411] , \gpio_defaults[410] , \gpio_defaults[409] , \gpio_defaults[408] , \gpio_defaults[407] , \gpio_defaults[406] , \gpio_defaults[405] , \gpio_defaults[404] , \gpio_defaults[403]  }),
+    .mgmt_gpio_in(\mgmt_io_in[31] ),
+    .mgmt_gpio_oeb(\one_loop2[12] ),
+    .mgmt_gpio_out(\mgmt_io_in[31] ),
+    .one(\one_loop2[12] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[31] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[31] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[31] ),
+    .pad_gpio_dm({ \mprj_io_dm[95] , \mprj_io_dm[94] , \mprj_io_dm[93]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[31] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[31] ),
+    .pad_gpio_in(\mprj_io_in[31] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[31] ),
+    .pad_gpio_out(\mprj_io_out[31] ),
+    .pad_gpio_outenb(\mprj_io_oeb[31] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[31] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[31] ),
+    .resetn(\gpio_resetn_2[13] ),
+    .resetn_out(\gpio_resetn_2[12] ),
+    .serial_clock(\gpio_clock_2[13] ),
+    .serial_clock_out(\gpio_clock_2[12] ),
+    .serial_data_in(\gpio_serial_link_2[13] ),
+    .serial_data_out(\gpio_serial_link_2[12] ),
+    .serial_load(\gpio_load_2[13] ),
+    .serial_load_out(\gpio_load_2[12] ),
+    .user_gpio_in(\user_io_in[31] ),
+    .user_gpio_oeb(\user_io_oeb[31] ),
+    .user_gpio_out(\user_io_out[31] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[13]  (
+    .gpio_defaults({ \gpio_defaults[428] , \gpio_defaults[427] , \gpio_defaults[426] , \gpio_defaults[425] , \gpio_defaults[424] , \gpio_defaults[423] , \gpio_defaults[422] , \gpio_defaults[421] , \gpio_defaults[420] , \gpio_defaults[419] , \gpio_defaults[418] , \gpio_defaults[417] , \gpio_defaults[416]  }),
+    .mgmt_gpio_in(\mgmt_io_in[32] ),
+    .mgmt_gpio_oeb(\one_loop2[13] ),
+    .mgmt_gpio_out(\mgmt_io_in[32] ),
+    .one(\one_loop2[13] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[32] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[32] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[32] ),
+    .pad_gpio_dm({ \mprj_io_dm[98] , \mprj_io_dm[97] , \mprj_io_dm[96]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[32] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[32] ),
+    .pad_gpio_in(\mprj_io_in[32] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[32] ),
+    .pad_gpio_out(\mprj_io_out[32] ),
+    .pad_gpio_outenb(\mprj_io_oeb[32] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[32] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[32] ),
+    .resetn(\gpio_resetn_2[14] ),
+    .resetn_out(\gpio_resetn_2[13] ),
+    .serial_clock(\gpio_clock_2[14] ),
+    .serial_clock_out(\gpio_clock_2[13] ),
+    .serial_data_in(\gpio_serial_link_2[14] ),
+    .serial_data_out(\gpio_serial_link_2[13] ),
+    .serial_load(\gpio_load_2[14] ),
+    .serial_load_out(\gpio_load_2[13] ),
+    .user_gpio_in(\user_io_in[32] ),
+    .user_gpio_oeb(\user_io_oeb[32] ),
+    .user_gpio_out(\user_io_out[32] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[14]  (
+    .gpio_defaults({ \gpio_defaults[441] , \gpio_defaults[440] , \gpio_defaults[439] , \gpio_defaults[438] , \gpio_defaults[437] , \gpio_defaults[436] , \gpio_defaults[435] , \gpio_defaults[434] , \gpio_defaults[433] , \gpio_defaults[432] , \gpio_defaults[431] , \gpio_defaults[430] , \gpio_defaults[429]  }),
+    .mgmt_gpio_in(\mgmt_io_in[33] ),
+    .mgmt_gpio_oeb(\one_loop2[14] ),
+    .mgmt_gpio_out(\mgmt_io_in[33] ),
+    .one(\one_loop2[14] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[33] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[33] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[33] ),
+    .pad_gpio_dm({ \mprj_io_dm[101] , \mprj_io_dm[100] , \mprj_io_dm[99]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[33] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[33] ),
+    .pad_gpio_in(\mprj_io_in[33] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[33] ),
+    .pad_gpio_out(\mprj_io_out[33] ),
+    .pad_gpio_outenb(\mprj_io_oeb[33] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[33] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[33] ),
+    .resetn(\gpio_resetn_2[15] ),
+    .resetn_out(\gpio_resetn_2[14] ),
+    .serial_clock(\gpio_clock_2[15] ),
+    .serial_clock_out(\gpio_clock_2[14] ),
+    .serial_data_in(\gpio_serial_link_2[15] ),
+    .serial_data_out(\gpio_serial_link_2[14] ),
+    .serial_load(\gpio_load_2[15] ),
+    .serial_load_out(\gpio_load_2[14] ),
+    .user_gpio_in(\user_io_in[33] ),
+    .user_gpio_oeb(\user_io_oeb[33] ),
+    .user_gpio_out(\user_io_out[33] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[15]  (
+    .gpio_defaults({ \gpio_defaults[454] , \gpio_defaults[453] , \gpio_defaults[452] , \gpio_defaults[451] , \gpio_defaults[450] , \gpio_defaults[449] , \gpio_defaults[448] , \gpio_defaults[447] , \gpio_defaults[446] , \gpio_defaults[445] , \gpio_defaults[444] , \gpio_defaults[443] , \gpio_defaults[442]  }),
+    .mgmt_gpio_in(\mgmt_io_in[34] ),
+    .mgmt_gpio_oeb(\one_loop2[15] ),
+    .mgmt_gpio_out(\mgmt_io_in[34] ),
+    .one(\one_loop2[15] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[34] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[34] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[34] ),
+    .pad_gpio_dm({ \mprj_io_dm[104] , \mprj_io_dm[103] , \mprj_io_dm[102]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[34] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[34] ),
+    .pad_gpio_in(\mprj_io_in[34] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[34] ),
+    .pad_gpio_out(\mprj_io_out[34] ),
+    .pad_gpio_outenb(\mprj_io_oeb[34] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[34] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[34] ),
+    .resetn(\gpio_resetn_2[16] ),
+    .resetn_out(\gpio_resetn_2[15] ),
+    .serial_clock(\gpio_clock_2[16] ),
+    .serial_clock_out(\gpio_clock_2[15] ),
+    .serial_data_in(\gpio_serial_link_2[16] ),
+    .serial_data_out(\gpio_serial_link_2[15] ),
+    .serial_load(\gpio_load_2[16] ),
+    .serial_load_out(\gpio_load_2[15] ),
+    .user_gpio_in(\user_io_in[34] ),
+    .user_gpio_oeb(\user_io_oeb[34] ),
+    .user_gpio_out(\user_io_out[34] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[1]  (
+    .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260]  }),
+    .mgmt_gpio_in(\mgmt_io_in[20] ),
+    .mgmt_gpio_oeb(\one_loop2[1] ),
+    .mgmt_gpio_out(\mgmt_io_in[20] ),
+    .one(\one_loop2[1] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[20] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[20] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[20] ),
+    .pad_gpio_dm({ \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[20] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[20] ),
+    .pad_gpio_in(\mprj_io_in[20] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[20] ),
+    .pad_gpio_out(\mprj_io_out[20] ),
+    .pad_gpio_outenb(\mprj_io_oeb[20] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[20] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[20] ),
+    .resetn(\gpio_resetn_2[2] ),
+    .resetn_out(\gpio_resetn_2[1] ),
+    .serial_clock(\gpio_clock_2[2] ),
+    .serial_clock_out(\gpio_clock_2[1] ),
+    .serial_data_in(\gpio_serial_link_2[2] ),
+    .serial_data_out(\gpio_serial_link_2[1] ),
+    .serial_load(\gpio_load_2[2] ),
+    .serial_load_out(\gpio_load_2[1] ),
+    .user_gpio_in(\user_io_in[20] ),
+    .user_gpio_oeb(\user_io_oeb[20] ),
+    .user_gpio_out(\user_io_out[20] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[2]  (
+    .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273]  }),
+    .mgmt_gpio_in(\mgmt_io_in[21] ),
+    .mgmt_gpio_oeb(\one_loop2[2] ),
+    .mgmt_gpio_out(\mgmt_io_in[21] ),
+    .one(\one_loop2[2] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[21] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[21] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[21] ),
+    .pad_gpio_dm({ \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[21] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[21] ),
+    .pad_gpio_in(\mprj_io_in[21] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[21] ),
+    .pad_gpio_out(\mprj_io_out[21] ),
+    .pad_gpio_outenb(\mprj_io_oeb[21] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[21] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[21] ),
+    .resetn(\gpio_resetn_2[3] ),
+    .resetn_out(\gpio_resetn_2[2] ),
+    .serial_clock(\gpio_clock_2[3] ),
+    .serial_clock_out(\gpio_clock_2[2] ),
+    .serial_data_in(\gpio_serial_link_2[3] ),
+    .serial_data_out(\gpio_serial_link_2[2] ),
+    .serial_load(\gpio_load_2[3] ),
+    .serial_load_out(\gpio_load_2[2] ),
+    .user_gpio_in(\user_io_in[21] ),
+    .user_gpio_oeb(\user_io_oeb[21] ),
+    .user_gpio_out(\user_io_out[21] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[3]  (
+    .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286]  }),
+    .mgmt_gpio_in(\mgmt_io_in[22] ),
+    .mgmt_gpio_oeb(\one_loop2[3] ),
+    .mgmt_gpio_out(\mgmt_io_in[22] ),
+    .one(\one_loop2[3] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[22] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[22] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[22] ),
+    .pad_gpio_dm({ \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[22] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[22] ),
+    .pad_gpio_in(\mprj_io_in[22] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[22] ),
+    .pad_gpio_out(\mprj_io_out[22] ),
+    .pad_gpio_outenb(\mprj_io_oeb[22] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[22] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[22] ),
+    .resetn(\gpio_resetn_2[4] ),
+    .resetn_out(\gpio_resetn_2[3] ),
+    .serial_clock(\gpio_clock_2[4] ),
+    .serial_clock_out(\gpio_clock_2[3] ),
+    .serial_data_in(\gpio_serial_link_2[4] ),
+    .serial_data_out(\gpio_serial_link_2[3] ),
+    .serial_load(\gpio_load_2[4] ),
+    .serial_load_out(\gpio_load_2[3] ),
+    .user_gpio_in(\user_io_in[22] ),
+    .user_gpio_oeb(\user_io_oeb[22] ),
+    .user_gpio_out(\user_io_out[22] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[4]  (
+    .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299]  }),
+    .mgmt_gpio_in(\mgmt_io_in[23] ),
+    .mgmt_gpio_oeb(\one_loop2[4] ),
+    .mgmt_gpio_out(\mgmt_io_in[23] ),
+    .one(\one_loop2[4] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[23] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[23] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[23] ),
+    .pad_gpio_dm({ \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[23] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[23] ),
+    .pad_gpio_in(\mprj_io_in[23] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[23] ),
+    .pad_gpio_out(\mprj_io_out[23] ),
+    .pad_gpio_outenb(\mprj_io_oeb[23] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[23] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[23] ),
+    .resetn(\gpio_resetn_2[5] ),
+    .resetn_out(\gpio_resetn_2[4] ),
+    .serial_clock(\gpio_clock_2[5] ),
+    .serial_clock_out(\gpio_clock_2[4] ),
+    .serial_data_in(\gpio_serial_link_2[5] ),
+    .serial_data_out(\gpio_serial_link_2[4] ),
+    .serial_load(\gpio_load_2[5] ),
+    .serial_load_out(\gpio_load_2[4] ),
+    .user_gpio_in(\user_io_in[23] ),
+    .user_gpio_oeb(\user_io_oeb[23] ),
+    .user_gpio_out(\user_io_out[23] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[5]  (
+    .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312]  }),
+    .mgmt_gpio_in(\mgmt_io_in[24] ),
+    .mgmt_gpio_oeb(\one_loop2[5] ),
+    .mgmt_gpio_out(\mgmt_io_in[24] ),
+    .one(\one_loop2[5] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[24] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[24] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[24] ),
+    .pad_gpio_dm({ \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[24] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[24] ),
+    .pad_gpio_in(\mprj_io_in[24] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[24] ),
+    .pad_gpio_out(\mprj_io_out[24] ),
+    .pad_gpio_outenb(\mprj_io_oeb[24] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[24] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[24] ),
+    .resetn(\gpio_resetn_2[6] ),
+    .resetn_out(\gpio_resetn_2[5] ),
+    .serial_clock(\gpio_clock_2[6] ),
+    .serial_clock_out(\gpio_clock_2[5] ),
+    .serial_data_in(\gpio_serial_link_2[6] ),
+    .serial_data_out(\gpio_serial_link_2[5] ),
+    .serial_load(\gpio_load_2[6] ),
+    .serial_load_out(\gpio_load_2[5] ),
+    .user_gpio_in(\user_io_in[24] ),
+    .user_gpio_oeb(\user_io_oeb[24] ),
+    .user_gpio_out(\user_io_out[24] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[6]  (
+    .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325]  }),
+    .mgmt_gpio_in(\mgmt_io_in[25] ),
+    .mgmt_gpio_oeb(\one_loop2[6] ),
+    .mgmt_gpio_out(\mgmt_io_in[25] ),
+    .one(\one_loop2[6] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[25] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[25] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[25] ),
+    .pad_gpio_dm({ \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[25] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[25] ),
+    .pad_gpio_in(\mprj_io_in[25] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[25] ),
+    .pad_gpio_out(\mprj_io_out[25] ),
+    .pad_gpio_outenb(\mprj_io_oeb[25] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[25] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[25] ),
+    .resetn(\gpio_resetn_2[7] ),
+    .resetn_out(\gpio_resetn_2[6] ),
+    .serial_clock(\gpio_clock_2[7] ),
+    .serial_clock_out(\gpio_clock_2[6] ),
+    .serial_data_in(\gpio_serial_link_2[7] ),
+    .serial_data_out(\gpio_serial_link_2[6] ),
+    .serial_load(\gpio_load_2[7] ),
+    .serial_load_out(\gpio_load_2[6] ),
+    .user_gpio_in(\user_io_in[25] ),
+    .user_gpio_oeb(\user_io_oeb[25] ),
+    .user_gpio_out(\user_io_out[25] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[7]  (
+    .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338]  }),
+    .mgmt_gpio_in(\mgmt_io_in[26] ),
+    .mgmt_gpio_oeb(\one_loop2[7] ),
+    .mgmt_gpio_out(\mgmt_io_in[26] ),
+    .one(\one_loop2[7] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[26] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[26] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[26] ),
+    .pad_gpio_dm({ \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[26] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[26] ),
+    .pad_gpio_in(\mprj_io_in[26] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[26] ),
+    .pad_gpio_out(\mprj_io_out[26] ),
+    .pad_gpio_outenb(\mprj_io_oeb[26] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[26] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[26] ),
+    .resetn(\gpio_resetn_2[8] ),
+    .resetn_out(\gpio_resetn_2[7] ),
+    .serial_clock(\gpio_clock_2[8] ),
+    .serial_clock_out(\gpio_clock_2[7] ),
+    .serial_data_in(\gpio_serial_link_2[8] ),
+    .serial_data_out(\gpio_serial_link_2[7] ),
+    .serial_load(\gpio_load_2[8] ),
+    .serial_load_out(\gpio_load_2[7] ),
+    .user_gpio_in(\user_io_in[26] ),
+    .user_gpio_oeb(\user_io_oeb[26] ),
+    .user_gpio_out(\user_io_out[26] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[8]  (
+    .gpio_defaults({ \gpio_defaults[363] , \gpio_defaults[362] , \gpio_defaults[361] , \gpio_defaults[360] , \gpio_defaults[359] , \gpio_defaults[358] , \gpio_defaults[357] , \gpio_defaults[356] , \gpio_defaults[355] , \gpio_defaults[354] , \gpio_defaults[353] , \gpio_defaults[352] , \gpio_defaults[351]  }),
+    .mgmt_gpio_in(\mgmt_io_in[27] ),
+    .mgmt_gpio_oeb(\one_loop2[8] ),
+    .mgmt_gpio_out(\mgmt_io_in[27] ),
+    .one(\one_loop2[8] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[27] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[27] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[27] ),
+    .pad_gpio_dm({ \mprj_io_dm[83] , \mprj_io_dm[82] , \mprj_io_dm[81]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[27] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[27] ),
+    .pad_gpio_in(\mprj_io_in[27] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[27] ),
+    .pad_gpio_out(\mprj_io_out[27] ),
+    .pad_gpio_outenb(\mprj_io_oeb[27] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[27] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[27] ),
+    .resetn(\gpio_resetn_2[9] ),
+    .resetn_out(\gpio_resetn_2[8] ),
+    .serial_clock(\gpio_clock_2[9] ),
+    .serial_clock_out(\gpio_clock_2[8] ),
+    .serial_data_in(\gpio_serial_link_2[9] ),
+    .serial_data_out(\gpio_serial_link_2[8] ),
+    .serial_load(\gpio_load_2[9] ),
+    .serial_load_out(\gpio_load_2[8] ),
+    .user_gpio_in(\user_io_in[27] ),
+    .user_gpio_oeb(\user_io_oeb[27] ),
+    .user_gpio_out(\user_io_out[27] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[9]  (
+    .gpio_defaults({ \gpio_defaults[376] , \gpio_defaults[375] , \gpio_defaults[374] , \gpio_defaults[373] , \gpio_defaults[372] , \gpio_defaults[371] , \gpio_defaults[370] , \gpio_defaults[369] , \gpio_defaults[368] , \gpio_defaults[367] , \gpio_defaults[366] , \gpio_defaults[365] , \gpio_defaults[364]  }),
+    .mgmt_gpio_in(\mgmt_io_in[28] ),
+    .mgmt_gpio_oeb(\one_loop2[9] ),
+    .mgmt_gpio_out(\mgmt_io_in[28] ),
+    .one(\one_loop2[9] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[28] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[28] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[28] ),
+    .pad_gpio_dm({ \mprj_io_dm[86] , \mprj_io_dm[85] , \mprj_io_dm[84]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[28] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[28] ),
+    .pad_gpio_in(\mprj_io_in[28] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[28] ),
+    .pad_gpio_out(\mprj_io_out[28] ),
+    .pad_gpio_outenb(\mprj_io_oeb[28] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[28] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[28] ),
+    .resetn(\gpio_resetn_2[10] ),
+    .resetn_out(\gpio_resetn_2[9] ),
+    .serial_clock(\gpio_clock_2[10] ),
+    .serial_clock_out(\gpio_clock_2[9] ),
+    .serial_data_in(\gpio_serial_link_2[10] ),
+    .serial_data_out(\gpio_serial_link_2[9] ),
+    .serial_load(\gpio_load_2[10] ),
+    .serial_load_out(\gpio_load_2[9] ),
+    .user_gpio_in(\user_io_in[28] ),
+    .user_gpio_oeb(\user_io_oeb[28] ),
+    .user_gpio_out(\user_io_out[28] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  housekeeping housekeeping (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .debug_in(debug_in),
+    .debug_mode(debug_mode),
+    .debug_oeb(debug_oeb),
+    .debug_out(debug_out),
+    .irq({ \irq_spi[2] , \irq_spi[1] , \irq_spi[0]  }),
+    .mask_rev_in({ \mask_rev[31] , \mask_rev[30] , \mask_rev[29] , \mask_rev[28] , \mask_rev[27] , \mask_rev[26] , \mask_rev[25] , \mask_rev[24] , \mask_rev[23] , \mask_rev[22] , \mask_rev[21] , \mask_rev[20] , \mask_rev[19] , \mask_rev[18] , \mask_rev[17] , \mask_rev[16] , \mask_rev[15] , \mask_rev[14] , \mask_rev[13] , \mask_rev[12] , \mask_rev[11] , \mask_rev[10] , \mask_rev[9] , \mask_rev[8] , \mask_rev[7] , \mask_rev[6] , \mask_rev[5] , \mask_rev[4] , \mask_rev[3] , \mask_rev[2] , \mask_rev[1] , \mask_rev[0]  }),
+    .mgmt_gpio_in({ \mgmt_io_in[37] , \mgmt_io_in[36] , \mgmt_io_in[35] , \mgmt_io_in[34] , \mgmt_io_in[33] , \mgmt_io_in[32] , \mgmt_io_in[31] , \mgmt_io_in[30] , \mgmt_io_in[29] , \mgmt_io_in[28] , \mgmt_io_in[27] , \mgmt_io_in[26] , \mgmt_io_in[25] , \mgmt_io_in[24] , \mgmt_io_in[23] , \mgmt_io_in[22] , \mgmt_io_in[21] , \mgmt_io_in[20] , \mgmt_io_in[19] , \mgmt_io_in[18] , \mgmt_io_in[17] , \mgmt_io_in[16] , \mgmt_io_in[15] , \mgmt_io_in[14] , \mgmt_io_in[13] , \mgmt_io_in[12] , \mgmt_io_in[11] , \mgmt_io_in[10] , \mgmt_io_in[9] , \mgmt_io_in[8] , \mgmt_io_in[7] , \mgmt_io_in[6] , \mgmt_io_in[5] , \mgmt_io_in[4] , \mgmt_io_in[3] , \mgmt_io_in[2] , \mgmt_io_in[1] , \mgmt_io_in[0]  }),
+    .mgmt_gpio_oeb({ \mgmt_io_oeb[4] , \mgmt_io_oeb[3] , \mgmt_io_oeb[2] , \mgmt_io_nc[32] , \mgmt_io_nc[31] , \mgmt_io_nc[30] , \mgmt_io_nc[29] , \mgmt_io_nc[28] , \mgmt_io_nc[27] , \mgmt_io_nc[26] , \mgmt_io_nc[25] , \mgmt_io_nc[24] , \mgmt_io_nc[23] , \mgmt_io_nc[22] , \mgmt_io_nc[21] , \mgmt_io_nc[20] , \mgmt_io_nc[19] , \mgmt_io_nc[18] , \mgmt_io_nc[17] , \mgmt_io_nc[16] , \mgmt_io_nc[15] , \mgmt_io_nc[14] , \mgmt_io_nc[13] , \mgmt_io_nc[12] , \mgmt_io_nc[11] , \mgmt_io_nc[10] , \mgmt_io_nc[9] , \mgmt_io_nc[8] , \mgmt_io_nc[7] , \mgmt_io_nc[6] , \mgmt_io_nc[5] , \mgmt_io_nc[4] , \mgmt_io_nc[3] , \mgmt_io_nc[2] , \mgmt_io_nc[1] , \mgmt_io_nc[0] , \mgmt_io_oeb[1] , \mgmt_io_oeb[0]  }),
+    .mgmt_gpio_out({ \mgmt_io_out[4] , \mgmt_io_out[3] , \mgmt_io_out[2] , \mgmt_io_in[34] , \mgmt_io_in[33] , \mgmt_io_in[32] , \mgmt_io_in[31] , \mgmt_io_in[30] , \mgmt_io_in[29] , \mgmt_io_in[28] , \mgmt_io_in[27] , \mgmt_io_in[26] , \mgmt_io_in[25] , \mgmt_io_in[24] , \mgmt_io_in[23] , \mgmt_io_in[22] , \mgmt_io_in[21] , \mgmt_io_in[20] , \mgmt_io_in[19] , \mgmt_io_in[18] , \mgmt_io_in[17] , \mgmt_io_in[16] , \mgmt_io_in[15] , \mgmt_io_in[14] , \mgmt_io_in[13] , \mgmt_io_in[12] , \mgmt_io_in[11] , \mgmt_io_in[10] , \mgmt_io_in[9] , \mgmt_io_in[8] , \mgmt_io_in[7] , \mgmt_io_in[6] , \mgmt_io_in[5] , \mgmt_io_in[4] , \mgmt_io_in[3] , \mgmt_io_in[2] , \mgmt_io_out[1] , \mgmt_io_out[0]  }),
+    .pad_flash_clk(flash_clk_frame),
+    .pad_flash_clk_oeb(flash_clk_oeb),
+    .pad_flash_csb(flash_csb_frame),
+    .pad_flash_csb_oeb(flash_csb_oeb),
+    .pad_flash_io0_di(flash_io0_di),
+    .pad_flash_io0_do(flash_io0_do),
+    .pad_flash_io0_ieb(flash_io0_ieb),
+    .pad_flash_io0_oeb(flash_io0_oeb),
+    .pad_flash_io1_di(flash_io1_di),
+    .pad_flash_io1_do(flash_io1_do),
+    .pad_flash_io1_ieb(flash_io1_ieb),
+    .pad_flash_io1_oeb(flash_io1_oeb),
+    .pll90_sel({ \spi_pll90_sel[2] , \spi_pll90_sel[1] , \spi_pll90_sel[0]  }),
+    .pll_bypass(ext_clk_sel),
+    .pll_dco_ena(spi_pll_dco_ena),
+    .pll_div({ \spi_pll_div[4] , \spi_pll_div[3] , \spi_pll_div[2] , \spi_pll_div[1] , \spi_pll_div[0]  }),
+    .pll_ena(spi_pll_ena),
+    .pll_sel({ \spi_pll_sel[2] , \spi_pll_sel[1] , \spi_pll_sel[0]  }),
+    .pll_trim({ \spi_pll_trim[25] , \spi_pll_trim[24] , \spi_pll_trim[23] , \spi_pll_trim[22] , \spi_pll_trim[21] , \spi_pll_trim[20] , \spi_pll_trim[19] , \spi_pll_trim[18] , \spi_pll_trim[17] , \spi_pll_trim[16] , \spi_pll_trim[15] , \spi_pll_trim[14] , \spi_pll_trim[13] , \spi_pll_trim[12] , \spi_pll_trim[11] , \spi_pll_trim[10] , \spi_pll_trim[9] , \spi_pll_trim[8] , \spi_pll_trim[7] , \spi_pll_trim[6] , \spi_pll_trim[5] , \spi_pll_trim[4] , \spi_pll_trim[3] , \spi_pll_trim[2] , \spi_pll_trim[1] , \spi_pll_trim[0]  }),
+    .porb(porb_l),
+    .pwr_ctrl_out(),
+    .qspi_enabled(qspi_enabled),
+    .reset(ext_reset),
+    .ser_rx(ser_rx),
+    .ser_tx(ser_tx),
+    .serial_clock(\gpio_clock_1_shifted[0] ),
+    .serial_data_1(\gpio_serial_link_1_shifted[0] ),
+    .serial_data_2(\gpio_serial_link_2_shifted[18] ),
+    .serial_load(\gpio_load_1_shifted[0] ),
+    .serial_resetn(\gpio_resetn_1_shifted[0] ),
+    .spi_csb(spi_csb),
+    .spi_enabled(spi_enabled),
+    .spi_sck(spi_sck),
+    .spi_sdi(spi_sdi),
+    .spi_sdo(spi_sdo),
+    .spi_sdoenb(spi_sdoenb),
+    .spimemio_flash_clk(flash_clk_core),
+    .spimemio_flash_csb(flash_csb_core),
+    .spimemio_flash_io0_di(flash_io0_di_core),
+    .spimemio_flash_io0_do(flash_io0_do_core),
+    .spimemio_flash_io0_oeb(flash_io0_oeb_core),
+    .spimemio_flash_io1_di(flash_io1_di_core),
+    .spimemio_flash_io1_do(flash_io1_do_core),
+    .spimemio_flash_io1_oeb(flash_io1_oeb_core),
+    .spimemio_flash_io2_di(flash_io2_di_core),
+    .spimemio_flash_io2_do(flash_io2_do_core),
+    .spimemio_flash_io2_oeb(flash_io2_oeb_core),
+    .spimemio_flash_io3_di(flash_io3_di_core),
+    .spimemio_flash_io3_do(flash_io3_do_core),
+    .spimemio_flash_io3_oeb(flash_io3_oeb_core),
+    .sram_ro_addr({ \hkspi_sram_addr[7] , \hkspi_sram_addr[6] , \hkspi_sram_addr[5] , \hkspi_sram_addr[4] , \hkspi_sram_addr[3] , \hkspi_sram_addr[2] , \hkspi_sram_addr[1] , \hkspi_sram_addr[0]  }),
+    .sram_ro_clk(hkspi_sram_clk),
+    .sram_ro_csb(hkspi_sram_csb),
+    .sram_ro_data({ \hkspi_sram_data[31] , \hkspi_sram_data[30] , \hkspi_sram_data[29] , \hkspi_sram_data[28] , \hkspi_sram_data[27] , \hkspi_sram_data[26] , \hkspi_sram_data[25] , \hkspi_sram_data[24] , \hkspi_sram_data[23] , \hkspi_sram_data[22] , \hkspi_sram_data[21] , \hkspi_sram_data[20] , \hkspi_sram_data[19] , \hkspi_sram_data[18] , \hkspi_sram_data[17] , \hkspi_sram_data[16] , \hkspi_sram_data[15] , \hkspi_sram_data[14] , \hkspi_sram_data[13] , \hkspi_sram_data[12] , \hkspi_sram_data[11] , \hkspi_sram_data[10] , \hkspi_sram_data[9] , \hkspi_sram_data[8] , \hkspi_sram_data[7] , \hkspi_sram_data[6] , \hkspi_sram_data[5] , \hkspi_sram_data[4] , \hkspi_sram_data[3] , \hkspi_sram_data[2] , \hkspi_sram_data[1] , \hkspi_sram_data[0]  }),
+    .trap(trap),
+    .uart_enabled(uart_enabled),
+    .user_clock(caravel_clk2),
+    .usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+    .usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+    .usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+    .usr2_vdd_pwrgood(mprj2_vdd_pwrgood),
+    .wb_ack_o(hk_ack_i),
+    .wb_adr_i({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0]  }),
+    .wb_clk_i(caravel_clk),
+    .wb_cyc_i(hk_cyc_o),
+    .wb_dat_i({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0]  }),
+    .wb_dat_o({ \hk_dat_i[31] , \hk_dat_i[30] , \hk_dat_i[29] , \hk_dat_i[28] , \hk_dat_i[27] , \hk_dat_i[26] , \hk_dat_i[25] , \hk_dat_i[24] , \hk_dat_i[23] , \hk_dat_i[22] , \hk_dat_i[21] , \hk_dat_i[20] , \hk_dat_i[19] , \hk_dat_i[18] , \hk_dat_i[17] , \hk_dat_i[16] , \hk_dat_i[15] , \hk_dat_i[14] , \hk_dat_i[13] , \hk_dat_i[12] , \hk_dat_i[11] , \hk_dat_i[10] , \hk_dat_i[9] , \hk_dat_i[8] , \hk_dat_i[7] , \hk_dat_i[6] , \hk_dat_i[5] , \hk_dat_i[4] , \hk_dat_i[3] , \hk_dat_i[2] , \hk_dat_i[1] , \hk_dat_i[0]  }),
+    .wb_rstn_i(caravel_rstn),
+    .wb_sel_i({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0]  }),
+    .wb_stb_i(hk_stb_o),
+    .wb_we_i(mprj_we_o_core)
+  );
+  mgmt_protect mgmt_buffers (
+    .caravel_clk(caravel_clk),
+    .caravel_clk2(caravel_clk2),
+    .caravel_rstn(caravel_rstn),
+    .la_data_in_core({ \la_data_in_user[127] , \la_data_in_user[126] , \la_data_in_user[125] , \la_data_in_user[124] , \la_data_in_user[123] , \la_data_in_user[122] , \la_data_in_user[121] , \la_data_in_user[120] , \la_data_in_user[119] , \la_data_in_user[118] , \la_data_in_user[117] , \la_data_in_user[116] , \la_data_in_user[115] , \la_data_in_user[114] , \la_data_in_user[113] , \la_data_in_user[112] , \la_data_in_user[111] , \la_data_in_user[110] , \la_data_in_user[109] , \la_data_in_user[108] , \la_data_in_user[107] , \la_data_in_user[106] , \la_data_in_user[105] , \la_data_in_user[104] , \la_data_in_user[103] , \la_data_in_user[102] , \la_data_in_user[101] , \la_data_in_user[100] , \la_data_in_user[99] , \la_data_in_user[98] , \la_data_in_user[97] , \la_data_in_user[96] , \la_data_in_user[95] , \la_data_in_user[94] , \la_data_in_user[93] , \la_data_in_user[92] , \la_data_in_user[91] , \la_data_in_user[90] , \la_data_in_user[89] , \la_data_in_user[88] , \la_data_in_user[87] , \la_data_in_user[86] , \la_data_in_user[85] , \la_data_in_user[84] , \la_data_in_user[83] , \la_data_in_user[82] , \la_data_in_user[81] , \la_data_in_user[80] , \la_data_in_user[79] , \la_data_in_user[78] , \la_data_in_user[77] , \la_data_in_user[76] , \la_data_in_user[75] , \la_data_in_user[74] , \la_data_in_user[73] , \la_data_in_user[72] , \la_data_in_user[71] , \la_data_in_user[70] , \la_data_in_user[69] , \la_data_in_user[68] , \la_data_in_user[67] , \la_data_in_user[66] , \la_data_in_user[65] , \la_data_in_user[64] , \la_data_in_user[63] , \la_data_in_user[62] , \la_data_in_user[61] , \la_data_in_user[60] , \la_data_in_user[59] , \la_data_in_user[58] , \la_data_in_user[57] , \la_data_in_user[56] , \la_data_in_user[55] , \la_data_in_user[54] , \la_data_in_user[53] , \la_data_in_user[52] , \la_data_in_user[51] , \la_data_in_user[50] , \la_data_in_user[49] , \la_data_in_user[48] , \la_data_in_user[47] , \la_data_in_user[46] , \la_data_in_user[45] , \la_data_in_user[44] , \la_data_in_user[43] , \la_data_in_user[42] , \la_data_in_user[41] , \la_data_in_user[40] , \la_data_in_user[39] , \la_data_in_user[38] , \la_data_in_user[37] , \la_data_in_user[36] , \la_data_in_user[35] , \la_data_in_user[34] , \la_data_in_user[33] , \la_data_in_user[32] , \la_data_in_user[31] , \la_data_in_user[30] , \la_data_in_user[29] , \la_data_in_user[28] , \la_data_in_user[27] , \la_data_in_user[26] , \la_data_in_user[25] , \la_data_in_user[24] , \la_data_in_user[23] , \la_data_in_user[22] , \la_data_in_user[21] , \la_data_in_user[20] , \la_data_in_user[19] , \la_data_in_user[18] , \la_data_in_user[17] , \la_data_in_user[16] , \la_data_in_user[15] , \la_data_in_user[14] , \la_data_in_user[13] , \la_data_in_user[12] , \la_data_in_user[11] , \la_data_in_user[10] , \la_data_in_user[9] , \la_data_in_user[8] , \la_data_in_user[7] , \la_data_in_user[6] , \la_data_in_user[5] , \la_data_in_user[4] , \la_data_in_user[3] , \la_data_in_user[2] , \la_data_in_user[1] , \la_data_in_user[0]  }),
+    .la_data_in_mprj({ \la_data_in_mprj[127] , \la_data_in_mprj[126] , \la_data_in_mprj[125] , \la_data_in_mprj[124] , \la_data_in_mprj[123] , \la_data_in_mprj[122] , \la_data_in_mprj[121] , \la_data_in_mprj[120] , \la_data_in_mprj[119] , \la_data_in_mprj[118] , \la_data_in_mprj[117] , \la_data_in_mprj[116] , \la_data_in_mprj[115] , \la_data_in_mprj[114] , \la_data_in_mprj[113] , \la_data_in_mprj[112] , \la_data_in_mprj[111] , \la_data_in_mprj[110] , \la_data_in_mprj[109] , \la_data_in_mprj[108] , \la_data_in_mprj[107] , \la_data_in_mprj[106] , \la_data_in_mprj[105] , \la_data_in_mprj[104] , \la_data_in_mprj[103] , \la_data_in_mprj[102] , \la_data_in_mprj[101] , \la_data_in_mprj[100] , \la_data_in_mprj[99] , \la_data_in_mprj[98] , \la_data_in_mprj[97] , \la_data_in_mprj[96] , \la_data_in_mprj[95] , \la_data_in_mprj[94] , \la_data_in_mprj[93] , \la_data_in_mprj[92] , \la_data_in_mprj[91] , \la_data_in_mprj[90] , \la_data_in_mprj[89] , \la_data_in_mprj[88] , \la_data_in_mprj[87] , \la_data_in_mprj[86] , \la_data_in_mprj[85] , \la_data_in_mprj[84] , \la_data_in_mprj[83] , \la_data_in_mprj[82] , \la_data_in_mprj[81] , \la_data_in_mprj[80] , \la_data_in_mprj[79] , \la_data_in_mprj[78] , \la_data_in_mprj[77] , \la_data_in_mprj[76] , \la_data_in_mprj[75] , \la_data_in_mprj[74] , \la_data_in_mprj[73] , \la_data_in_mprj[72] , \la_data_in_mprj[71] , \la_data_in_mprj[70] , \la_data_in_mprj[69] , \la_data_in_mprj[68] , \la_data_in_mprj[67] , \la_data_in_mprj[66] , \la_data_in_mprj[65] , \la_data_in_mprj[64] , \la_data_in_mprj[63] , \la_data_in_mprj[62] , \la_data_in_mprj[61] , \la_data_in_mprj[60] , \la_data_in_mprj[59] , \la_data_in_mprj[58] , \la_data_in_mprj[57] , \la_data_in_mprj[56] , \la_data_in_mprj[55] , \la_data_in_mprj[54] , \la_data_in_mprj[53] , \la_data_in_mprj[52] , \la_data_in_mprj[51] , \la_data_in_mprj[50] , \la_data_in_mprj[49] , \la_data_in_mprj[48] , \la_data_in_mprj[47] , \la_data_in_mprj[46] , \la_data_in_mprj[45] , \la_data_in_mprj[44] , \la_data_in_mprj[43] , \la_data_in_mprj[42] , \la_data_in_mprj[41] , \la_data_in_mprj[40] , \la_data_in_mprj[39] , \la_data_in_mprj[38] , \la_data_in_mprj[37] , \la_data_in_mprj[36] , \la_data_in_mprj[35] , \la_data_in_mprj[34] , \la_data_in_mprj[33] , \la_data_in_mprj[32] , \la_data_in_mprj[31] , \la_data_in_mprj[30] , \la_data_in_mprj[29] , \la_data_in_mprj[28] , \la_data_in_mprj[27] , \la_data_in_mprj[26] , \la_data_in_mprj[25] , \la_data_in_mprj[24] , \la_data_in_mprj[23] , \la_data_in_mprj[22] , \la_data_in_mprj[21] , \la_data_in_mprj[20] , \la_data_in_mprj[19] , \la_data_in_mprj[18] , \la_data_in_mprj[17] , \la_data_in_mprj[16] , \la_data_in_mprj[15] , \la_data_in_mprj[14] , \la_data_in_mprj[13] , \la_data_in_mprj[12] , \la_data_in_mprj[11] , \la_data_in_mprj[10] , \la_data_in_mprj[9] , \la_data_in_mprj[8] , \la_data_in_mprj[7] , \la_data_in_mprj[6] , \la_data_in_mprj[5] , \la_data_in_mprj[4] , \la_data_in_mprj[3] , \la_data_in_mprj[2] , \la_data_in_mprj[1] , \la_data_in_mprj[0]  }),
+    .la_data_out_core({ \la_data_out_user[127] , \la_data_out_user[126] , \la_data_out_user[125] , \la_data_out_user[124] , \la_data_out_user[123] , \la_data_out_user[122] , \la_data_out_user[121] , \la_data_out_user[120] , \la_data_out_user[119] , \la_data_out_user[118] , \la_data_out_user[117] , \la_data_out_user[116] , \la_data_out_user[115] , \la_data_out_user[114] , \la_data_out_user[113] , \la_data_out_user[112] , \la_data_out_user[111] , \la_data_out_user[110] , \la_data_out_user[109] , \la_data_out_user[108] , \la_data_out_user[107] , \la_data_out_user[106] , \la_data_out_user[105] , \la_data_out_user[104] , \la_data_out_user[103] , \la_data_out_user[102] , \la_data_out_user[101] , \la_data_out_user[100] , \la_data_out_user[99] , \la_data_out_user[98] , \la_data_out_user[97] , \la_data_out_user[96] , \la_data_out_user[95] , \la_data_out_user[94] , \la_data_out_user[93] , \la_data_out_user[92] , \la_data_out_user[91] , \la_data_out_user[90] , \la_data_out_user[89] , \la_data_out_user[88] , \la_data_out_user[87] , \la_data_out_user[86] , \la_data_out_user[85] , \la_data_out_user[84] , \la_data_out_user[83] , \la_data_out_user[82] , \la_data_out_user[81] , \la_data_out_user[80] , \la_data_out_user[79] , \la_data_out_user[78] , \la_data_out_user[77] , \la_data_out_user[76] , \la_data_out_user[75] , \la_data_out_user[74] , \la_data_out_user[73] , \la_data_out_user[72] , \la_data_out_user[71] , \la_data_out_user[70] , \la_data_out_user[69] , \la_data_out_user[68] , \la_data_out_user[67] , \la_data_out_user[66] , \la_data_out_user[65] , \la_data_out_user[64] , \la_data_out_user[63] , \la_data_out_user[62] , \la_data_out_user[61] , \la_data_out_user[60] , \la_data_out_user[59] , \la_data_out_user[58] , \la_data_out_user[57] , \la_data_out_user[56] , \la_data_out_user[55] , \la_data_out_user[54] , \la_data_out_user[53] , \la_data_out_user[52] , \la_data_out_user[51] , \la_data_out_user[50] , \la_data_out_user[49] , \la_data_out_user[48] , \la_data_out_user[47] , \la_data_out_user[46] , \la_data_out_user[45] , \la_data_out_user[44] , \la_data_out_user[43] , \la_data_out_user[42] , \la_data_out_user[41] , \la_data_out_user[40] , \la_data_out_user[39] , \la_data_out_user[38] , \la_data_out_user[37] , \la_data_out_user[36] , \la_data_out_user[35] , \la_data_out_user[34] , \la_data_out_user[33] , \la_data_out_user[32] , \la_data_out_user[31] , \la_data_out_user[30] , \la_data_out_user[29] , \la_data_out_user[28] , \la_data_out_user[27] , \la_data_out_user[26] , \la_data_out_user[25] , \la_data_out_user[24] , \la_data_out_user[23] , \la_data_out_user[22] , \la_data_out_user[21] , \la_data_out_user[20] , \la_data_out_user[19] , \la_data_out_user[18] , \la_data_out_user[17] , \la_data_out_user[16] , \la_data_out_user[15] , \la_data_out_user[14] , \la_data_out_user[13] , \la_data_out_user[12] , \la_data_out_user[11] , \la_data_out_user[10] , \la_data_out_user[9] , \la_data_out_user[8] , \la_data_out_user[7] , \la_data_out_user[6] , \la_data_out_user[5] , \la_data_out_user[4] , \la_data_out_user[3] , \la_data_out_user[2] , \la_data_out_user[1] , \la_data_out_user[0]  }),
+    .la_data_out_mprj({ \la_data_out_mprj[127] , \la_data_out_mprj[126] , \la_data_out_mprj[125] , \la_data_out_mprj[124] , \la_data_out_mprj[123] , \la_data_out_mprj[122] , \la_data_out_mprj[121] , \la_data_out_mprj[120] , \la_data_out_mprj[119] , \la_data_out_mprj[118] , \la_data_out_mprj[117] , \la_data_out_mprj[116] , \la_data_out_mprj[115] , \la_data_out_mprj[114] , \la_data_out_mprj[113] , \la_data_out_mprj[112] , \la_data_out_mprj[111] , \la_data_out_mprj[110] , \la_data_out_mprj[109] , \la_data_out_mprj[108] , \la_data_out_mprj[107] , \la_data_out_mprj[106] , \la_data_out_mprj[105] , \la_data_out_mprj[104] , \la_data_out_mprj[103] , \la_data_out_mprj[102] , \la_data_out_mprj[101] , \la_data_out_mprj[100] , \la_data_out_mprj[99] , \la_data_out_mprj[98] , \la_data_out_mprj[97] , \la_data_out_mprj[96] , \la_data_out_mprj[95] , \la_data_out_mprj[94] , \la_data_out_mprj[93] , \la_data_out_mprj[92] , \la_data_out_mprj[91] , \la_data_out_mprj[90] , \la_data_out_mprj[89] , \la_data_out_mprj[88] , \la_data_out_mprj[87] , \la_data_out_mprj[86] , \la_data_out_mprj[85] , \la_data_out_mprj[84] , \la_data_out_mprj[83] , \la_data_out_mprj[82] , \la_data_out_mprj[81] , \la_data_out_mprj[80] , \la_data_out_mprj[79] , \la_data_out_mprj[78] , \la_data_out_mprj[77] , \la_data_out_mprj[76] , \la_data_out_mprj[75] , \la_data_out_mprj[74] , \la_data_out_mprj[73] , \la_data_out_mprj[72] , \la_data_out_mprj[71] , \la_data_out_mprj[70] , \la_data_out_mprj[69] , \la_data_out_mprj[68] , \la_data_out_mprj[67] , \la_data_out_mprj[66] , \la_data_out_mprj[65] , \la_data_out_mprj[64] , \la_data_out_mprj[63] , \la_data_out_mprj[62] , \la_data_out_mprj[61] , \la_data_out_mprj[60] , \la_data_out_mprj[59] , \la_data_out_mprj[58] , \la_data_out_mprj[57] , \la_data_out_mprj[56] , \la_data_out_mprj[55] , \la_data_out_mprj[54] , \la_data_out_mprj[53] , \la_data_out_mprj[52] , \la_data_out_mprj[51] , \la_data_out_mprj[50] , \la_data_out_mprj[49] , \la_data_out_mprj[48] , \la_data_out_mprj[47] , \la_data_out_mprj[46] , \la_data_out_mprj[45] , \la_data_out_mprj[44] , \la_data_out_mprj[43] , \la_data_out_mprj[42] , \la_data_out_mprj[41] , \la_data_out_mprj[40] , \la_data_out_mprj[39] , \la_data_out_mprj[38] , \la_data_out_mprj[37] , \la_data_out_mprj[36] , \la_data_out_mprj[35] , \la_data_out_mprj[34] , \la_data_out_mprj[33] , \la_data_out_mprj[32] , \la_data_out_mprj[31] , \la_data_out_mprj[30] , \la_data_out_mprj[29] , \la_data_out_mprj[28] , \la_data_out_mprj[27] , \la_data_out_mprj[26] , \la_data_out_mprj[25] , \la_data_out_mprj[24] , \la_data_out_mprj[23] , \la_data_out_mprj[22] , \la_data_out_mprj[21] , \la_data_out_mprj[20] , \la_data_out_mprj[19] , \la_data_out_mprj[18] , \la_data_out_mprj[17] , \la_data_out_mprj[16] , \la_data_out_mprj[15] , \la_data_out_mprj[14] , \la_data_out_mprj[13] , \la_data_out_mprj[12] , \la_data_out_mprj[11] , \la_data_out_mprj[10] , \la_data_out_mprj[9] , \la_data_out_mprj[8] , \la_data_out_mprj[7] , \la_data_out_mprj[6] , \la_data_out_mprj[5] , \la_data_out_mprj[4] , \la_data_out_mprj[3] , \la_data_out_mprj[2] , \la_data_out_mprj[1] , \la_data_out_mprj[0]  }),
+    .la_iena_mprj({ \la_iena_mprj[127] , \la_iena_mprj[126] , \la_iena_mprj[125] , \la_iena_mprj[124] , \la_iena_mprj[123] , \la_iena_mprj[122] , \la_iena_mprj[121] , \la_iena_mprj[120] , \la_iena_mprj[119] , \la_iena_mprj[118] , \la_iena_mprj[117] , \la_iena_mprj[116] , \la_iena_mprj[115] , \la_iena_mprj[114] , \la_iena_mprj[113] , \la_iena_mprj[112] , \la_iena_mprj[111] , \la_iena_mprj[110] , \la_iena_mprj[109] , \la_iena_mprj[108] , \la_iena_mprj[107] , \la_iena_mprj[106] , \la_iena_mprj[105] , \la_iena_mprj[104] , \la_iena_mprj[103] , \la_iena_mprj[102] , \la_iena_mprj[101] , \la_iena_mprj[100] , \la_iena_mprj[99] , \la_iena_mprj[98] , \la_iena_mprj[97] , \la_iena_mprj[96] , \la_iena_mprj[95] , \la_iena_mprj[94] , \la_iena_mprj[93] , \la_iena_mprj[92] , \la_iena_mprj[91] , \la_iena_mprj[90] , \la_iena_mprj[89] , \la_iena_mprj[88] , \la_iena_mprj[87] , \la_iena_mprj[86] , \la_iena_mprj[85] , \la_iena_mprj[84] , \la_iena_mprj[83] , \la_iena_mprj[82] , \la_iena_mprj[81] , \la_iena_mprj[80] , \la_iena_mprj[79] , \la_iena_mprj[78] , \la_iena_mprj[77] , \la_iena_mprj[76] , \la_iena_mprj[75] , \la_iena_mprj[74] , \la_iena_mprj[73] , \la_iena_mprj[72] , \la_iena_mprj[71] , \la_iena_mprj[70] , \la_iena_mprj[69] , \la_iena_mprj[68] , \la_iena_mprj[67] , \la_iena_mprj[66] , \la_iena_mprj[65] , \la_iena_mprj[64] , \la_iena_mprj[63] , \la_iena_mprj[62] , \la_iena_mprj[61] , \la_iena_mprj[60] , \la_iena_mprj[59] , \la_iena_mprj[58] , \la_iena_mprj[57] , \la_iena_mprj[56] , \la_iena_mprj[55] , \la_iena_mprj[54] , \la_iena_mprj[53] , \la_iena_mprj[52] , \la_iena_mprj[51] , \la_iena_mprj[50] , \la_iena_mprj[49] , \la_iena_mprj[48] , \la_iena_mprj[47] , \la_iena_mprj[46] , \la_iena_mprj[45] , \la_iena_mprj[44] , \la_iena_mprj[43] , \la_iena_mprj[42] , \la_iena_mprj[41] , \la_iena_mprj[40] , \la_iena_mprj[39] , \la_iena_mprj[38] , \la_iena_mprj[37] , \la_iena_mprj[36] , \la_iena_mprj[35] , \la_iena_mprj[34] , \la_iena_mprj[33] , \la_iena_mprj[32] , \la_iena_mprj[31] , \la_iena_mprj[30] , \la_iena_mprj[29] , \la_iena_mprj[28] , \la_iena_mprj[27] , \la_iena_mprj[26] , \la_iena_mprj[25] , \la_iena_mprj[24] , \la_iena_mprj[23] , \la_iena_mprj[22] , \la_iena_mprj[21] , \la_iena_mprj[20] , \la_iena_mprj[19] , \la_iena_mprj[18] , \la_iena_mprj[17] , \la_iena_mprj[16] , \la_iena_mprj[15] , \la_iena_mprj[14] , \la_iena_mprj[13] , \la_iena_mprj[12] , \la_iena_mprj[11] , \la_iena_mprj[10] , \la_iena_mprj[9] , \la_iena_mprj[8] , \la_iena_mprj[7] , \la_iena_mprj[6] , \la_iena_mprj[5] , \la_iena_mprj[4] , \la_iena_mprj[3] , \la_iena_mprj[2] , \la_iena_mprj[1] , \la_iena_mprj[0]  }),
+    .la_oenb_core({ \la_oenb_user[127] , \la_oenb_user[126] , \la_oenb_user[125] , \la_oenb_user[124] , \la_oenb_user[123] , \la_oenb_user[122] , \la_oenb_user[121] , \la_oenb_user[120] , \la_oenb_user[119] , \la_oenb_user[118] , \la_oenb_user[117] , \la_oenb_user[116] , \la_oenb_user[115] , \la_oenb_user[114] , \la_oenb_user[113] , \la_oenb_user[112] , \la_oenb_user[111] , \la_oenb_user[110] , \la_oenb_user[109] , \la_oenb_user[108] , \la_oenb_user[107] , \la_oenb_user[106] , \la_oenb_user[105] , \la_oenb_user[104] , \la_oenb_user[103] , \la_oenb_user[102] , \la_oenb_user[101] , \la_oenb_user[100] , \la_oenb_user[99] , \la_oenb_user[98] , \la_oenb_user[97] , \la_oenb_user[96] , \la_oenb_user[95] , \la_oenb_user[94] , \la_oenb_user[93] , \la_oenb_user[92] , \la_oenb_user[91] , \la_oenb_user[90] , \la_oenb_user[89] , \la_oenb_user[88] , \la_oenb_user[87] , \la_oenb_user[86] , \la_oenb_user[85] , \la_oenb_user[84] , \la_oenb_user[83] , \la_oenb_user[82] , \la_oenb_user[81] , \la_oenb_user[80] , \la_oenb_user[79] , \la_oenb_user[78] , \la_oenb_user[77] , \la_oenb_user[76] , \la_oenb_user[75] , \la_oenb_user[74] , \la_oenb_user[73] , \la_oenb_user[72] , \la_oenb_user[71] , \la_oenb_user[70] , \la_oenb_user[69] , \la_oenb_user[68] , \la_oenb_user[67] , \la_oenb_user[66] , \la_oenb_user[65] , \la_oenb_user[64] , \la_oenb_user[63] , \la_oenb_user[62] , \la_oenb_user[61] , \la_oenb_user[60] , \la_oenb_user[59] , \la_oenb_user[58] , \la_oenb_user[57] , \la_oenb_user[56] , \la_oenb_user[55] , \la_oenb_user[54] , \la_oenb_user[53] , \la_oenb_user[52] , \la_oenb_user[51] , \la_oenb_user[50] , \la_oenb_user[49] , \la_oenb_user[48] , \la_oenb_user[47] , \la_oenb_user[46] , \la_oenb_user[45] , \la_oenb_user[44] , \la_oenb_user[43] , \la_oenb_user[42] , \la_oenb_user[41] , \la_oenb_user[40] , \la_oenb_user[39] , \la_oenb_user[38] , \la_oenb_user[37] , \la_oenb_user[36] , \la_oenb_user[35] , \la_oenb_user[34] , \la_oenb_user[33] , \la_oenb_user[32] , \la_oenb_user[31] , \la_oenb_user[30] , \la_oenb_user[29] , \la_oenb_user[28] , \la_oenb_user[27] , \la_oenb_user[26] , \la_oenb_user[25] , \la_oenb_user[24] , \la_oenb_user[23] , \la_oenb_user[22] , \la_oenb_user[21] , \la_oenb_user[20] , \la_oenb_user[19] , \la_oenb_user[18] , \la_oenb_user[17] , \la_oenb_user[16] , \la_oenb_user[15] , \la_oenb_user[14] , \la_oenb_user[13] , \la_oenb_user[12] , \la_oenb_user[11] , \la_oenb_user[10] , \la_oenb_user[9] , \la_oenb_user[8] , \la_oenb_user[7] , \la_oenb_user[6] , \la_oenb_user[5] , \la_oenb_user[4] , \la_oenb_user[3] , \la_oenb_user[2] , \la_oenb_user[1] , \la_oenb_user[0]  }),
+    .la_oenb_mprj({ \la_oenb_mprj[127] , \la_oenb_mprj[126] , \la_oenb_mprj[125] , \la_oenb_mprj[124] , \la_oenb_mprj[123] , \la_oenb_mprj[122] , \la_oenb_mprj[121] , \la_oenb_mprj[120] , \la_oenb_mprj[119] , \la_oenb_mprj[118] , \la_oenb_mprj[117] , \la_oenb_mprj[116] , \la_oenb_mprj[115] , \la_oenb_mprj[114] , \la_oenb_mprj[113] , \la_oenb_mprj[112] , \la_oenb_mprj[111] , \la_oenb_mprj[110] , \la_oenb_mprj[109] , \la_oenb_mprj[108] , \la_oenb_mprj[107] , \la_oenb_mprj[106] , \la_oenb_mprj[105] , \la_oenb_mprj[104] , \la_oenb_mprj[103] , \la_oenb_mprj[102] , \la_oenb_mprj[101] , \la_oenb_mprj[100] , \la_oenb_mprj[99] , \la_oenb_mprj[98] , \la_oenb_mprj[97] , \la_oenb_mprj[96] , \la_oenb_mprj[95] , \la_oenb_mprj[94] , \la_oenb_mprj[93] , \la_oenb_mprj[92] , \la_oenb_mprj[91] , \la_oenb_mprj[90] , \la_oenb_mprj[89] , \la_oenb_mprj[88] , \la_oenb_mprj[87] , \la_oenb_mprj[86] , \la_oenb_mprj[85] , \la_oenb_mprj[84] , \la_oenb_mprj[83] , \la_oenb_mprj[82] , \la_oenb_mprj[81] , \la_oenb_mprj[80] , \la_oenb_mprj[79] , \la_oenb_mprj[78] , \la_oenb_mprj[77] , \la_oenb_mprj[76] , \la_oenb_mprj[75] , \la_oenb_mprj[74] , \la_oenb_mprj[73] , \la_oenb_mprj[72] , \la_oenb_mprj[71] , \la_oenb_mprj[70] , \la_oenb_mprj[69] , \la_oenb_mprj[68] , \la_oenb_mprj[67] , \la_oenb_mprj[66] , \la_oenb_mprj[65] , \la_oenb_mprj[64] , \la_oenb_mprj[63] , \la_oenb_mprj[62] , \la_oenb_mprj[61] , \la_oenb_mprj[60] , \la_oenb_mprj[59] , \la_oenb_mprj[58] , \la_oenb_mprj[57] , \la_oenb_mprj[56] , \la_oenb_mprj[55] , \la_oenb_mprj[54] , \la_oenb_mprj[53] , \la_oenb_mprj[52] , \la_oenb_mprj[51] , \la_oenb_mprj[50] , \la_oenb_mprj[49] , \la_oenb_mprj[48] , \la_oenb_mprj[47] , \la_oenb_mprj[46] , \la_oenb_mprj[45] , \la_oenb_mprj[44] , \la_oenb_mprj[43] , \la_oenb_mprj[42] , \la_oenb_mprj[41] , \la_oenb_mprj[40] , \la_oenb_mprj[39] , \la_oenb_mprj[38] , \la_oenb_mprj[37] , \la_oenb_mprj[36] , \la_oenb_mprj[35] , \la_oenb_mprj[34] , \la_oenb_mprj[33] , \la_oenb_mprj[32] , \la_oenb_mprj[31] , \la_oenb_mprj[30] , \la_oenb_mprj[29] , \la_oenb_mprj[28] , \la_oenb_mprj[27] , \la_oenb_mprj[26] , \la_oenb_mprj[25] , \la_oenb_mprj[24] , \la_oenb_mprj[23] , \la_oenb_mprj[22] , \la_oenb_mprj[21] , \la_oenb_mprj[20] , \la_oenb_mprj[19] , \la_oenb_mprj[18] , \la_oenb_mprj[17] , \la_oenb_mprj[16] , \la_oenb_mprj[15] , \la_oenb_mprj[14] , \la_oenb_mprj[13] , \la_oenb_mprj[12] , \la_oenb_mprj[11] , \la_oenb_mprj[10] , \la_oenb_mprj[9] , \la_oenb_mprj[8] , \la_oenb_mprj[7] , \la_oenb_mprj[6] , \la_oenb_mprj[5] , \la_oenb_mprj[4] , \la_oenb_mprj[3] , \la_oenb_mprj[2] , \la_oenb_mprj[1] , \la_oenb_mprj[0]  }),
+    .mprj_ack_i_core(mprj_ack_i_core),
+    .mprj_ack_i_user(mprj_ack_i_user),
+    .mprj_adr_o_core({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0]  }),
+    .mprj_adr_o_user({ \mprj_adr_o_user[31] , \mprj_adr_o_user[30] , \mprj_adr_o_user[29] , \mprj_adr_o_user[28] , \mprj_adr_o_user[27] , \mprj_adr_o_user[26] , \mprj_adr_o_user[25] , \mprj_adr_o_user[24] , \mprj_adr_o_user[23] , \mprj_adr_o_user[22] , \mprj_adr_o_user[21] , \mprj_adr_o_user[20] , \mprj_adr_o_user[19] , \mprj_adr_o_user[18] , \mprj_adr_o_user[17] , \mprj_adr_o_user[16] , \mprj_adr_o_user[15] , \mprj_adr_o_user[14] , \mprj_adr_o_user[13] , \mprj_adr_o_user[12] , \mprj_adr_o_user[11] , \mprj_adr_o_user[10] , \mprj_adr_o_user[9] , \mprj_adr_o_user[8] , \mprj_adr_o_user[7] , \mprj_adr_o_user[6] , \mprj_adr_o_user[5] , \mprj_adr_o_user[4] , \mprj_adr_o_user[3] , \mprj_adr_o_user[2] , \mprj_adr_o_user[1] , \mprj_adr_o_user[0]  }),
+    .mprj_cyc_o_core(mprj_cyc_o_core),
+    .mprj_cyc_o_user(mprj_cyc_o_user),
+    .mprj_dat_i_core({ \mprj_dat_i_core[31] , \mprj_dat_i_core[30] , \mprj_dat_i_core[29] , \mprj_dat_i_core[28] , \mprj_dat_i_core[27] , \mprj_dat_i_core[26] , \mprj_dat_i_core[25] , \mprj_dat_i_core[24] , \mprj_dat_i_core[23] , \mprj_dat_i_core[22] , \mprj_dat_i_core[21] , \mprj_dat_i_core[20] , \mprj_dat_i_core[19] , \mprj_dat_i_core[18] , \mprj_dat_i_core[17] , \mprj_dat_i_core[16] , \mprj_dat_i_core[15] , \mprj_dat_i_core[14] , \mprj_dat_i_core[13] , \mprj_dat_i_core[12] , \mprj_dat_i_core[11] , \mprj_dat_i_core[10] , \mprj_dat_i_core[9] , \mprj_dat_i_core[8] , \mprj_dat_i_core[7] , \mprj_dat_i_core[6] , \mprj_dat_i_core[5] , \mprj_dat_i_core[4] , \mprj_dat_i_core[3] , \mprj_dat_i_core[2] , \mprj_dat_i_core[1] , \mprj_dat_i_core[0]  }),
+    .mprj_dat_i_user({ \mprj_dat_i_user[31] , \mprj_dat_i_user[30] , \mprj_dat_i_user[29] , \mprj_dat_i_user[28] , \mprj_dat_i_user[27] , \mprj_dat_i_user[26] , \mprj_dat_i_user[25] , \mprj_dat_i_user[24] , \mprj_dat_i_user[23] , \mprj_dat_i_user[22] , \mprj_dat_i_user[21] , \mprj_dat_i_user[20] , \mprj_dat_i_user[19] , \mprj_dat_i_user[18] , \mprj_dat_i_user[17] , \mprj_dat_i_user[16] , \mprj_dat_i_user[15] , \mprj_dat_i_user[14] , \mprj_dat_i_user[13] , \mprj_dat_i_user[12] , \mprj_dat_i_user[11] , \mprj_dat_i_user[10] , \mprj_dat_i_user[9] , \mprj_dat_i_user[8] , \mprj_dat_i_user[7] , \mprj_dat_i_user[6] , \mprj_dat_i_user[5] , \mprj_dat_i_user[4] , \mprj_dat_i_user[3] , \mprj_dat_i_user[2] , \mprj_dat_i_user[1] , \mprj_dat_i_user[0]  }),
+    .mprj_dat_o_core({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0]  }),
+    .mprj_dat_o_user({ \mprj_dat_o_user[31] , \mprj_dat_o_user[30] , \mprj_dat_o_user[29] , \mprj_dat_o_user[28] , \mprj_dat_o_user[27] , \mprj_dat_o_user[26] , \mprj_dat_o_user[25] , \mprj_dat_o_user[24] , \mprj_dat_o_user[23] , \mprj_dat_o_user[22] , \mprj_dat_o_user[21] , \mprj_dat_o_user[20] , \mprj_dat_o_user[19] , \mprj_dat_o_user[18] , \mprj_dat_o_user[17] , \mprj_dat_o_user[16] , \mprj_dat_o_user[15] , \mprj_dat_o_user[14] , \mprj_dat_o_user[13] , \mprj_dat_o_user[12] , \mprj_dat_o_user[11] , \mprj_dat_o_user[10] , \mprj_dat_o_user[9] , \mprj_dat_o_user[8] , \mprj_dat_o_user[7] , \mprj_dat_o_user[6] , \mprj_dat_o_user[5] , \mprj_dat_o_user[4] , \mprj_dat_o_user[3] , \mprj_dat_o_user[2] , \mprj_dat_o_user[1] , \mprj_dat_o_user[0]  }),
+    .mprj_iena_wb(mprj_iena_wb),
+    .mprj_sel_o_core({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0]  }),
+    .mprj_sel_o_user({ \mprj_sel_o_user[3] , \mprj_sel_o_user[2] , \mprj_sel_o_user[1] , \mprj_sel_o_user[0]  }),
+    .mprj_stb_o_core(mprj_stb_o_core),
+    .mprj_stb_o_user(mprj_stb_o_user),
+    .mprj_we_o_core(mprj_we_o_core),
+    .mprj_we_o_user(mprj_we_o_user),
+    .user1_vcc_powergood(mprj_vcc_pwrgood),
+    .user1_vdd_powergood(mprj_vdd_pwrgood),
+    .user2_vcc_powergood(mprj2_vcc_pwrgood),
+    .user2_vdd_powergood(mprj2_vdd_pwrgood),
+    .user_clock(mprj_clock),
+    .user_clock2(mprj_clock2),
+    .user_irq({ \user_irq[2] , \user_irq[1] , \user_irq[0]  }),
+    .user_irq_core({ \user_irq_core[2] , \user_irq_core[1] , \user_irq_core[0]  }),
+    .user_irq_ena({ \user_irq_ena[2] , \user_irq_ena[1] , \user_irq_ena[0]  }),
+    .user_reset(mprj_reset),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vccd2(vccd2_core),
+    .vdda1(vdda1_core),
+    .vdda2(vdda2_core),
+    .vssa1(vssa1_core),
+    .vssa2(vssa2_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .vssd2(vssd2_core)
+  );
+  user_project_wrapper mprj (
+    .analog_io({ \user_analog_io[28] , \user_analog_io[27] , \user_analog_io[26] , \user_analog_io[25] , \user_analog_io[24] , \user_analog_io[23] , \user_analog_io[22] , \user_analog_io[21] , \user_analog_io[20] , \user_analog_io[19] , \user_analog_io[18] , \user_analog_io[17] , \user_analog_io[16] , \user_analog_io[15] , \user_analog_io[14] , \user_analog_io[13] , \user_analog_io[12] , \user_analog_io[11] , \user_analog_io[10] , \user_analog_io[9] , \user_analog_io[8] , \user_analog_io[7] , \user_analog_io[6] , \user_analog_io[5] , \user_analog_io[4] , \user_analog_io[3] , \user_analog_io[2] , \user_analog_io[1] , \user_analog_io[0]  }),
+    .io_in({ \user_io_in[37] , \user_io_in[36] , \user_io_in[35] , \user_io_in[34] , \user_io_in[33] , \user_io_in[32] , \user_io_in[31] , \user_io_in[30] , \user_io_in[29] , \user_io_in[28] , \user_io_in[27] , \user_io_in[26] , \user_io_in[25] , \user_io_in[24] , \user_io_in[23] , \user_io_in[22] , \user_io_in[21] , \user_io_in[20] , \user_io_in[19] , \user_io_in[18] , \user_io_in[17] , \user_io_in[16] , \user_io_in[15] , \user_io_in[14] , \user_io_in[13] , \user_io_in[12] , \user_io_in[11] , \user_io_in[10] , \user_io_in[9] , \user_io_in[8] , \user_io_in[7] , \user_io_in[6] , \user_io_in[5] , \user_io_in[4] , \user_io_in[3] , \user_io_in[2] , \user_io_in[1] , \user_io_in[0]  }),
+    .io_oeb({ \user_io_oeb[37] , \user_io_oeb[36] , \user_io_oeb[35] , \user_io_oeb[34] , \user_io_oeb[33] , \user_io_oeb[32] , \user_io_oeb[31] , \user_io_oeb[30] , \user_io_oeb[29] , \user_io_oeb[28] , \user_io_oeb[27] , \user_io_oeb[26] , \user_io_oeb[25] , \user_io_oeb[24] , \user_io_oeb[23] , \user_io_oeb[22] , \user_io_oeb[21] , \user_io_oeb[20] , \user_io_oeb[19] , \user_io_oeb[18] , \user_io_oeb[17] , \user_io_oeb[16] , \user_io_oeb[15] , \user_io_oeb[14] , \user_io_oeb[13] , \user_io_oeb[12] , \user_io_oeb[11] , \user_io_oeb[10] , \user_io_oeb[9] , \user_io_oeb[8] , \user_io_oeb[7] , \user_io_oeb[6] , \user_io_oeb[5] , \user_io_oeb[4] , \user_io_oeb[3] , \user_io_oeb[2] , \user_io_oeb[1] , \user_io_oeb[0]  }),
+    .io_out({ \user_io_out[37] , \user_io_out[36] , \user_io_out[35] , \user_io_out[34] , \user_io_out[33] , \user_io_out[32] , \user_io_out[31] , \user_io_out[30] , \user_io_out[29] , \user_io_out[28] , \user_io_out[27] , \user_io_out[26] , \user_io_out[25] , \user_io_out[24] , \user_io_out[23] , \user_io_out[22] , \user_io_out[21] , \user_io_out[20] , \user_io_out[19] , \user_io_out[18] , \user_io_out[17] , \user_io_out[16] , \user_io_out[15] , \user_io_out[14] , \user_io_out[13] , \user_io_out[12] , \user_io_out[11] , \user_io_out[10] , \user_io_out[9] , \user_io_out[8] , \user_io_out[7] , \user_io_out[6] , \user_io_out[5] , \user_io_out[4] , \user_io_out[3] , \user_io_out[2] , \user_io_out[1] , \user_io_out[0]  }),
+    .la_data_in({ \la_data_in_user[127] , \la_data_in_user[126] , \la_data_in_user[125] , \la_data_in_user[124] , \la_data_in_user[123] , \la_data_in_user[122] , \la_data_in_user[121] , \la_data_in_user[120] , \la_data_in_user[119] , \la_data_in_user[118] , \la_data_in_user[117] , \la_data_in_user[116] , \la_data_in_user[115] , \la_data_in_user[114] , \la_data_in_user[113] , \la_data_in_user[112] , \la_data_in_user[111] , \la_data_in_user[110] , \la_data_in_user[109] , \la_data_in_user[108] , \la_data_in_user[107] , \la_data_in_user[106] , \la_data_in_user[105] , \la_data_in_user[104] , \la_data_in_user[103] , \la_data_in_user[102] , \la_data_in_user[101] , \la_data_in_user[100] , \la_data_in_user[99] , \la_data_in_user[98] , \la_data_in_user[97] , \la_data_in_user[96] , \la_data_in_user[95] , \la_data_in_user[94] , \la_data_in_user[93] , \la_data_in_user[92] , \la_data_in_user[91] , \la_data_in_user[90] , \la_data_in_user[89] , \la_data_in_user[88] , \la_data_in_user[87] , \la_data_in_user[86] , \la_data_in_user[85] , \la_data_in_user[84] , \la_data_in_user[83] , \la_data_in_user[82] , \la_data_in_user[81] , \la_data_in_user[80] , \la_data_in_user[79] , \la_data_in_user[78] , \la_data_in_user[77] , \la_data_in_user[76] , \la_data_in_user[75] , \la_data_in_user[74] , \la_data_in_user[73] , \la_data_in_user[72] , \la_data_in_user[71] , \la_data_in_user[70] , \la_data_in_user[69] , \la_data_in_user[68] , \la_data_in_user[67] , \la_data_in_user[66] , \la_data_in_user[65] , \la_data_in_user[64] , \la_data_in_user[63] , \la_data_in_user[62] , \la_data_in_user[61] , \la_data_in_user[60] , \la_data_in_user[59] , \la_data_in_user[58] , \la_data_in_user[57] , \la_data_in_user[56] , \la_data_in_user[55] , \la_data_in_user[54] , \la_data_in_user[53] , \la_data_in_user[52] , \la_data_in_user[51] , \la_data_in_user[50] , \la_data_in_user[49] , \la_data_in_user[48] , \la_data_in_user[47] , \la_data_in_user[46] , \la_data_in_user[45] , \la_data_in_user[44] , \la_data_in_user[43] , \la_data_in_user[42] , \la_data_in_user[41] , \la_data_in_user[40] , \la_data_in_user[39] , \la_data_in_user[38] , \la_data_in_user[37] , \la_data_in_user[36] , \la_data_in_user[35] , \la_data_in_user[34] , \la_data_in_user[33] , \la_data_in_user[32] , \la_data_in_user[31] , \la_data_in_user[30] , \la_data_in_user[29] , \la_data_in_user[28] , \la_data_in_user[27] , \la_data_in_user[26] , \la_data_in_user[25] , \la_data_in_user[24] , \la_data_in_user[23] , \la_data_in_user[22] , \la_data_in_user[21] , \la_data_in_user[20] , \la_data_in_user[19] , \la_data_in_user[18] , \la_data_in_user[17] , \la_data_in_user[16] , \la_data_in_user[15] , \la_data_in_user[14] , \la_data_in_user[13] , \la_data_in_user[12] , \la_data_in_user[11] , \la_data_in_user[10] , \la_data_in_user[9] , \la_data_in_user[8] , \la_data_in_user[7] , \la_data_in_user[6] , \la_data_in_user[5] , \la_data_in_user[4] , \la_data_in_user[3] , \la_data_in_user[2] , \la_data_in_user[1] , \la_data_in_user[0]  }),
+    .la_data_out({ \la_data_out_user[127] , \la_data_out_user[126] , \la_data_out_user[125] , \la_data_out_user[124] , \la_data_out_user[123] , \la_data_out_user[122] , \la_data_out_user[121] , \la_data_out_user[120] , \la_data_out_user[119] , \la_data_out_user[118] , \la_data_out_user[117] , \la_data_out_user[116] , \la_data_out_user[115] , \la_data_out_user[114] , \la_data_out_user[113] , \la_data_out_user[112] , \la_data_out_user[111] , \la_data_out_user[110] , \la_data_out_user[109] , \la_data_out_user[108] , \la_data_out_user[107] , \la_data_out_user[106] , \la_data_out_user[105] , \la_data_out_user[104] , \la_data_out_user[103] , \la_data_out_user[102] , \la_data_out_user[101] , \la_data_out_user[100] , \la_data_out_user[99] , \la_data_out_user[98] , \la_data_out_user[97] , \la_data_out_user[96] , \la_data_out_user[95] , \la_data_out_user[94] , \la_data_out_user[93] , \la_data_out_user[92] , \la_data_out_user[91] , \la_data_out_user[90] , \la_data_out_user[89] , \la_data_out_user[88] , \la_data_out_user[87] , \la_data_out_user[86] , \la_data_out_user[85] , \la_data_out_user[84] , \la_data_out_user[83] , \la_data_out_user[82] , \la_data_out_user[81] , \la_data_out_user[80] , \la_data_out_user[79] , \la_data_out_user[78] , \la_data_out_user[77] , \la_data_out_user[76] , \la_data_out_user[75] , \la_data_out_user[74] , \la_data_out_user[73] , \la_data_out_user[72] , \la_data_out_user[71] , \la_data_out_user[70] , \la_data_out_user[69] , \la_data_out_user[68] , \la_data_out_user[67] , \la_data_out_user[66] , \la_data_out_user[65] , \la_data_out_user[64] , \la_data_out_user[63] , \la_data_out_user[62] , \la_data_out_user[61] , \la_data_out_user[60] , \la_data_out_user[59] , \la_data_out_user[58] , \la_data_out_user[57] , \la_data_out_user[56] , \la_data_out_user[55] , \la_data_out_user[54] , \la_data_out_user[53] , \la_data_out_user[52] , \la_data_out_user[51] , \la_data_out_user[50] , \la_data_out_user[49] , \la_data_out_user[48] , \la_data_out_user[47] , \la_data_out_user[46] , \la_data_out_user[45] , \la_data_out_user[44] , \la_data_out_user[43] , \la_data_out_user[42] , \la_data_out_user[41] , \la_data_out_user[40] , \la_data_out_user[39] , \la_data_out_user[38] , \la_data_out_user[37] , \la_data_out_user[36] , \la_data_out_user[35] , \la_data_out_user[34] , \la_data_out_user[33] , \la_data_out_user[32] , \la_data_out_user[31] , \la_data_out_user[30] , \la_data_out_user[29] , \la_data_out_user[28] , \la_data_out_user[27] , \la_data_out_user[26] , \la_data_out_user[25] , \la_data_out_user[24] , \la_data_out_user[23] , \la_data_out_user[22] , \la_data_out_user[21] , \la_data_out_user[20] , \la_data_out_user[19] , \la_data_out_user[18] , \la_data_out_user[17] , \la_data_out_user[16] , \la_data_out_user[15] , \la_data_out_user[14] , \la_data_out_user[13] , \la_data_out_user[12] , \la_data_out_user[11] , \la_data_out_user[10] , \la_data_out_user[9] , \la_data_out_user[8] , \la_data_out_user[7] , \la_data_out_user[6] , \la_data_out_user[5] , \la_data_out_user[4] , \la_data_out_user[3] , \la_data_out_user[2] , \la_data_out_user[1] , \la_data_out_user[0]  }),
+    .la_oenb({ \la_oenb_user[127] , \la_oenb_user[126] , \la_oenb_user[125] , \la_oenb_user[124] , \la_oenb_user[123] , \la_oenb_user[122] , \la_oenb_user[121] , \la_oenb_user[120] , \la_oenb_user[119] , \la_oenb_user[118] , \la_oenb_user[117] , \la_oenb_user[116] , \la_oenb_user[115] , \la_oenb_user[114] , \la_oenb_user[113] , \la_oenb_user[112] , \la_oenb_user[111] , \la_oenb_user[110] , \la_oenb_user[109] , \la_oenb_user[108] , \la_oenb_user[107] , \la_oenb_user[106] , \la_oenb_user[105] , \la_oenb_user[104] , \la_oenb_user[103] , \la_oenb_user[102] , \la_oenb_user[101] , \la_oenb_user[100] , \la_oenb_user[99] , \la_oenb_user[98] , \la_oenb_user[97] , \la_oenb_user[96] , \la_oenb_user[95] , \la_oenb_user[94] , \la_oenb_user[93] , \la_oenb_user[92] , \la_oenb_user[91] , \la_oenb_user[90] , \la_oenb_user[89] , \la_oenb_user[88] , \la_oenb_user[87] , \la_oenb_user[86] , \la_oenb_user[85] , \la_oenb_user[84] , \la_oenb_user[83] , \la_oenb_user[82] , \la_oenb_user[81] , \la_oenb_user[80] , \la_oenb_user[79] , \la_oenb_user[78] , \la_oenb_user[77] , \la_oenb_user[76] , \la_oenb_user[75] , \la_oenb_user[74] , \la_oenb_user[73] , \la_oenb_user[72] , \la_oenb_user[71] , \la_oenb_user[70] , \la_oenb_user[69] , \la_oenb_user[68] , \la_oenb_user[67] , \la_oenb_user[66] , \la_oenb_user[65] , \la_oenb_user[64] , \la_oenb_user[63] , \la_oenb_user[62] , \la_oenb_user[61] , \la_oenb_user[60] , \la_oenb_user[59] , \la_oenb_user[58] , \la_oenb_user[57] , \la_oenb_user[56] , \la_oenb_user[55] , \la_oenb_user[54] , \la_oenb_user[53] , \la_oenb_user[52] , \la_oenb_user[51] , \la_oenb_user[50] , \la_oenb_user[49] , \la_oenb_user[48] , \la_oenb_user[47] , \la_oenb_user[46] , \la_oenb_user[45] , \la_oenb_user[44] , \la_oenb_user[43] , \la_oenb_user[42] , \la_oenb_user[41] , \la_oenb_user[40] , \la_oenb_user[39] , \la_oenb_user[38] , \la_oenb_user[37] , \la_oenb_user[36] , \la_oenb_user[35] , \la_oenb_user[34] , \la_oenb_user[33] , \la_oenb_user[32] , \la_oenb_user[31] , \la_oenb_user[30] , \la_oenb_user[29] , \la_oenb_user[28] , \la_oenb_user[27] , \la_oenb_user[26] , \la_oenb_user[25] , \la_oenb_user[24] , \la_oenb_user[23] , \la_oenb_user[22] , \la_oenb_user[21] , \la_oenb_user[20] , \la_oenb_user[19] , \la_oenb_user[18] , \la_oenb_user[17] , \la_oenb_user[16] , \la_oenb_user[15] , \la_oenb_user[14] , \la_oenb_user[13] , \la_oenb_user[12] , \la_oenb_user[11] , \la_oenb_user[10] , \la_oenb_user[9] , \la_oenb_user[8] , \la_oenb_user[7] , \la_oenb_user[6] , \la_oenb_user[5] , \la_oenb_user[4] , \la_oenb_user[3] , \la_oenb_user[2] , \la_oenb_user[1] , \la_oenb_user[0]  }),
+    .user_clock2(mprj_clock2),
+    .user_irq({ \user_irq_core[2] , \user_irq_core[1] , \user_irq_core[0]  }),
+    .vccd1(vccd1_core),
+    .vccd2(vccd2_core),
+    .vdda1(vdda1_core),
+    .vdda2(vdda2_core),
+    .vssa1(vssa1_core),
+    .vssa2(vssa2_core),
+    .vssd1(vssd1_core),
+    .vssd2(vssd2_core),
+    .wb_clk_i(mprj_clock),
+    .wb_rst_i(mprj_reset),
+    .wbs_ack_o(mprj_ack_i_user),
+    .wbs_adr_i({ \mprj_adr_o_user[31] , \mprj_adr_o_user[30] , \mprj_adr_o_user[29] , \mprj_adr_o_user[28] , \mprj_adr_o_user[27] , \mprj_adr_o_user[26] , \mprj_adr_o_user[25] , \mprj_adr_o_user[24] , \mprj_adr_o_user[23] , \mprj_adr_o_user[22] , \mprj_adr_o_user[21] , \mprj_adr_o_user[20] , \mprj_adr_o_user[19] , \mprj_adr_o_user[18] , \mprj_adr_o_user[17] , \mprj_adr_o_user[16] , \mprj_adr_o_user[15] , \mprj_adr_o_user[14] , \mprj_adr_o_user[13] , \mprj_adr_o_user[12] , \mprj_adr_o_user[11] , \mprj_adr_o_user[10] , \mprj_adr_o_user[9] , \mprj_adr_o_user[8] , \mprj_adr_o_user[7] , \mprj_adr_o_user[6] , \mprj_adr_o_user[5] , \mprj_adr_o_user[4] , \mprj_adr_o_user[3] , \mprj_adr_o_user[2] , \mprj_adr_o_user[1] , \mprj_adr_o_user[0]  }),
+    .wbs_cyc_i(mprj_cyc_o_user),
+    .wbs_dat_i({ \mprj_dat_o_user[31] , \mprj_dat_o_user[30] , \mprj_dat_o_user[29] , \mprj_dat_o_user[28] , \mprj_dat_o_user[27] , \mprj_dat_o_user[26] , \mprj_dat_o_user[25] , \mprj_dat_o_user[24] , \mprj_dat_o_user[23] , \mprj_dat_o_user[22] , \mprj_dat_o_user[21] , \mprj_dat_o_user[20] , \mprj_dat_o_user[19] , \mprj_dat_o_user[18] , \mprj_dat_o_user[17] , \mprj_dat_o_user[16] , \mprj_dat_o_user[15] , \mprj_dat_o_user[14] , \mprj_dat_o_user[13] , \mprj_dat_o_user[12] , \mprj_dat_o_user[11] , \mprj_dat_o_user[10] , \mprj_dat_o_user[9] , \mprj_dat_o_user[8] , \mprj_dat_o_user[7] , \mprj_dat_o_user[6] , \mprj_dat_o_user[5] , \mprj_dat_o_user[4] , \mprj_dat_o_user[3] , \mprj_dat_o_user[2] , \mprj_dat_o_user[1] , \mprj_dat_o_user[0]  }),
+    .wbs_dat_o({ \mprj_dat_i_user[31] , \mprj_dat_i_user[30] , \mprj_dat_i_user[29] , \mprj_dat_i_user[28] , \mprj_dat_i_user[27] , \mprj_dat_i_user[26] , \mprj_dat_i_user[25] , \mprj_dat_i_user[24] , \mprj_dat_i_user[23] , \mprj_dat_i_user[22] , \mprj_dat_i_user[21] , \mprj_dat_i_user[20] , \mprj_dat_i_user[19] , \mprj_dat_i_user[18] , \mprj_dat_i_user[17] , \mprj_dat_i_user[16] , \mprj_dat_i_user[15] , \mprj_dat_i_user[14] , \mprj_dat_i_user[13] , \mprj_dat_i_user[12] , \mprj_dat_i_user[11] , \mprj_dat_i_user[10] , \mprj_dat_i_user[9] , \mprj_dat_i_user[8] , \mprj_dat_i_user[7] , \mprj_dat_i_user[6] , \mprj_dat_i_user[5] , \mprj_dat_i_user[4] , \mprj_dat_i_user[3] , \mprj_dat_i_user[2] , \mprj_dat_i_user[1] , \mprj_dat_i_user[0]  }),
+    .wbs_sel_i({ \mprj_sel_o_user[3] , \mprj_sel_o_user[2] , \mprj_sel_o_user[1] , \mprj_sel_o_user[0]  }),
+    .wbs_stb_i(mprj_stb_o_user),
+    .wbs_we_i(mprj_we_o_user)
+  );
+  chip_io padframe (
+    .clock(clock),
+    .clock_core(clock_core),
+    .flash_clk(flash_clk),
+    .flash_clk_core(flash_clk_frame),
+    .flash_clk_ieb_core(flash_clk_ieb),
+    .flash_clk_oeb_core(flash_clk_oeb),
+    .flash_csb(flash_csb),
+    .flash_csb_core(flash_csb_frame),
+    .flash_csb_ieb_core(flash_csb_ieb),
+    .flash_csb_oeb_core(flash_csb_oeb),
+    .flash_io0(flash_io0),
+    .flash_io0_di_core(flash_io0_di),
+    .flash_io0_do_core(flash_io0_do),
+    .flash_io0_ieb_core(flash_io0_ieb),
+    .flash_io0_oeb_core(flash_io0_oeb),
+    .flash_io1(flash_io1),
+    .flash_io1_di_core(flash_io1_di),
+    .flash_io1_do_core(flash_io1_do),
+    .flash_io1_ieb_core(flash_io1_ieb),
+    .flash_io1_oeb_core(flash_io1_oeb),
+    .gpio(gpio),
+    .gpio_in_core(gpio_in_core),
+    .gpio_inenb_core(gpio_inenb_core),
+    .gpio_mode0_core(gpio_mode0_core),
+    .gpio_mode1_core(gpio_mode1_core),
+    .gpio_out_core(gpio_out_core),
+    .gpio_outenb_core(gpio_outenb_core),
+    .mprj_analog_io({ \user_analog_io[28] , \user_analog_io[27] , \user_analog_io[26] , \user_analog_io[25] , \user_analog_io[24] , \user_analog_io[23] , \user_analog_io[22] , \user_analog_io[21] , \user_analog_io[20] , \user_analog_io[19] , \user_analog_io[18] , \user_analog_io[17] , \user_analog_io[16] , \user_analog_io[15] , \user_analog_io[14] , \user_analog_io[13] , \user_analog_io[12] , \user_analog_io[11] , \user_analog_io[10] , \user_analog_io[9] , \user_analog_io[8] , \user_analog_io[7] , \user_analog_io[6] , \user_analog_io[5] , \user_analog_io[4] , \user_analog_io[3] , \user_analog_io[2] , \user_analog_io[1] , \user_analog_io[0]  }),
+    .mprj_io(mprj_io),
+    .mprj_io_analog_en({ \mprj_io_analog_en[37] , \mprj_io_analog_en[36] , \mprj_io_analog_en[35] , \mprj_io_analog_en[34] , \mprj_io_analog_en[33] , \mprj_io_analog_en[32] , \mprj_io_analog_en[31] , \mprj_io_analog_en[30] , \mprj_io_analog_en[29] , \mprj_io_analog_en[28] , \mprj_io_analog_en[27] , \mprj_io_analog_en[26] , \mprj_io_analog_en[25] , \mprj_io_analog_en[24] , \mprj_io_analog_en[23] , \mprj_io_analog_en[22] , \mprj_io_analog_en[21] , \mprj_io_analog_en[20] , \mprj_io_analog_en[19] , \mprj_io_analog_en[18] , \mprj_io_analog_en[17] , \mprj_io_analog_en[16] , \mprj_io_analog_en[15] , \mprj_io_analog_en[14] , \mprj_io_analog_en[13] , \mprj_io_analog_en[12] , \mprj_io_analog_en[11] , \mprj_io_analog_en[10] , \mprj_io_analog_en[9] , \mprj_io_analog_en[8] , \mprj_io_analog_en[7] , \mprj_io_analog_en[6] , \mprj_io_analog_en[5] , \mprj_io_analog_en[4] , \mprj_io_analog_en[3] , \mprj_io_analog_en[2] , \mprj_io_analog_en[1] , \mprj_io_analog_en[0]  }),
+    .mprj_io_analog_pol({ \mprj_io_analog_pol[37] , \mprj_io_analog_pol[36] , \mprj_io_analog_pol[35] , \mprj_io_analog_pol[34] , \mprj_io_analog_pol[33] , \mprj_io_analog_pol[32] , \mprj_io_analog_pol[31] , \mprj_io_analog_pol[30] , \mprj_io_analog_pol[29] , \mprj_io_analog_pol[28] , \mprj_io_analog_pol[27] , \mprj_io_analog_pol[26] , \mprj_io_analog_pol[25] , \mprj_io_analog_pol[24] , \mprj_io_analog_pol[23] , \mprj_io_analog_pol[22] , \mprj_io_analog_pol[21] , \mprj_io_analog_pol[20] , \mprj_io_analog_pol[19] , \mprj_io_analog_pol[18] , \mprj_io_analog_pol[17] , \mprj_io_analog_pol[16] , \mprj_io_analog_pol[15] , \mprj_io_analog_pol[14] , \mprj_io_analog_pol[13] , \mprj_io_analog_pol[12] , \mprj_io_analog_pol[11] , \mprj_io_analog_pol[10] , \mprj_io_analog_pol[9] , \mprj_io_analog_pol[8] , \mprj_io_analog_pol[7] , \mprj_io_analog_pol[6] , \mprj_io_analog_pol[5] , \mprj_io_analog_pol[4] , \mprj_io_analog_pol[3] , \mprj_io_analog_pol[2] , \mprj_io_analog_pol[1] , \mprj_io_analog_pol[0]  }),
+    .mprj_io_analog_sel({ \mprj_io_analog_sel[37] , \mprj_io_analog_sel[36] , \mprj_io_analog_sel[35] , \mprj_io_analog_sel[34] , \mprj_io_analog_sel[33] , \mprj_io_analog_sel[32] , \mprj_io_analog_sel[31] , \mprj_io_analog_sel[30] , \mprj_io_analog_sel[29] , \mprj_io_analog_sel[28] , \mprj_io_analog_sel[27] , \mprj_io_analog_sel[26] , \mprj_io_analog_sel[25] , \mprj_io_analog_sel[24] , \mprj_io_analog_sel[23] , \mprj_io_analog_sel[22] , \mprj_io_analog_sel[21] , \mprj_io_analog_sel[20] , \mprj_io_analog_sel[19] , \mprj_io_analog_sel[18] , \mprj_io_analog_sel[17] , \mprj_io_analog_sel[16] , \mprj_io_analog_sel[15] , \mprj_io_analog_sel[14] , \mprj_io_analog_sel[13] , \mprj_io_analog_sel[12] , \mprj_io_analog_sel[11] , \mprj_io_analog_sel[10] , \mprj_io_analog_sel[9] , \mprj_io_analog_sel[8] , \mprj_io_analog_sel[7] , \mprj_io_analog_sel[6] , \mprj_io_analog_sel[5] , \mprj_io_analog_sel[4] , \mprj_io_analog_sel[3] , \mprj_io_analog_sel[2] , \mprj_io_analog_sel[1] , \mprj_io_analog_sel[0]  }),
+    .mprj_io_dm({ \mprj_io_dm[113] , \mprj_io_dm[112] , \mprj_io_dm[111] , \mprj_io_dm[110] , \mprj_io_dm[109] , \mprj_io_dm[108] , \mprj_io_dm[107] , \mprj_io_dm[106] , \mprj_io_dm[105] , \mprj_io_dm[104] , \mprj_io_dm[103] , \mprj_io_dm[102] , \mprj_io_dm[101] , \mprj_io_dm[100] , \mprj_io_dm[99] , \mprj_io_dm[98] , \mprj_io_dm[97] , \mprj_io_dm[96] , \mprj_io_dm[95] , \mprj_io_dm[94] , \mprj_io_dm[93] , \mprj_io_dm[92] , \mprj_io_dm[91] , \mprj_io_dm[90] , \mprj_io_dm[89] , \mprj_io_dm[88] , \mprj_io_dm[87] , \mprj_io_dm[86] , \mprj_io_dm[85] , \mprj_io_dm[84] , \mprj_io_dm[83] , \mprj_io_dm[82] , \mprj_io_dm[81] , \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78] , \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75] , \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72] , \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69] , \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66] , \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63] , \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60] , \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57] , \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54] , \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51] , \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48] , \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45] , \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42] , \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39] , \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36] , \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33] , \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30] , \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27] , \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24] , \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21] , \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18] , \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15] , \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12] , \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9] , \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6] , \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3] , \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0]  }),
+    .mprj_io_holdover({ \mprj_io_holdover[37] , \mprj_io_holdover[36] , \mprj_io_holdover[35] , \mprj_io_holdover[34] , \mprj_io_holdover[33] , \mprj_io_holdover[32] , \mprj_io_holdover[31] , \mprj_io_holdover[30] , \mprj_io_holdover[29] , \mprj_io_holdover[28] , \mprj_io_holdover[27] , \mprj_io_holdover[26] , \mprj_io_holdover[25] , \mprj_io_holdover[24] , \mprj_io_holdover[23] , \mprj_io_holdover[22] , \mprj_io_holdover[21] , \mprj_io_holdover[20] , \mprj_io_holdover[19] , \mprj_io_holdover[18] , \mprj_io_holdover[17] , \mprj_io_holdover[16] , \mprj_io_holdover[15] , \mprj_io_holdover[14] , \mprj_io_holdover[13] , \mprj_io_holdover[12] , \mprj_io_holdover[11] , \mprj_io_holdover[10] , \mprj_io_holdover[9] , \mprj_io_holdover[8] , \mprj_io_holdover[7] , \mprj_io_holdover[6] , \mprj_io_holdover[5] , \mprj_io_holdover[4] , \mprj_io_holdover[3] , \mprj_io_holdover[2] , \mprj_io_holdover[1] , \mprj_io_holdover[0]  }),
+    .mprj_io_ib_mode_sel({ \mprj_io_ib_mode_sel[37] , \mprj_io_ib_mode_sel[36] , \mprj_io_ib_mode_sel[35] , \mprj_io_ib_mode_sel[34] , \mprj_io_ib_mode_sel[33] , \mprj_io_ib_mode_sel[32] , \mprj_io_ib_mode_sel[31] , \mprj_io_ib_mode_sel[30] , \mprj_io_ib_mode_sel[29] , \mprj_io_ib_mode_sel[28] , \mprj_io_ib_mode_sel[27] , \mprj_io_ib_mode_sel[26] , \mprj_io_ib_mode_sel[25] , \mprj_io_ib_mode_sel[24] , \mprj_io_ib_mode_sel[23] , \mprj_io_ib_mode_sel[22] , \mprj_io_ib_mode_sel[21] , \mprj_io_ib_mode_sel[20] , \mprj_io_ib_mode_sel[19] , \mprj_io_ib_mode_sel[18] , \mprj_io_ib_mode_sel[17] , \mprj_io_ib_mode_sel[16] , \mprj_io_ib_mode_sel[15] , \mprj_io_ib_mode_sel[14] , \mprj_io_ib_mode_sel[13] , \mprj_io_ib_mode_sel[12] , \mprj_io_ib_mode_sel[11] , \mprj_io_ib_mode_sel[10] , \mprj_io_ib_mode_sel[9] , \mprj_io_ib_mode_sel[8] , \mprj_io_ib_mode_sel[7] , \mprj_io_ib_mode_sel[6] , \mprj_io_ib_mode_sel[5] , \mprj_io_ib_mode_sel[4] , \mprj_io_ib_mode_sel[3] , \mprj_io_ib_mode_sel[2] , \mprj_io_ib_mode_sel[1] , \mprj_io_ib_mode_sel[0]  }),
+    .mprj_io_in({ \mprj_io_in[37] , \mprj_io_in[36] , \mprj_io_in[35] , \mprj_io_in[34] , \mprj_io_in[33] , \mprj_io_in[32] , \mprj_io_in[31] , \mprj_io_in[30] , \mprj_io_in[29] , \mprj_io_in[28] , \mprj_io_in[27] , \mprj_io_in[26] , \mprj_io_in[25] , \mprj_io_in[24] , \mprj_io_in[23] , \mprj_io_in[22] , \mprj_io_in[21] , \mprj_io_in[20] , \mprj_io_in[19] , \mprj_io_in[18] , \mprj_io_in[17] , \mprj_io_in[16] , \mprj_io_in[15] , \mprj_io_in[14] , \mprj_io_in[13] , \mprj_io_in[12] , \mprj_io_in[11] , \mprj_io_in[10] , \mprj_io_in[9] , \mprj_io_in[8] , \mprj_io_in[7] , \mprj_io_in[6] , \mprj_io_in[5] , \mprj_io_in[4] , \mprj_io_in[3] , \mprj_io_in[2] , \mprj_io_in[1] , \mprj_io_in[0]  }),
+    .mprj_io_inp_dis({ \mprj_io_inp_dis[37] , \mprj_io_inp_dis[36] , \mprj_io_inp_dis[35] , \mprj_io_inp_dis[34] , \mprj_io_inp_dis[33] , \mprj_io_inp_dis[32] , \mprj_io_inp_dis[31] , \mprj_io_inp_dis[30] , \mprj_io_inp_dis[29] , \mprj_io_inp_dis[28] , \mprj_io_inp_dis[27] , \mprj_io_inp_dis[26] , \mprj_io_inp_dis[25] , \mprj_io_inp_dis[24] , \mprj_io_inp_dis[23] , \mprj_io_inp_dis[22] , \mprj_io_inp_dis[21] , \mprj_io_inp_dis[20] , \mprj_io_inp_dis[19] , \mprj_io_inp_dis[18] , \mprj_io_inp_dis[17] , \mprj_io_inp_dis[16] , \mprj_io_inp_dis[15] , \mprj_io_inp_dis[14] , \mprj_io_inp_dis[13] , \mprj_io_inp_dis[12] , \mprj_io_inp_dis[11] , \mprj_io_inp_dis[10] , \mprj_io_inp_dis[9] , \mprj_io_inp_dis[8] , \mprj_io_inp_dis[7] , \mprj_io_inp_dis[6] , \mprj_io_inp_dis[5] , \mprj_io_inp_dis[4] , \mprj_io_inp_dis[3] , \mprj_io_inp_dis[2] , \mprj_io_inp_dis[1] , \mprj_io_inp_dis[0]  }),
+    .mprj_io_oeb({ \mprj_io_oeb[37] , \mprj_io_oeb[36] , \mprj_io_oeb[35] , \mprj_io_oeb[34] , \mprj_io_oeb[33] , \mprj_io_oeb[32] , \mprj_io_oeb[31] , \mprj_io_oeb[30] , \mprj_io_oeb[29] , \mprj_io_oeb[28] , \mprj_io_oeb[27] , \mprj_io_oeb[26] , \mprj_io_oeb[25] , \mprj_io_oeb[24] , \mprj_io_oeb[23] , \mprj_io_oeb[22] , \mprj_io_oeb[21] , \mprj_io_oeb[20] , \mprj_io_oeb[19] , \mprj_io_oeb[18] , \mprj_io_oeb[17] , \mprj_io_oeb[16] , \mprj_io_oeb[15] , \mprj_io_oeb[14] , \mprj_io_oeb[13] , \mprj_io_oeb[12] , \mprj_io_oeb[11] , \mprj_io_oeb[10] , \mprj_io_oeb[9] , \mprj_io_oeb[8] , \mprj_io_oeb[7] , \mprj_io_oeb[6] , \mprj_io_oeb[5] , \mprj_io_oeb[4] , \mprj_io_oeb[3] , \mprj_io_oeb[2] , \mprj_io_oeb[1] , \mprj_io_oeb[0]  }),
+    .mprj_io_out({ \mprj_io_out[37] , \mprj_io_out[36] , \mprj_io_out[35] , \mprj_io_out[34] , \mprj_io_out[33] , \mprj_io_out[32] , \mprj_io_out[31] , \mprj_io_out[30] , \mprj_io_out[29] , \mprj_io_out[28] , \mprj_io_out[27] , \mprj_io_out[26] , \mprj_io_out[25] , \mprj_io_out[24] , \mprj_io_out[23] , \mprj_io_out[22] , \mprj_io_out[21] , \mprj_io_out[20] , \mprj_io_out[19] , \mprj_io_out[18] , \mprj_io_out[17] , \mprj_io_out[16] , \mprj_io_out[15] , \mprj_io_out[14] , \mprj_io_out[13] , \mprj_io_out[12] , \mprj_io_out[11] , \mprj_io_out[10] , \mprj_io_out[9] , \mprj_io_out[8] , \mprj_io_out[7] , \mprj_io_out[6] , \mprj_io_out[5] , \mprj_io_out[4] , \mprj_io_out[3] , \mprj_io_out[2] , \mprj_io_out[1] , \mprj_io_out[0]  }),
+    .mprj_io_slow_sel({ \mprj_io_slow_sel[37] , \mprj_io_slow_sel[36] , \mprj_io_slow_sel[35] , \mprj_io_slow_sel[34] , \mprj_io_slow_sel[33] , \mprj_io_slow_sel[32] , \mprj_io_slow_sel[31] , \mprj_io_slow_sel[30] , \mprj_io_slow_sel[29] , \mprj_io_slow_sel[28] , \mprj_io_slow_sel[27] , \mprj_io_slow_sel[26] , \mprj_io_slow_sel[25] , \mprj_io_slow_sel[24] , \mprj_io_slow_sel[23] , \mprj_io_slow_sel[22] , \mprj_io_slow_sel[21] , \mprj_io_slow_sel[20] , \mprj_io_slow_sel[19] , \mprj_io_slow_sel[18] , \mprj_io_slow_sel[17] , \mprj_io_slow_sel[16] , \mprj_io_slow_sel[15] , \mprj_io_slow_sel[14] , \mprj_io_slow_sel[13] , \mprj_io_slow_sel[12] , \mprj_io_slow_sel[11] , \mprj_io_slow_sel[10] , \mprj_io_slow_sel[9] , \mprj_io_slow_sel[8] , \mprj_io_slow_sel[7] , \mprj_io_slow_sel[6] , \mprj_io_slow_sel[5] , \mprj_io_slow_sel[4] , \mprj_io_slow_sel[3] , \mprj_io_slow_sel[2] , \mprj_io_slow_sel[1] , \mprj_io_slow_sel[0]  }),
+    .mprj_io_vtrip_sel({ \mprj_io_vtrip_sel[37] , \mprj_io_vtrip_sel[36] , \mprj_io_vtrip_sel[35] , \mprj_io_vtrip_sel[34] , \mprj_io_vtrip_sel[33] , \mprj_io_vtrip_sel[32] , \mprj_io_vtrip_sel[31] , \mprj_io_vtrip_sel[30] , \mprj_io_vtrip_sel[29] , \mprj_io_vtrip_sel[28] , \mprj_io_vtrip_sel[27] , \mprj_io_vtrip_sel[26] , \mprj_io_vtrip_sel[25] , \mprj_io_vtrip_sel[24] , \mprj_io_vtrip_sel[23] , \mprj_io_vtrip_sel[22] , \mprj_io_vtrip_sel[21] , \mprj_io_vtrip_sel[20] , \mprj_io_vtrip_sel[19] , \mprj_io_vtrip_sel[18] , \mprj_io_vtrip_sel[17] , \mprj_io_vtrip_sel[16] , \mprj_io_vtrip_sel[15] , \mprj_io_vtrip_sel[14] , \mprj_io_vtrip_sel[13] , \mprj_io_vtrip_sel[12] , \mprj_io_vtrip_sel[11] , \mprj_io_vtrip_sel[10] , \mprj_io_vtrip_sel[9] , \mprj_io_vtrip_sel[8] , \mprj_io_vtrip_sel[7] , \mprj_io_vtrip_sel[6] , \mprj_io_vtrip_sel[5] , \mprj_io_vtrip_sel[4] , \mprj_io_vtrip_sel[3] , \mprj_io_vtrip_sel[2] , \mprj_io_vtrip_sel[1] , \mprj_io_vtrip_sel[0]  }),
+    .por(por_l),
+    .porb_h(porb_h),
+    .resetb(resetb),
+    .resetb_core_h(rstb_h),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vccd1_pad(vccd1),
+    .vccd2(vccd2_core),
+    .vccd2_pad(vccd2),
+    .vccd_pad(vccd),
+    .vdda(vdda_core),
+    .vdda1(vdda1_core),
+    .vdda1_pad(vdda1),
+    .vdda1_pad2(vdda1_2),
+    .vdda2(vdda2_core),
+    .vdda2_pad(vdda2),
+    .vdda_pad(vdda),
+    .vddio(vddio_core),
+    .vddio_pad(vddio),
+    .vddio_pad2(vddio_2),
+    .vssa(vssa_core),
+    .vssa1(vssa1_core),
+    .vssa1_pad(vssa1),
+    .vssa1_pad2(vssa1_2),
+    .vssa2(vssa2_core),
+    .vssa2_pad(vssa2),
+    .vssa_pad(vssa),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .vssd1_pad(vssd1),
+    .vssd2(vssd2_core),
+    .vssd2_pad(vssd2),
+    .vssd_pad(vssd),
+    .vssio(vssio_core),
+    .vssio_pad(vssio),
+    .vssio_pad2(vssio_2)
+  );
+  digital_pll pll (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .clockp({ pll_clk, pll_clk90 }),
+    .dco(spi_pll_dco_ena),
+    .div({ \spi_pll_div[4] , \spi_pll_div[3] , \spi_pll_div[2] , \spi_pll_div[1] , \spi_pll_div[0]  }),
+    .enable(spi_pll_ena),
+    .ext_trim({ \spi_pll_trim[25] , \spi_pll_trim[24] , \spi_pll_trim[23] , \spi_pll_trim[22] , \spi_pll_trim[21] , \spi_pll_trim[20] , \spi_pll_trim[19] , \spi_pll_trim[18] , \spi_pll_trim[17] , \spi_pll_trim[16] , \spi_pll_trim[15] , \spi_pll_trim[14] , \spi_pll_trim[13] , \spi_pll_trim[12] , \spi_pll_trim[11] , \spi_pll_trim[10] , \spi_pll_trim[9] , \spi_pll_trim[8] , \spi_pll_trim[7] , \spi_pll_trim[6] , \spi_pll_trim[5] , \spi_pll_trim[4] , \spi_pll_trim[3] , \spi_pll_trim[2] , \spi_pll_trim[1] , \spi_pll_trim[0]  }),
+    .osc(clock_core),
+    .resetb(rstb_l)
+  );
+  simple_por por (
+    .por_l(por_l),
+    .porb_h(porb_h),
+    .porb_l(porb_l),
+    .vdd1v8(vccd_core),
+    .vdd3v3(vddio_core),
+    .vss3v3(vssio_core),
+    .vss1v8(vssd_core)
+  );
+  xres_buf rstb_level (
+    .A(rstb_h),
+    .LVGND(vssd_core),
+    .LVPWR(vccd_core),
+    .VGND(vssio_core),
+    .VPWR(vddio_core),
+    .X(rstb_l)
+  );
+  mgmt_core_wrapper soc (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .core_clk(caravel_clk),
+    .core_rstn(caravel_rstn),
+    .debug_in(debug_in),
+    .debug_mode(debug_mode),
+    .debug_oeb(debug_oeb),
+    .debug_out(debug_out),
+    .flash_clk(flash_clk_core),
+    .flash_csb(flash_csb_core),
+    .flash_io0_di(flash_io0_di_core),
+    .flash_io0_do(flash_io0_do_core),
+    .flash_io0_oeb(flash_io0_oeb_core),
+    .flash_io1_di(flash_io1_di_core),
+    .flash_io1_do(flash_io1_do_core),
+    .flash_io1_oeb(flash_io1_oeb_core),
+    .flash_io2_di(flash_io2_di_core),
+    .flash_io2_do(flash_io2_do_core),
+    .flash_io2_oeb(flash_io2_oeb_core),
+    .flash_io3_di(flash_io3_di_core),
+    .flash_io3_do(flash_io3_do_core),
+    .flash_io3_oeb(flash_io3_oeb_core),
+    .gpio_in_pad(gpio_in_core),
+    .gpio_inenb_pad(gpio_inenb_core),
+    .gpio_mode0_pad(gpio_mode0_core),
+    .gpio_mode1_pad(gpio_mode1_core),
+    .gpio_out_pad(gpio_out_core),
+    .gpio_outenb_pad(gpio_outenb_core),
+    .hk_ack_i(hk_ack_i),
+    .hk_dat_i({ \hk_dat_i[31] , \hk_dat_i[30] , \hk_dat_i[29] , \hk_dat_i[28] , \hk_dat_i[27] , \hk_dat_i[26] , \hk_dat_i[25] , \hk_dat_i[24] , \hk_dat_i[23] , \hk_dat_i[22] , \hk_dat_i[21] , \hk_dat_i[20] , \hk_dat_i[19] , \hk_dat_i[18] , \hk_dat_i[17] , \hk_dat_i[16] , \hk_dat_i[15] , \hk_dat_i[14] , \hk_dat_i[13] , \hk_dat_i[12] , \hk_dat_i[11] , \hk_dat_i[10] , \hk_dat_i[9] , \hk_dat_i[8] , \hk_dat_i[7] , \hk_dat_i[6] , \hk_dat_i[5] , \hk_dat_i[4] , \hk_dat_i[3] , \hk_dat_i[2] , \hk_dat_i[1] , \hk_dat_i[0]  }),
+    .hk_stb_o(hk_stb_o),
+    .hk_cyc_o(hk_cyc_o),
+    .irq({ \irq_spi[2] , \irq_spi[1] , \irq_spi[0] , \user_irq[2] , \user_irq[1] , \user_irq[0]  }),
+    .la_iena({ \la_iena_mprj[127] , \la_iena_mprj[126] , \la_iena_mprj[125] , \la_iena_mprj[124] , \la_iena_mprj[123] , \la_iena_mprj[122] , \la_iena_mprj[121] , \la_iena_mprj[120] , \la_iena_mprj[119] , \la_iena_mprj[118] , \la_iena_mprj[117] , \la_iena_mprj[116] , \la_iena_mprj[115] , \la_iena_mprj[114] , \la_iena_mprj[113] , \la_iena_mprj[112] , \la_iena_mprj[111] , \la_iena_mprj[110] , \la_iena_mprj[109] , \la_iena_mprj[108] , \la_iena_mprj[107] , \la_iena_mprj[106] , \la_iena_mprj[105] , \la_iena_mprj[104] , \la_iena_mprj[103] , \la_iena_mprj[102] , \la_iena_mprj[101] , \la_iena_mprj[100] , \la_iena_mprj[99] , \la_iena_mprj[98] , \la_iena_mprj[97] , \la_iena_mprj[96] , \la_iena_mprj[95] , \la_iena_mprj[94] , \la_iena_mprj[93] , \la_iena_mprj[92] , \la_iena_mprj[91] , \la_iena_mprj[90] , \la_iena_mprj[89] , \la_iena_mprj[88] , \la_iena_mprj[87] , \la_iena_mprj[86] , \la_iena_mprj[85] , \la_iena_mprj[84] , \la_iena_mprj[83] , \la_iena_mprj[82] , \la_iena_mprj[81] , \la_iena_mprj[80] , \la_iena_mprj[79] , \la_iena_mprj[78] , \la_iena_mprj[77] , \la_iena_mprj[76] , \la_iena_mprj[75] , \la_iena_mprj[74] , \la_iena_mprj[73] , \la_iena_mprj[72] , \la_iena_mprj[71] , \la_iena_mprj[70] , \la_iena_mprj[69] , \la_iena_mprj[68] , \la_iena_mprj[67] , \la_iena_mprj[66] , \la_iena_mprj[65] , \la_iena_mprj[64] , \la_iena_mprj[63] , \la_iena_mprj[62] , \la_iena_mprj[61] , \la_iena_mprj[60] , \la_iena_mprj[59] , \la_iena_mprj[58] , \la_iena_mprj[57] , \la_iena_mprj[56] , \la_iena_mprj[55] , \la_iena_mprj[54] , \la_iena_mprj[53] , \la_iena_mprj[52] , \la_iena_mprj[51] , \la_iena_mprj[50] , \la_iena_mprj[49] , \la_iena_mprj[48] , \la_iena_mprj[47] , \la_iena_mprj[46] , \la_iena_mprj[45] , \la_iena_mprj[44] , \la_iena_mprj[43] , \la_iena_mprj[42] , \la_iena_mprj[41] , \la_iena_mprj[40] , \la_iena_mprj[39] , \la_iena_mprj[38] , \la_iena_mprj[37] , \la_iena_mprj[36] , \la_iena_mprj[35] , \la_iena_mprj[34] , \la_iena_mprj[33] , \la_iena_mprj[32] , \la_iena_mprj[31] , \la_iena_mprj[30] , \la_iena_mprj[29] , \la_iena_mprj[28] , \la_iena_mprj[27] , \la_iena_mprj[26] , \la_iena_mprj[25] , \la_iena_mprj[24] , \la_iena_mprj[23] , \la_iena_mprj[22] , \la_iena_mprj[21] , \la_iena_mprj[20] , \la_iena_mprj[19] , \la_iena_mprj[18] , \la_iena_mprj[17] , \la_iena_mprj[16] , \la_iena_mprj[15] , \la_iena_mprj[14] , \la_iena_mprj[13] , \la_iena_mprj[12] , \la_iena_mprj[11] , \la_iena_mprj[10] , \la_iena_mprj[9] , \la_iena_mprj[8] , \la_iena_mprj[7] , \la_iena_mprj[6] , \la_iena_mprj[5] , \la_iena_mprj[4] , \la_iena_mprj[3] , \la_iena_mprj[2] , \la_iena_mprj[1] , \la_iena_mprj[0]  }),
+    .la_input({ \la_data_in_mprj[127] , \la_data_in_mprj[126] , \la_data_in_mprj[125] , \la_data_in_mprj[124] , \la_data_in_mprj[123] , \la_data_in_mprj[122] , \la_data_in_mprj[121] , \la_data_in_mprj[120] , \la_data_in_mprj[119] , \la_data_in_mprj[118] , \la_data_in_mprj[117] , \la_data_in_mprj[116] , \la_data_in_mprj[115] , \la_data_in_mprj[114] , \la_data_in_mprj[113] , \la_data_in_mprj[112] , \la_data_in_mprj[111] , \la_data_in_mprj[110] , \la_data_in_mprj[109] , \la_data_in_mprj[108] , \la_data_in_mprj[107] , \la_data_in_mprj[106] , \la_data_in_mprj[105] , \la_data_in_mprj[104] , \la_data_in_mprj[103] , \la_data_in_mprj[102] , \la_data_in_mprj[101] , \la_data_in_mprj[100] , \la_data_in_mprj[99] , \la_data_in_mprj[98] , \la_data_in_mprj[97] , \la_data_in_mprj[96] , \la_data_in_mprj[95] , \la_data_in_mprj[94] , \la_data_in_mprj[93] , \la_data_in_mprj[92] , \la_data_in_mprj[91] , \la_data_in_mprj[90] , \la_data_in_mprj[89] , \la_data_in_mprj[88] , \la_data_in_mprj[87] , \la_data_in_mprj[86] , \la_data_in_mprj[85] , \la_data_in_mprj[84] , \la_data_in_mprj[83] , \la_data_in_mprj[82] , \la_data_in_mprj[81] , \la_data_in_mprj[80] , \la_data_in_mprj[79] , \la_data_in_mprj[78] , \la_data_in_mprj[77] , \la_data_in_mprj[76] , \la_data_in_mprj[75] , \la_data_in_mprj[74] , \la_data_in_mprj[73] , \la_data_in_mprj[72] , \la_data_in_mprj[71] , \la_data_in_mprj[70] , \la_data_in_mprj[69] , \la_data_in_mprj[68] , \la_data_in_mprj[67] , \la_data_in_mprj[66] , \la_data_in_mprj[65] , \la_data_in_mprj[64] , \la_data_in_mprj[63] , \la_data_in_mprj[62] , \la_data_in_mprj[61] , \la_data_in_mprj[60] , \la_data_in_mprj[59] , \la_data_in_mprj[58] , \la_data_in_mprj[57] , \la_data_in_mprj[56] , \la_data_in_mprj[55] , \la_data_in_mprj[54] , \la_data_in_mprj[53] , \la_data_in_mprj[52] , \la_data_in_mprj[51] , \la_data_in_mprj[50] , \la_data_in_mprj[49] , \la_data_in_mprj[48] , \la_data_in_mprj[47] , \la_data_in_mprj[46] , \la_data_in_mprj[45] , \la_data_in_mprj[44] , \la_data_in_mprj[43] , \la_data_in_mprj[42] , \la_data_in_mprj[41] , \la_data_in_mprj[40] , \la_data_in_mprj[39] , \la_data_in_mprj[38] , \la_data_in_mprj[37] , \la_data_in_mprj[36] , \la_data_in_mprj[35] , \la_data_in_mprj[34] , \la_data_in_mprj[33] , \la_data_in_mprj[32] , \la_data_in_mprj[31] , \la_data_in_mprj[30] , \la_data_in_mprj[29] , \la_data_in_mprj[28] , \la_data_in_mprj[27] , \la_data_in_mprj[26] , \la_data_in_mprj[25] , \la_data_in_mprj[24] , \la_data_in_mprj[23] , \la_data_in_mprj[22] , \la_data_in_mprj[21] , \la_data_in_mprj[20] , \la_data_in_mprj[19] , \la_data_in_mprj[18] , \la_data_in_mprj[17] , \la_data_in_mprj[16] , \la_data_in_mprj[15] , \la_data_in_mprj[14] , \la_data_in_mprj[13] , \la_data_in_mprj[12] , \la_data_in_mprj[11] , \la_data_in_mprj[10] , \la_data_in_mprj[9] , \la_data_in_mprj[8] , \la_data_in_mprj[7] , \la_data_in_mprj[6] , \la_data_in_mprj[5] , \la_data_in_mprj[4] , \la_data_in_mprj[3] , \la_data_in_mprj[2] , \la_data_in_mprj[1] , \la_data_in_mprj[0]  }),
+    .la_oenb({ \la_oenb_mprj[127] , \la_oenb_mprj[126] , \la_oenb_mprj[125] , \la_oenb_mprj[124] , \la_oenb_mprj[123] , \la_oenb_mprj[122] , \la_oenb_mprj[121] , \la_oenb_mprj[120] , \la_oenb_mprj[119] , \la_oenb_mprj[118] , \la_oenb_mprj[117] , \la_oenb_mprj[116] , \la_oenb_mprj[115] , \la_oenb_mprj[114] , \la_oenb_mprj[113] , \la_oenb_mprj[112] , \la_oenb_mprj[111] , \la_oenb_mprj[110] , \la_oenb_mprj[109] , \la_oenb_mprj[108] , \la_oenb_mprj[107] , \la_oenb_mprj[106] , \la_oenb_mprj[105] , \la_oenb_mprj[104] , \la_oenb_mprj[103] , \la_oenb_mprj[102] , \la_oenb_mprj[101] , \la_oenb_mprj[100] , \la_oenb_mprj[99] , \la_oenb_mprj[98] , \la_oenb_mprj[97] , \la_oenb_mprj[96] , \la_oenb_mprj[95] , \la_oenb_mprj[94] , \la_oenb_mprj[93] , \la_oenb_mprj[92] , \la_oenb_mprj[91] , \la_oenb_mprj[90] , \la_oenb_mprj[89] , \la_oenb_mprj[88] , \la_oenb_mprj[87] , \la_oenb_mprj[86] , \la_oenb_mprj[85] , \la_oenb_mprj[84] , \la_oenb_mprj[83] , \la_oenb_mprj[82] , \la_oenb_mprj[81] , \la_oenb_mprj[80] , \la_oenb_mprj[79] , \la_oenb_mprj[78] , \la_oenb_mprj[77] , \la_oenb_mprj[76] , \la_oenb_mprj[75] , \la_oenb_mprj[74] , \la_oenb_mprj[73] , \la_oenb_mprj[72] , \la_oenb_mprj[71] , \la_oenb_mprj[70] , \la_oenb_mprj[69] , \la_oenb_mprj[68] , \la_oenb_mprj[67] , \la_oenb_mprj[66] , \la_oenb_mprj[65] , \la_oenb_mprj[64] , \la_oenb_mprj[63] , \la_oenb_mprj[62] , \la_oenb_mprj[61] , \la_oenb_mprj[60] , \la_oenb_mprj[59] , \la_oenb_mprj[58] , \la_oenb_mprj[57] , \la_oenb_mprj[56] , \la_oenb_mprj[55] , \la_oenb_mprj[54] , \la_oenb_mprj[53] , \la_oenb_mprj[52] , \la_oenb_mprj[51] , \la_oenb_mprj[50] , \la_oenb_mprj[49] , \la_oenb_mprj[48] , \la_oenb_mprj[47] , \la_oenb_mprj[46] , \la_oenb_mprj[45] , \la_oenb_mprj[44] , \la_oenb_mprj[43] , \la_oenb_mprj[42] , \la_oenb_mprj[41] , \la_oenb_mprj[40] , \la_oenb_mprj[39] , \la_oenb_mprj[38] , \la_oenb_mprj[37] , \la_oenb_mprj[36] , \la_oenb_mprj[35] , \la_oenb_mprj[34] , \la_oenb_mprj[33] , \la_oenb_mprj[32] , \la_oenb_mprj[31] , \la_oenb_mprj[30] , \la_oenb_mprj[29] , \la_oenb_mprj[28] , \la_oenb_mprj[27] , \la_oenb_mprj[26] , \la_oenb_mprj[25] , \la_oenb_mprj[24] , \la_oenb_mprj[23] , \la_oenb_mprj[22] , \la_oenb_mprj[21] , \la_oenb_mprj[20] , \la_oenb_mprj[19] , \la_oenb_mprj[18] , \la_oenb_mprj[17] , \la_oenb_mprj[16] , \la_oenb_mprj[15] , \la_oenb_mprj[14] , \la_oenb_mprj[13] , \la_oenb_mprj[12] , \la_oenb_mprj[11] , \la_oenb_mprj[10] , \la_oenb_mprj[9] , \la_oenb_mprj[8] , \la_oenb_mprj[7] , \la_oenb_mprj[6] , \la_oenb_mprj[5] , \la_oenb_mprj[4] , \la_oenb_mprj[3] , \la_oenb_mprj[2] , \la_oenb_mprj[1] , \la_oenb_mprj[0]  }),
+    .la_output({ \la_data_out_mprj[127] , \la_data_out_mprj[126] , \la_data_out_mprj[125] , \la_data_out_mprj[124] , \la_data_out_mprj[123] , \la_data_out_mprj[122] , \la_data_out_mprj[121] , \la_data_out_mprj[120] , \la_data_out_mprj[119] , \la_data_out_mprj[118] , \la_data_out_mprj[117] , \la_data_out_mprj[116] , \la_data_out_mprj[115] , \la_data_out_mprj[114] , \la_data_out_mprj[113] , \la_data_out_mprj[112] , \la_data_out_mprj[111] , \la_data_out_mprj[110] , \la_data_out_mprj[109] , \la_data_out_mprj[108] , \la_data_out_mprj[107] , \la_data_out_mprj[106] , \la_data_out_mprj[105] , \la_data_out_mprj[104] , \la_data_out_mprj[103] , \la_data_out_mprj[102] , \la_data_out_mprj[101] , \la_data_out_mprj[100] , \la_data_out_mprj[99] , \la_data_out_mprj[98] , \la_data_out_mprj[97] , \la_data_out_mprj[96] , \la_data_out_mprj[95] , \la_data_out_mprj[94] , \la_data_out_mprj[93] , \la_data_out_mprj[92] , \la_data_out_mprj[91] , \la_data_out_mprj[90] , \la_data_out_mprj[89] , \la_data_out_mprj[88] , \la_data_out_mprj[87] , \la_data_out_mprj[86] , \la_data_out_mprj[85] , \la_data_out_mprj[84] , \la_data_out_mprj[83] , \la_data_out_mprj[82] , \la_data_out_mprj[81] , \la_data_out_mprj[80] , \la_data_out_mprj[79] , \la_data_out_mprj[78] , \la_data_out_mprj[77] , \la_data_out_mprj[76] , \la_data_out_mprj[75] , \la_data_out_mprj[74] , \la_data_out_mprj[73] , \la_data_out_mprj[72] , \la_data_out_mprj[71] , \la_data_out_mprj[70] , \la_data_out_mprj[69] , \la_data_out_mprj[68] , \la_data_out_mprj[67] , \la_data_out_mprj[66] , \la_data_out_mprj[65] , \la_data_out_mprj[64] , \la_data_out_mprj[63] , \la_data_out_mprj[62] , \la_data_out_mprj[61] , \la_data_out_mprj[60] , \la_data_out_mprj[59] , \la_data_out_mprj[58] , \la_data_out_mprj[57] , \la_data_out_mprj[56] , \la_data_out_mprj[55] , \la_data_out_mprj[54] , \la_data_out_mprj[53] , \la_data_out_mprj[52] , \la_data_out_mprj[51] , \la_data_out_mprj[50] , \la_data_out_mprj[49] , \la_data_out_mprj[48] , \la_data_out_mprj[47] , \la_data_out_mprj[46] , \la_data_out_mprj[45] , \la_data_out_mprj[44] , \la_data_out_mprj[43] , \la_data_out_mprj[42] , \la_data_out_mprj[41] , \la_data_out_mprj[40] , \la_data_out_mprj[39] , \la_data_out_mprj[38] , \la_data_out_mprj[37] , \la_data_out_mprj[36] , \la_data_out_mprj[35] , \la_data_out_mprj[34] , \la_data_out_mprj[33] , \la_data_out_mprj[32] , \la_data_out_mprj[31] , \la_data_out_mprj[30] , \la_data_out_mprj[29] , \la_data_out_mprj[28] , \la_data_out_mprj[27] , \la_data_out_mprj[26] , \la_data_out_mprj[25] , \la_data_out_mprj[24] , \la_data_out_mprj[23] , \la_data_out_mprj[22] , \la_data_out_mprj[21] , \la_data_out_mprj[20] , \la_data_out_mprj[19] , \la_data_out_mprj[18] , \la_data_out_mprj[17] , \la_data_out_mprj[16] , \la_data_out_mprj[15] , \la_data_out_mprj[14] , \la_data_out_mprj[13] , \la_data_out_mprj[12] , \la_data_out_mprj[11] , \la_data_out_mprj[10] , \la_data_out_mprj[9] , \la_data_out_mprj[8] , \la_data_out_mprj[7] , \la_data_out_mprj[6] , \la_data_out_mprj[5] , \la_data_out_mprj[4] , \la_data_out_mprj[3] , \la_data_out_mprj[2] , \la_data_out_mprj[1] , \la_data_out_mprj[0]  }),
+    .mprj_ack_i(mprj_ack_i_core),
+    .mprj_adr_o({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0]  }),
+    .mprj_cyc_o(mprj_cyc_o_core),
+    .mprj_dat_i({ \mprj_dat_i_core[31] , \mprj_dat_i_core[30] , \mprj_dat_i_core[29] , \mprj_dat_i_core[28] , \mprj_dat_i_core[27] , \mprj_dat_i_core[26] , \mprj_dat_i_core[25] , \mprj_dat_i_core[24] , \mprj_dat_i_core[23] , \mprj_dat_i_core[22] , \mprj_dat_i_core[21] , \mprj_dat_i_core[20] , \mprj_dat_i_core[19] , \mprj_dat_i_core[18] , \mprj_dat_i_core[17] , \mprj_dat_i_core[16] , \mprj_dat_i_core[15] , \mprj_dat_i_core[14] , \mprj_dat_i_core[13] , \mprj_dat_i_core[12] , \mprj_dat_i_core[11] , \mprj_dat_i_core[10] , \mprj_dat_i_core[9] , \mprj_dat_i_core[8] , \mprj_dat_i_core[7] , \mprj_dat_i_core[6] , \mprj_dat_i_core[5] , \mprj_dat_i_core[4] , \mprj_dat_i_core[3] , \mprj_dat_i_core[2] , \mprj_dat_i_core[1] , \mprj_dat_i_core[0]  }),
+    .mprj_dat_o({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0]  }),
+    .mprj_sel_o({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0]  }),
+    .mprj_stb_o(mprj_stb_o_core),
+    .mprj_wb_iena(mprj_iena_wb),
+    .mprj_we_o(mprj_we_o_core),
+    .qspi_enabled(qspi_enabled),
+    .ser_rx(ser_rx),
+    .ser_tx(ser_tx),
+    .spi_csb(spi_csb),
+    .spi_enabled(spi_enabled),
+    .spi_sck(spi_sck),
+    .spi_sdi(spi_sdi),
+    .spi_sdo(spi_sdo),
+    .spi_sdoenb(spi_sdoenb),
+    .sram_ro_addr({ \hkspi_sram_addr[7] , \hkspi_sram_addr[6] , \hkspi_sram_addr[5] , \hkspi_sram_addr[4] , \hkspi_sram_addr[3] , \hkspi_sram_addr[2] , \hkspi_sram_addr[1] , \hkspi_sram_addr[0]  }),
+    .sram_ro_clk(hkspi_sram_clk),
+    .sram_ro_csb(hkspi_sram_csb),
+    .sram_ro_data({ \hkspi_sram_data[31] , \hkspi_sram_data[30] , \hkspi_sram_data[29] , \hkspi_sram_data[28] , \hkspi_sram_data[27] , \hkspi_sram_data[26] , \hkspi_sram_data[25] , \hkspi_sram_data[24] , \hkspi_sram_data[23] , \hkspi_sram_data[22] , \hkspi_sram_data[21] , \hkspi_sram_data[20] , \hkspi_sram_data[19] , \hkspi_sram_data[18] , \hkspi_sram_data[17] , \hkspi_sram_data[16] , \hkspi_sram_data[15] , \hkspi_sram_data[14] , \hkspi_sram_data[13] , \hkspi_sram_data[12] , \hkspi_sram_data[11] , \hkspi_sram_data[10] , \hkspi_sram_data[9] , \hkspi_sram_data[8] , \hkspi_sram_data[7] , \hkspi_sram_data[6] , \hkspi_sram_data[5] , \hkspi_sram_data[4] , \hkspi_sram_data[3] , \hkspi_sram_data[2] , \hkspi_sram_data[1] , \hkspi_sram_data[0]  }),
+    .trap(trap),
+    .uart_enabled(uart_enabled),
+    .user_irq_ena({ \user_irq_ena[2] , \user_irq_ena[1] , \user_irq_ena[0]  })
+  );
+  user_id_programming user_id_value (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .mask_rev({ \mask_rev[31] , \mask_rev[30] , \mask_rev[29] , \mask_rev[28] , \mask_rev[27] , \mask_rev[26] , \mask_rev[25] , \mask_rev[24] , \mask_rev[23] , \mask_rev[22] , \mask_rev[21] , \mask_rev[20] , \mask_rev[19] , \mask_rev[18] , \mask_rev[17] , \mask_rev[16] , \mask_rev[15] , \mask_rev[14] , \mask_rev[13] , \mask_rev[12] , \mask_rev[11] , \mask_rev[10] , \mask_rev[9] , \mask_rev[8] , \mask_rev[7] , \mask_rev[6] , \mask_rev[5] , \mask_rev[4] , \mask_rev[3] , \mask_rev[2] , \mask_rev[1] , \mask_rev[0]  })
+  );
+  spare_logic_block \spare_logic[0]  (
+    .vssd(vssd_core),
+    .vccd(vccd_core),
+    .spare_xz(),
+    .spare_xi(),
+    .spare_xib(),
+    .spare_xna(),
+    .spare_xno(),
+    .spare_xmx(),
+    .spare_xfq(),
+    .spare_xfqn()
+  );
+  spare_logic_block \spare_logic[1]  (
+    .vssd(vssd_core),
+    .vccd(vccd_core),
+    .spare_xz(),
+    .spare_xi(),
+    .spare_xib(),
+    .spare_xna(),
+    .spare_xno(),
+    .spare_xmx(),
+    .spare_xfq(),
+    .spare_xfqn()
+  );
+  spare_logic_block \spare_logic[2]  (
+    .vssd(vssd_core),
+    .vccd(vccd_core),
+    .spare_xz(),
+    .spare_xi(),
+    .spare_xib(),
+    .spare_xna(),
+    .spare_xno(),
+    .spare_xmx(),
+    .spare_xfq(),
+    .spare_xfqn()
+  );
+  spare_logic_block \spare_logic[3]  (
+    .vssd(vssd_core),
+    .vccd(vccd_core),
+    .spare_xz(),
+    .spare_xi(),
+    .spare_xib(),
+    .spare_xna(),
+    .spare_xno(),
+    .spare_xmx(),
+    .spare_xfq(),
+    .spare_xfqn()
+  );
+
+  assign \gpio_resetn_1_shifted[14]  = \gpio_resetn_1[13] ;
+  assign \gpio_resetn_1_shifted[13]  = \gpio_resetn_1[12] ;
+  assign \gpio_resetn_1_shifted[12]  = \gpio_resetn_1[11] ;
+  assign \gpio_resetn_1_shifted[11]  = \gpio_resetn_1[10] ;
+  assign \gpio_resetn_1_shifted[10]  = \gpio_resetn_1[9] ;
+  assign \gpio_resetn_1_shifted[9]  = \gpio_resetn_1[8] ;
+  assign \gpio_resetn_1_shifted[8]  = \gpio_resetn_1[7] ;
+  assign \gpio_resetn_1_shifted[7]  = \gpio_resetn_1[6] ;
+  assign \gpio_resetn_1_shifted[6]  = \gpio_resetn_1[5] ;
+  assign \gpio_resetn_1_shifted[5]  = \gpio_resetn_1[4] ;
+  assign \gpio_resetn_1_shifted[4]  = \gpio_resetn_1[3] ;
+  assign \gpio_resetn_1_shifted[3]  = \gpio_resetn_1[2] ;
+  assign \gpio_resetn_1_shifted[2]  = \gpio_resetn_1[1] ;
+  assign \gpio_resetn_1_shifted[1]  = \gpio_resetn_1[0] ;
+  assign \gpio_load_1_shifted[18]  = \gpio_load_1[17] ;
+  assign \gpio_load_1_shifted[17]  = \gpio_load_1[16] ;
+  assign \gpio_load_1_shifted[16]  = \gpio_load_1[15] ;
+  assign \gpio_load_1_shifted[15]  = \gpio_load_1[14] ;
+  assign \gpio_load_1_shifted[14]  = \gpio_load_1[13] ;
+  assign \gpio_load_1_shifted[13]  = \gpio_load_1[12] ;
+  assign \gpio_load_1_shifted[12]  = \gpio_load_1[11] ;
+  assign \gpio_load_1_shifted[11]  = \gpio_load_1[10] ;
+  assign \gpio_load_1_shifted[10]  = \gpio_load_1[9] ;
+  assign \gpio_load_1_shifted[9]  = \gpio_load_1[8] ;
+  assign \gpio_load_1_shifted[8]  = \gpio_load_1[7] ;
+  assign \gpio_load_1_shifted[7]  = \gpio_load_1[6] ;
+  assign \gpio_load_1_shifted[6]  = \gpio_load_1[5] ;
+  assign \gpio_load_1_shifted[5]  = \gpio_load_1[4] ;
+  assign \gpio_load_1_shifted[4]  = \gpio_load_1[3] ;
+  assign \gpio_load_1_shifted[3]  = \gpio_load_1[2] ;
+  assign \gpio_load_1_shifted[2]  = \gpio_load_1[1] ;
+  assign \gpio_load_1_shifted[1]  = \gpio_load_1[0] ;
+  assign \gpio_load_2_shifted[18]  = \gpio_load_1_shifted[0] ;
+  assign \gpio_load_2_shifted[17]  = \gpio_load_2[18] ;
+  assign \gpio_load_2_shifted[16]  = \gpio_load_2[17] ;
+  assign \gpio_load_2_shifted[15]  = \gpio_load_2[16] ;
+  assign \gpio_load_2_shifted[14]  = \gpio_load_2[15] ;
+  assign \gpio_load_2_shifted[13]  = \gpio_load_2[14] ;
+  assign \gpio_load_2_shifted[12]  = \gpio_load_2[13] ;
+  assign \gpio_load_2_shifted[11]  = \gpio_load_2[12] ;
+  assign \gpio_load_2_shifted[10]  = \gpio_load_2[11] ;
+  assign \gpio_load_2_shifted[9]  = \gpio_load_2[10] ;
+  assign \gpio_load_2_shifted[8]  = \gpio_load_2[9] ;
+  assign \gpio_load_2_shifted[7]  = \gpio_load_2[8] ;
+  assign \gpio_load_2_shifted[6]  = \gpio_load_2[7] ;
+  assign \gpio_load_2_shifted[5]  = \gpio_load_2[6] ;
+  assign \gpio_load_2_shifted[4]  = \gpio_load_2[5] ;
+  assign \gpio_load_2_shifted[3]  = \gpio_load_2[4] ;
+  assign \gpio_load_2_shifted[2]  = \gpio_load_2[3] ;
+  assign \gpio_load_2_shifted[1]  = \gpio_load_2[2] ;
+  assign \gpio_load_2_shifted[0]  = \gpio_load_2[1] ;
+  assign \gpio_resetn_2_shifted[18]  = \gpio_resetn_1_shifted[0] ;
+  assign \gpio_resetn_2_shifted[17]  = \gpio_resetn_2[18] ;
+  assign \gpio_resetn_2_shifted[16]  = \gpio_resetn_2[17] ;
+  assign \gpio_resetn_2_shifted[15]  = \gpio_resetn_2[16] ;
+  assign \gpio_resetn_2_shifted[14]  = \gpio_resetn_2[15] ;
+  assign \gpio_resetn_2_shifted[13]  = \gpio_resetn_2[14] ;
+  assign \gpio_resetn_2_shifted[12]  = \gpio_resetn_2[13] ;
+  assign \gpio_resetn_2_shifted[11]  = \gpio_resetn_2[12] ;
+  assign \gpio_resetn_2_shifted[10]  = \gpio_resetn_2[11] ;
+  assign \gpio_resetn_2_shifted[9]  = \gpio_resetn_2[10] ;
+  assign \gpio_resetn_2_shifted[8]  = \gpio_resetn_2[9] ;
+  assign \gpio_resetn_2_shifted[7]  = \gpio_resetn_2[8] ;
+  assign \gpio_resetn_2_shifted[6]  = \gpio_resetn_2[7] ;
+  assign \gpio_resetn_2_shifted[5]  = \gpio_resetn_2[6] ;
+  assign \gpio_resetn_2_shifted[4]  = \gpio_resetn_2[5] ;
+  assign \gpio_resetn_2_shifted[3]  = \gpio_resetn_2[4] ;
+  assign \gpio_resetn_2_shifted[2]  = \gpio_resetn_2[3] ;
+  assign \gpio_resetn_2_shifted[1]  = \gpio_resetn_2[2] ;
+  assign \gpio_resetn_2_shifted[0]  = \gpio_resetn_2[1] ;
+  assign \gpio_serial_link_2_shifted[17]  = \gpio_serial_link_2[18] ;
+  assign \gpio_serial_link_2_shifted[16]  = \gpio_serial_link_2[17] ;
+  assign \gpio_serial_link_2_shifted[15]  = \gpio_serial_link_2[16] ;
+  assign \gpio_serial_link_2_shifted[14]  = \gpio_serial_link_2[15] ;
+  assign \gpio_serial_link_2_shifted[13]  = \gpio_serial_link_2[14] ;
+  assign \gpio_serial_link_2_shifted[12]  = \gpio_serial_link_2[13] ;
+  assign \gpio_serial_link_2_shifted[11]  = \gpio_serial_link_2[12] ;
+  assign \gpio_serial_link_2_shifted[10]  = \gpio_serial_link_2[11] ;
+  assign \gpio_serial_link_2_shifted[9]  = \gpio_serial_link_2[10] ;
+  assign \gpio_serial_link_2_shifted[8]  = \gpio_serial_link_2[9] ;
+  assign \gpio_serial_link_2_shifted[7]  = \gpio_serial_link_2[8] ;
+  assign \gpio_serial_link_2_shifted[6]  = \gpio_serial_link_2[7] ;
+  assign \gpio_serial_link_2_shifted[5]  = \gpio_serial_link_2[6] ;
+  assign \gpio_serial_link_2_shifted[4]  = \gpio_serial_link_2[5] ;
+  assign \gpio_serial_link_2_shifted[3]  = \gpio_serial_link_2[4] ;
+  assign \gpio_serial_link_2_shifted[2]  = \gpio_serial_link_2[3] ;
+  assign \gpio_serial_link_2_shifted[1]  = \gpio_serial_link_2[2] ;
+  assign \gpio_serial_link_2_shifted[0]  = \gpio_serial_link_2[1] ;
+  assign \gpio_serial_link_1_shifted[18]  = \gpio_serial_link_1[17] ;
+  assign \gpio_serial_link_1_shifted[17]  = \gpio_serial_link_1[16] ;
+  assign \gpio_serial_link_1_shifted[16]  = \gpio_serial_link_1[15] ;
+  assign \gpio_serial_link_1_shifted[15]  = \gpio_serial_link_1[14] ;
+  assign \gpio_serial_link_1_shifted[14]  = \gpio_serial_link_1[13] ;
+  assign \gpio_serial_link_1_shifted[13]  = \gpio_serial_link_1[12] ;
+  assign \gpio_serial_link_1_shifted[12]  = \gpio_serial_link_1[11] ;
+  assign \gpio_serial_link_1_shifted[11]  = \gpio_serial_link_1[10] ;
+  assign \gpio_serial_link_1_shifted[10]  = \gpio_serial_link_1[9] ;
+  assign \gpio_serial_link_1_shifted[9]  = \gpio_serial_link_1[8] ;
+  assign \gpio_serial_link_1_shifted[8]  = \gpio_serial_link_1[7] ;
+  assign \gpio_serial_link_1_shifted[7]  = \gpio_serial_link_1[6] ;
+  assign \gpio_serial_link_1_shifted[6]  = \gpio_serial_link_1[5] ;
+  assign \gpio_serial_link_1_shifted[5]  = \gpio_serial_link_1[4] ;
+  assign \gpio_serial_link_1_shifted[4]  = \gpio_serial_link_1[3] ;
+  assign \gpio_serial_link_1_shifted[3]  = \gpio_serial_link_1[2] ;
+  assign \gpio_serial_link_1_shifted[2]  = \gpio_serial_link_1[1] ;
+  assign \gpio_serial_link_1_shifted[1]  = \gpio_serial_link_1[0] ;
+  assign \gpio_resetn_1_shifted[15]  = \gpio_resetn_1[14] ;
+  assign \gpio_clock_2_shifted[14]  = \gpio_clock_2[15] ;
+  assign \gpio_clock_1_shifted[5]  = \gpio_clock_1[4] ;
+  assign \gpio_clock_1_shifted[2]  = \gpio_clock_1[1] ;
+  assign \gpio_clock_1_shifted[3]  = \gpio_clock_1[2] ;
+  assign \gpio_clock_2_shifted[2]  = \gpio_clock_2[3] ;
+  assign \gpio_clock_1_shifted[12]  = \gpio_clock_1[11] ;
+  assign \gpio_clock_1_shifted[4]  = \gpio_clock_1[3] ;
+  assign \gpio_clock_2_shifted[7]  = \gpio_clock_2[8] ;
+  assign \gpio_clock_2_shifted[12]  = \gpio_clock_2[13] ;
+  assign \gpio_clock_2_shifted[11]  = \gpio_clock_2[12] ;
+  assign \gpio_clock_1_shifted[16]  = \gpio_clock_1[15] ;
+  assign \gpio_clock_1_shifted[14]  = \gpio_clock_1[13] ;
+  assign \gpio_clock_1_shifted[7]  = \gpio_clock_1[6] ;
+  assign \gpio_clock_2_shifted[5]  = \gpio_clock_2[6] ;
+  assign \gpio_clock_1_shifted[6]  = \gpio_clock_1[5] ;
+  assign \gpio_clock_2_shifted[4]  = \gpio_clock_2[5] ;
+  assign \gpio_clock_2_shifted[13]  = \gpio_clock_2[14] ;
+  assign \gpio_clock_2_shifted[0]  = \gpio_clock_2[1] ;
+  assign \gpio_clock_1_shifted[17]  = \gpio_clock_1[16] ;
+  assign \gpio_resetn_1_shifted[17]  = \gpio_resetn_1[16] ;
+  assign \gpio_clock_2_shifted[3]  = \gpio_clock_2[4] ;
+  assign \gpio_resetn_1_shifted[18]  = \gpio_resetn_1[17] ;
+  assign \gpio_clock_2_shifted[1]  = \gpio_clock_2[2] ;
+  assign \gpio_clock_2_shifted[15]  = \gpio_clock_2[16] ;
+  assign \gpio_clock_1_shifted[13]  = \gpio_clock_1[12] ;
+  assign \gpio_clock_1_shifted[11]  = \gpio_clock_1[10] ;
+  assign mprj_io_loader_data_2 = \gpio_serial_link_2_shifted[18] ;
+  assign mprj_io_loader_data_1 = \gpio_serial_link_1_shifted[0] ;
+  assign mprj_io_loader_strobe = \gpio_load_1_shifted[0] ;
+  assign mprj_io_loader_clock = \gpio_clock_1_shifted[0] ;
+  assign mprj_io_loader_resetn = \gpio_resetn_1_shifted[0] ;
+  assign \gpio_clock_1_shifted[1]  = \gpio_clock_1[0] ;
+  assign \gpio_clock_1_shifted[9]  = \gpio_clock_1[8] ;
+  assign \gpio_resetn_1_shifted[16]  = \gpio_resetn_1[15] ;
+  assign \gpio_clock_1_shifted[15]  = \gpio_clock_1[14] ;
+  assign \gpio_clock_1_shifted[8]  = \gpio_clock_1[7] ;
+  assign \gpio_clock_1_shifted[10]  = \gpio_clock_1[9] ;
+  assign \gpio_clock_2_shifted[8]  = \gpio_clock_2[9] ;
+  assign \gpio_clock_2_shifted[9]  = \gpio_clock_2[10] ;
+  assign \gpio_clock_1_shifted[18]  = \gpio_clock_1[17] ;
+  assign \gpio_clock_2_shifted[16]  = \gpio_clock_2[17] ;
+  assign \gpio_clock_2_shifted[6]  = \gpio_clock_2[7] ;
+  assign \gpio_clock_2_shifted[17]  = \gpio_clock_2[18] ;
+  assign \gpio_clock_2_shifted[10]  = \gpio_clock_2[11] ;
+  assign \gpio_clock_2_shifted[18]  = \gpio_clock_1_shifted[0] ;
+endmodule
diff --git a/verilog/gl/gpio_defaults_block_1800.v b/verilog/gl/gpio_defaults_block_1800.v
new file mode 100644
index 0000000..bdb0ae2
--- /dev/null
+++ b/verilog/gl/gpio_defaults_block_1800.v
@@ -0,0 +1,260 @@
+module gpio_defaults_block_1800 (VGND,
+    VPWR,
+    gpio_defaults);
+ input VGND;
+ input VPWR;
+ output [12:0] gpio_defaults;
+
+ wire \gpio_defaults_low[0] ;
+ wire \gpio_defaults_high[10] ;
+ wire \gpio_defaults_low[11] ;
+ wire \gpio_defaults_low[12] ;
+ wire \gpio_defaults_high[1] ;
+ wire \gpio_defaults_low[2] ;
+ wire \gpio_defaults_low[3] ;
+ wire \gpio_defaults_low[4] ;
+ wire \gpio_defaults_low[5] ;
+ wire \gpio_defaults_low[6] ;
+ wire \gpio_defaults_low[7] ;
+ wire \gpio_defaults_low[8] ;
+ wire \gpio_defaults_low[9] ;
+ wire \gpio_defaults_high[0] ;
+ wire \gpio_defaults_high[11] ;
+ wire \gpio_defaults_high[12] ;
+ wire \gpio_defaults_high[2] ;
+ wire \gpio_defaults_high[3] ;
+ wire \gpio_defaults_high[4] ;
+ wire \gpio_defaults_high[5] ;
+ wire \gpio_defaults_high[6] ;
+ wire \gpio_defaults_high[7] ;
+ wire \gpio_defaults_high[8] ;
+ wire \gpio_defaults_high[9] ;
+ wire \gpio_defaults_low[10] ;
+ wire \gpio_defaults_low[1] ;
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[0]  (.HI(\gpio_defaults_high[0] ),
+    .LO(\gpio_defaults_low[0] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[10]  (.HI(\gpio_defaults_high[10] ),
+    .LO(\gpio_defaults_low[10] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[11]  (.HI(\gpio_defaults_high[11] ),
+    .LO(\gpio_defaults_low[11] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[12]  (.HI(\gpio_defaults_high[12] ),
+    .LO(\gpio_defaults_low[12] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[1]  (.HI(\gpio_defaults_high[1] ),
+    .LO(\gpio_defaults_low[1] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[2]  (.HI(\gpio_defaults_high[2] ),
+    .LO(\gpio_defaults_low[2] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[3]  (.HI(\gpio_defaults_high[3] ),
+    .LO(\gpio_defaults_low[3] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[4]  (.HI(\gpio_defaults_high[4] ),
+    .LO(\gpio_defaults_low[4] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[5]  (.HI(\gpio_defaults_high[5] ),
+    .LO(\gpio_defaults_low[5] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[6]  (.HI(\gpio_defaults_high[6] ),
+    .LO(\gpio_defaults_low[6] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[7]  (.HI(\gpio_defaults_high[7] ),
+    .LO(\gpio_defaults_low[7] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[8]  (.HI(\gpio_defaults_high[8] ),
+    .LO(\gpio_defaults_low[8] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[9]  (.HI(\gpio_defaults_high[9] ),
+    .LO(\gpio_defaults_low[9] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ assign gpio_defaults[0] = \gpio_defaults_low[0] ;
+ assign gpio_defaults[1] = \gpio_defaults_low[1] ;
+ assign gpio_defaults[2] = \gpio_defaults_low[2] ;
+ assign gpio_defaults[3] = \gpio_defaults_low[3] ;
+ assign gpio_defaults[4] = \gpio_defaults_low[4] ;
+ assign gpio_defaults[5] = \gpio_defaults_low[5] ;
+ assign gpio_defaults[6] = \gpio_defaults_low[6] ;
+ assign gpio_defaults[7] = \gpio_defaults_low[7] ;
+ assign gpio_defaults[8] = \gpio_defaults_low[8] ;
+ assign gpio_defaults[9] = \gpio_defaults_low[9] ;
+ assign gpio_defaults[10] = \gpio_defaults_low[10] ;
+ assign gpio_defaults[11] = \gpio_defaults_high[11] ;
+ assign gpio_defaults[12] = \gpio_defaults_high[12] ;
+endmodule
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
new file mode 100644
index 0000000..ddc717b
--- /dev/null
+++ b/verilog/rtl/caravel.v
@@ -0,0 +1,1459 @@
+ `ifdef SIM
+ `default_nettype wire
+ `endif
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130	*/
+/* fabrication process and open source PDK			*/
+/*                                                          	*/
+/* Copyright 2020 efabless, Inc.                            	*/
+/* Written by Tim Edwards, December 2019                    	*/
+/* and Mohamed Shalan, August 2020			    	*/
+/* This file is open source hardware released under the     	*/
+/* Apache 2.0 license.  See file LICENSE.                   	*/
+/*								*/
+/* Updated 10/15/2021:  Revised using the housekeeping module	*/
+/* from housekeeping.v (refactoring a number of functions from	*/
+/* the management SoC).						*/
+/*                                                          	*/
+/*--------------------------------------------------------------*/
+
+module caravel (
+
+    // All top-level I/O are package-facing pins
+
+    inout vddio,	// Common 3.3V padframe/ESD power
+    inout vddio_2,	// Common 3.3V padframe/ESD power
+    inout vssio,	// Common padframe/ESD ground
+    inout vssio_2,	// Common padframe/ESD ground
+    inout vdda,		// Management 3.3V power
+    inout vssa,		// Common analog ground
+    inout vccd,		// Management/Common 1.8V power
+    inout vssd,		// Common digital ground
+    inout vdda1,	// User area 1 3.3V power
+    inout vdda1_2,	// User area 1 3.3V power
+    inout vdda2,	// User area 2 3.3V power
+    inout vssa1,	// User area 1 analog ground
+    inout vssa1_2,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V power
+    inout vccd2,	// User area 2 1.8V power
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+
+    inout gpio,		// Used for external LDO control
+    inout [`MPRJ_IO_PADS-1:0] mprj_io,
+    input clock,    	// CMOS core clock input, not a crystal
+    input resetb,	// Reset input (sense inverted)
+
+    // Note that only two flash data pins are dedicated to the
+    // management SoC wrapper.  The management SoC exports the
+    // quad SPI mode status to make use of the top two mprj_io
+    // pins for io2 and io3.
+
+    output flash_csb,
+    output flash_clk,
+    output flash_io0,
+    output flash_io1
+);
+
+    //------------------------------------------------------------
+    // This value is uniquely defined for each user project.
+    //------------------------------------------------------------
+    parameter USER_PROJECT_ID = 32'h00020005;
+
+    /*
+     *--------------------------------------------------------------------
+     *
+     * These pins are overlaid on mprj_io space.  They have the function
+     * below when the management processor is in reset, or in the default
+     * configuration.  They are assigned to uses in the user space by the
+     * configuration program running off of the SPI flash.  Note that even
+     * when the user has taken control of these pins, they can be restored
+     * to the original use by setting the resetb pin low.  The SPI pins and
+     * UART pins can be connected directly to an FTDI chip as long as the
+     * FTDI chip sets these lines to high impedence (input function) at
+     * all times except when holding the chip in reset.
+     *
+     * JTAG       = mprj_io[0]		(inout)
+     * SDO 	  = mprj_io[1]		(output)
+     * SDI 	  = mprj_io[2]		(input)
+     * CSB 	  = mprj_io[3]		(input)
+     * SCK	  = mprj_io[4]		(input)
+     * ser_rx     = mprj_io[5]		(input)
+     * ser_tx     = mprj_io[6]		(output)
+     * irq 	  = mprj_io[7]		(input)
+     *
+     * spi_sck    = mprj_io[32]		(output)
+     * spi_csb    = mprj_io[33]		(output)
+     * spi_sdi    = mprj_io[34]		(input)
+     * spi_sdo    = mprj_io[35]		(output)
+     * flash_io2  = mprj_io[36]		(inout) 
+     * flash_io3  = mprj_io[37]		(inout) 
+     *
+     * These pins are reserved for any project that wants to incorporate
+     * its own processor and flash controller.  While a user project can
+     * technically use any available I/O pins for the purpose, these
+     * four pins connect to a pass-through mode from the SPI slave (pins
+     * 1-4 above) so that any SPI flash connected to these specific pins
+     * can be accessed through the SPI slave even when the processor is in
+     * reset.
+     *
+     * user_flash_csb = mprj_io[8]
+     * user_flash_sck = mprj_io[9]
+     * user_flash_io0 = mprj_io[10]
+     * user_flash_io1 = mprj_io[11]
+     *
+     *--------------------------------------------------------------------
+     */
+
+    // One-bit GPIO dedicated to management SoC (outside of user control)
+    wire gpio_out_core;
+    wire gpio_in_core;
+    wire gpio_mode0_core;
+    wire gpio_mode1_core;
+    wire gpio_outenb_core;
+    wire gpio_inenb_core;
+
+    // User Project Control (pad-facing)
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
+    wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
+
+    // User Project Control (user-facing)
+    wire [`MPRJ_IO_PADS-1:0] user_io_oeb;
+    wire [`MPRJ_IO_PADS-1:0] user_io_in;
+    wire [`MPRJ_IO_PADS-1:0] user_io_out;
+    wire [`MPRJ_IO_PADS-10:0] user_analog_io;
+
+    /* Padframe control signals */
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2;
+    wire mprj_io_loader_resetn;
+    wire mprj_io_loader_clock;
+    wire mprj_io_loader_strobe;
+    wire mprj_io_loader_data_1;		/* user1 side serial loader */
+    wire mprj_io_loader_data_2;		/* user2 side serial loader */
+
+    // User Project Control management I/O
+    // There are two types of GPIO connections:
+    // (1) Full Bidirectional: Management connects to in, out, and oeb
+    //     Uses:  JTAG and SDO
+    // (2) Selectable bidirectional:  Management connects to in and out,
+    //	   which are tied together.  oeb is grounded (oeb from the
+    //	   configuration is used)
+
+    // SDI 	 = mprj_io[2]		(input)
+    // CSB 	 = mprj_io[3]		(input)
+    // SCK	 = mprj_io[4]		(input)
+    // ser_rx    = mprj_io[5]		(input)
+    // ser_tx    = mprj_io[6]		(output)
+    // irq 	 = mprj_io[7]		(input)
+
+    wire [`MPRJ_IO_PADS-1:0] mgmt_io_in;	/* one- and three-pin data */
+    wire [`MPRJ_IO_PADS-5:0] mgmt_io_nc;	/* no-connects */
+    wire [4:0] mgmt_io_out;			/* three-pin interface out */
+    wire [4:0] mgmt_io_oeb;			/* three-pin output enable */
+    wire [`MPRJ_PWR_PADS-1:0] pwr_ctrl_nc;	/* no-connects */
+
+    wire clock_core;
+
+    // Power-on-reset signal.  The reset pad generates the sense-inverted
+    // reset at 3.3V.  The 1.8V signal and the inverted 1.8V signal are
+    // derived.
+
+    wire porb_h;
+    wire porb_l;
+    wire por_l;
+
+    wire rstb_h;
+    wire rstb_l;
+
+    // Flash SPI communication (management SoC to housekeeping)
+    wire flash_clk_core,     flash_csb_core;
+    wire flash_clk_oeb_core, flash_csb_oeb_core;
+    wire flash_clk_ieb_core, flash_csb_ieb_core;
+    wire flash_io0_oeb_core, flash_io1_oeb_core;
+    wire flash_io2_oeb_core, flash_io3_oeb_core;
+    wire flash_io0_ieb_core, flash_io1_ieb_core;
+    wire flash_io2_ieb_core, flash_io3_ieb_core;
+    wire flash_io0_do_core,  flash_io1_do_core;
+    wire flash_io2_do_core,  flash_io3_do_core;
+    wire flash_io0_di_core,  flash_io1_di_core;
+    wire flash_io2_di_core,  flash_io3_di_core;
+
+    // Flash SPI communication (
+    wire flash_clk_frame;
+    wire flash_csb_frame;
+    wire flash_clk_oeb, flash_csb_oeb;
+    wire flash_clk_ieb, flash_csb_ieb;
+    wire flash_io0_oeb, flash_io1_oeb;
+    wire flash_io0_ieb, flash_io1_ieb;
+    wire flash_io0_do,  flash_io1_do;
+    wire flash_io0_di,  flash_io1_di;
+
+    chip_io padframe(
+	`ifndef TOP_ROUTING
+		// Package Pins
+		.vddio_pad	(vddio),		// Common padframe/ESD supply
+		.vddio_pad2	(vddio_2),
+		.vssio_pad	(vssio),		// Common padframe/ESD ground
+		.vssio_pad2	(vssio_2),
+		.vccd_pad	(vccd),			// Common 1.8V supply
+		.vssd_pad	(vssd),			// Common digital ground
+		.vdda_pad	(vdda),			// Management analog 3.3V supply
+		.vssa_pad	(vssa),			// Management analog ground
+		.vdda1_pad	(vdda1),		// User area 1 3.3V supply
+		.vdda1_pad2	(vdda1_2),		
+		.vdda2_pad	(vdda2),		// User area 2 3.3V supply
+		.vssa1_pad	(vssa1),		// User area 1 analog ground
+		.vssa1_pad2	(vssa1_2),
+		.vssa2_pad	(vssa2),		// User area 2 analog ground
+		.vccd1_pad	(vccd1),		// User area 1 1.8V supply
+		.vccd2_pad	(vccd2),		// User area 2 1.8V supply
+		.vssd1_pad	(vssd1),		// User area 1 digital ground
+		.vssd2_pad	(vssd2),		// User area 2 digital ground
+	`endif
+	// Core Side Pins
+	.vddio	(vddio_core),
+	.vssio	(vssio_core),
+	.vdda	(vdda_core),
+	.vssa	(vssa_core),
+	.vccd	(vccd_core),
+	.vssd	(vssd_core),
+	.vdda1	(vdda1_core),
+	.vdda2	(vdda2_core),
+	.vssa1	(vssa1_core),
+	.vssa2	(vssa2_core),
+	.vccd1	(vccd1_core),
+	.vccd2	(vccd2_core),
+	.vssd1	(vssd1_core),
+	.vssd2	(vssd2_core),
+
+	.gpio(gpio),
+	.mprj_io(mprj_io),
+	.clock(clock),
+	.resetb(resetb),
+	.flash_csb(flash_csb),
+	.flash_clk(flash_clk),
+	.flash_io0(flash_io0),
+	.flash_io1(flash_io1),
+	// SoC Core Interface
+	.porb_h(porb_h),
+	.por(por_l),
+	.resetb_core_h(rstb_h),
+	.clock_core(clock_core),
+	.gpio_out_core(gpio_out_core),
+	.gpio_in_core(gpio_in_core),
+	.gpio_mode0_core(gpio_mode0_core),
+	.gpio_mode1_core(gpio_mode1_core),
+	.gpio_outenb_core(gpio_outenb_core),
+	.gpio_inenb_core(gpio_inenb_core),
+	.flash_csb_core(flash_csb_frame),
+	.flash_clk_core(flash_clk_frame),
+	.flash_csb_oeb_core(flash_csb_oeb),
+	.flash_clk_oeb_core(flash_clk_oeb),
+	.flash_io0_oeb_core(flash_io0_oeb),
+	.flash_io1_oeb_core(flash_io1_oeb),
+	.flash_csb_ieb_core(flash_csb_ieb),
+	.flash_clk_ieb_core(flash_clk_ieb),
+	.flash_io0_ieb_core(flash_io0_ieb),
+	.flash_io1_ieb_core(flash_io1_ieb),
+	.flash_io0_do_core(flash_io0_do),
+	.flash_io1_do_core(flash_io1_do),
+	.flash_io0_di_core(flash_io0_di),
+	.flash_io1_di_core(flash_io1_di),
+	.mprj_io_in(mprj_io_in),
+	.mprj_io_out(mprj_io_out),
+	.mprj_io_oeb(mprj_io_oeb),
+	.mprj_io_inp_dis(mprj_io_inp_dis),
+	.mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+	.mprj_io_vtrip_sel(mprj_io_vtrip_sel),
+	.mprj_io_slow_sel(mprj_io_slow_sel),
+	.mprj_io_holdover(mprj_io_holdover),
+	.mprj_io_analog_en(mprj_io_analog_en),
+	.mprj_io_analog_sel(mprj_io_analog_sel),
+	.mprj_io_analog_pol(mprj_io_analog_pol),
+	.mprj_io_dm(mprj_io_dm),
+	.mprj_analog_io(user_analog_io)
+    );
+
+    // SoC core
+    wire caravel_clk;
+    wire caravel_clk2;
+    wire caravel_rstn;
+
+    // Logic analyzer signals
+    wire [127:0] la_data_in_user;  // From CPU to MPRJ
+    wire [127:0] la_data_in_mprj;  // From MPRJ to CPU
+    wire [127:0] la_data_out_mprj; // From CPU to MPRJ
+    wire [127:0] la_data_out_user; // From MPRJ to CPU
+    wire [127:0] la_oenb_user;     // From CPU to MPRJ
+    wire [127:0] la_oenb_mprj;     // From CPU to MPRJ
+    wire [127:0] la_iena_mprj;     // From CPU only
+
+    wire [2:0]   user_irq;	  // From MRPJ to CPU
+    wire [2:0]   user_irq_core;
+    wire [2:0]   user_irq_ena;
+    wire [2:0]	 irq_spi;	  // From SPI and external pins
+
+    // Exported Wishbone Bus (processor facing)
+    wire mprj_iena_wb;
+    wire mprj_cyc_o_core;
+    wire mprj_stb_o_core;
+    wire mprj_we_o_core;
+    wire [3:0] mprj_sel_o_core;
+    wire [31:0] mprj_adr_o_core;
+    wire [31:0] mprj_dat_o_core;
+    wire mprj_ack_i_core;
+    wire [31:0] mprj_dat_i_core;
+
+    wire [31:0] hk_dat_i;
+    wire hk_ack_i;
+    wire hk_stb_o;
+    wire hk_cyc_o;
+
+    // Exported Wishbone Bus (user area facing)
+    wire 	mprj_cyc_o_user;
+    wire 	mprj_stb_o_user;
+    wire 	mprj_we_o_user;
+    wire [3:0]  mprj_sel_o_user;
+    wire [31:0] mprj_adr_o_user;
+    wire [31:0] mprj_dat_o_user;
+    wire [31:0] mprj_dat_i_user;
+    wire	mprj_ack_i_user;
+
+    // Mask revision
+    wire [31:0] mask_rev;
+
+    wire 	mprj_clock;
+    wire 	mprj_clock2;
+    wire 	mprj_reset;
+
+    // Power monitoring 
+    wire	mprj_vcc_pwrgood;
+    wire	mprj2_vcc_pwrgood;
+    wire	mprj_vdd_pwrgood;
+    wire	mprj2_vdd_pwrgood;
+
+    // SRAM read-only access from houskeeping
+    wire 	hkspi_sram_clk;
+    wire 	hkspi_sram_csb;
+    wire [7:0]	hkspi_sram_addr;
+    wire [31:0]	hkspi_sram_data;
+
+    // Management processor (wrapper).  Any management core
+    // implementation must match this pinout.
+
+    mgmt_core_wrapper soc (
+	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+	`endif
+
+	// Clock and reset
+	.core_clk(caravel_clk),
+	.core_rstn(caravel_rstn),
+
+	// GPIO (1 pin)
+	.gpio_out_pad(gpio_out_core),
+	.gpio_in_pad(gpio_in_core),
+	.gpio_mode0_pad(gpio_mode0_core),
+	.gpio_mode1_pad(gpio_mode1_core),
+	.gpio_outenb_pad(gpio_outenb_core),
+	.gpio_inenb_pad(gpio_inenb_core),
+
+	// Primary SPI flash controller
+	.flash_csb(flash_csb_core),
+	.flash_clk(flash_clk_core),
+	.flash_io0_oeb(flash_io0_oeb_core),
+	.flash_io0_di(flash_io0_di_core),
+	.flash_io0_do(flash_io0_do_core),
+	.flash_io1_oeb(flash_io1_oeb_core),
+	.flash_io1_di(flash_io1_di_core),
+	.flash_io1_do(flash_io1_do_core),
+	.flash_io2_oeb(flash_io2_oeb_core),
+	.flash_io2_di(flash_io2_di_core),
+	.flash_io2_do(flash_io2_do_core),
+	.flash_io3_oeb(flash_io3_oeb_core),
+	.flash_io3_di(flash_io3_di_core),
+	.flash_io3_do(flash_io3_do_core),
+
+	// Exported Wishbone Bus
+	.mprj_wb_iena(mprj_iena_wb),
+	.mprj_cyc_o(mprj_cyc_o_core),
+	.mprj_stb_o(mprj_stb_o_core),
+	.mprj_we_o(mprj_we_o_core),
+	.mprj_sel_o(mprj_sel_o_core),
+	.mprj_adr_o(mprj_adr_o_core),
+	.mprj_dat_o(mprj_dat_o_core),
+	.mprj_ack_i(mprj_ack_i_core),
+	.mprj_dat_i(mprj_dat_i_core),
+
+	.hk_stb_o(hk_stb_o),
+	.hk_cyc_o(hk_cyc_o),
+	.hk_dat_i(hk_dat_i),
+	.hk_ack_i(hk_ack_i),
+
+	// IRQ
+	.irq({irq_spi, user_irq}),
+	.user_irq_ena(user_irq_ena),
+
+	// Module status (these may or may not be implemented)
+	.qspi_enabled(qspi_enabled),
+	.uart_enabled(uart_enabled),
+	.spi_enabled(spi_enabled),
+	.debug_mode(debug_mode),
+
+	// Module I/O (these may or may not be implemented)
+	// UART
+	.ser_tx(ser_tx),
+	.ser_rx(ser_rx),
+	// SPI master
+	.spi_sdi(spi_sdi),
+	.spi_csb(spi_csb),
+	.spi_sck(spi_sck),
+	.spi_sdo(spi_sdo),
+	.spi_sdoenb(spi_sdoenb),
+	// Debug
+	.debug_in(debug_in),
+	.debug_out(debug_out),
+	.debug_oeb(debug_oeb),
+	// Logic analyzer
+	.la_input(la_data_in_mprj),
+	.la_output(la_data_out_mprj),
+	.la_oenb(la_oenb_mprj),
+	.la_iena(la_iena_mprj),
+
+	// SRAM Read-only access from housekeeping
+	.sram_ro_clk(hkspi_sram_clk),
+	.sram_ro_csb(hkspi_sram_csb),
+	.sram_ro_addr(hkspi_sram_addr),
+	.sram_ro_data(hkspi_sram_data),
+
+	// Trap status
+	.trap(trap)
+    );
+
+    /* Clock and reset to user space are passed through a tristate	*/
+    /* buffer like the above, but since they are intended to be		*/
+    /* always active, connect the enable to the logic-1 output from	*/
+    /* the vccd1 domain.						*/
+
+    mgmt_protect mgmt_buffers (
+	`ifdef USE_POWER_PINS
+ 	    .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+	    .vccd2(vccd2_core),
+	    .vssd2(vssd2_core),
+	    .vdda1(vdda1_core),
+	    .vssa1(vssa1_core),
+	    .vdda2(vdda2_core),
+	    .vssa2(vssa2_core),
+	`endif
+	.caravel_clk(caravel_clk),
+	.caravel_clk2(caravel_clk2),
+	.caravel_rstn(caravel_rstn),
+	.mprj_iena_wb(mprj_iena_wb),
+	.mprj_cyc_o_core(mprj_cyc_o_core),
+	.mprj_stb_o_core(mprj_stb_o_core),
+	.mprj_we_o_core(mprj_we_o_core),
+	.mprj_sel_o_core(mprj_sel_o_core),
+	.mprj_adr_o_core(mprj_adr_o_core),
+	.mprj_dat_o_core(mprj_dat_o_core),
+	.mprj_ack_i_core(mprj_ack_i_core),
+	.mprj_dat_i_core(mprj_dat_i_core),
+	.user_irq_core(user_irq_core),
+	.user_irq_ena(user_irq_ena),
+	.la_data_out_core(la_data_out_user),
+	.la_data_out_mprj(la_data_out_mprj),
+	.la_data_in_core(la_data_in_user),
+	.la_data_in_mprj(la_data_in_mprj),
+	.la_oenb_mprj(la_oenb_mprj),
+	.la_oenb_core(la_oenb_user),
+	.la_iena_mprj(la_iena_mprj),
+
+	.user_clock(mprj_clock),
+	.user_clock2(mprj_clock2),
+	.user_reset(mprj_reset),
+	.mprj_cyc_o_user(mprj_cyc_o_user),
+	.mprj_stb_o_user(mprj_stb_o_user),
+	.mprj_we_o_user(mprj_we_o_user),
+	.mprj_sel_o_user(mprj_sel_o_user),
+	.mprj_adr_o_user(mprj_adr_o_user),
+	.mprj_dat_o_user(mprj_dat_o_user),
+	.mprj_dat_i_user(mprj_dat_i_user),
+	.mprj_ack_i_user(mprj_ack_i_user),
+	.user_irq(user_irq),
+	.user1_vcc_powergood(mprj_vcc_pwrgood),
+	.user2_vcc_powergood(mprj2_vcc_pwrgood),
+	.user1_vdd_powergood(mprj_vdd_pwrgood),
+	.user2_vdd_powergood(mprj2_vdd_pwrgood)
+    );
+
+    /*--------------------------------------------------*/
+    /* Wrapper module around the user project 		*/
+    /*--------------------------------------------------*/
+
+    user_project_wrapper mprj ( 
+        `ifdef USE_POWER_PINS
+	    .vdda1(vdda1_core),		// User area 1 3.3V power
+	    .vdda2(vdda2_core),		// User area 2 3.3V power
+	    .vssa1(vssa1_core),		// User area 1 analog ground
+	    .vssa2(vssa2_core),		// User area 2 analog ground
+	    .vccd1(vccd1_core),		// User area 1 1.8V power
+	    .vccd2(vccd2_core),		// User area 2 1.8V power
+	    .vssd1(vssd1_core),		// User area 1 digital ground
+	    .vssd2(vssd2_core),		// User area 2 digital ground
+    	`endif
+
+    	.wb_clk_i(mprj_clock),
+    	.wb_rst_i(mprj_reset),
+
+	// Management SoC Wishbone bus (exported)
+	.wbs_cyc_i(mprj_cyc_o_user),
+	.wbs_stb_i(mprj_stb_o_user),
+	.wbs_we_i(mprj_we_o_user),
+	.wbs_sel_i(mprj_sel_o_user),
+	.wbs_adr_i(mprj_adr_o_user),
+	.wbs_dat_i(mprj_dat_o_user),
+	.wbs_ack_o(mprj_ack_i_user),
+	.wbs_dat_o(mprj_dat_i_user),
+
+	// GPIO pad 3-pin interface (plus analog)
+	.io_in (user_io_in),
+    	.io_out(user_io_out),
+    	.io_oeb(user_io_oeb),
+	.analog_io(user_analog_io),
+
+	// Logic analyzer
+	.la_data_in(la_data_in_user),
+	.la_data_out(la_data_out_user),
+	.la_oenb(la_oenb_user),
+
+	// Independent clock
+	.user_clock2(mprj_clock2),
+
+	// IRQ
+	.user_irq(user_irq_core)
+    );
+
+    /*------------------------------------------*/
+    /* End user project instantiation		*/
+    /*------------------------------------------*/
+
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1_shifted;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2_shifted;
+
+    assign gpio_serial_link_1_shifted = {gpio_serial_link_1[`MPRJ_IO_PADS_1-2:0],
+					 mprj_io_loader_data_1};
+    // Note that serial_link_2 is backwards compared to serial_link_1, so it
+    // shifts in the other direction.
+    assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2,
+					 gpio_serial_link_2[`MPRJ_IO_PADS_2-1:1]};
+
+    // Propagating clock and reset to mitigate timing and fanout issues
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2;
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2;
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_load_1;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_load_2;
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1_shifted;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2_shifted;
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1_shifted;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2_shifted;
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_load_1_shifted;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_load_2_shifted;
+
+    assign gpio_clock_1_shifted = {gpio_clock_1[`MPRJ_IO_PADS_1-2:0],
+					 mprj_io_loader_clock};
+    assign gpio_clock_2_shifted = {mprj_io_loader_clock,
+					gpio_clock_2[`MPRJ_IO_PADS_2-1:1]};
+    assign gpio_resetn_1_shifted = {gpio_resetn_1[`MPRJ_IO_PADS_1-2:0],
+					 mprj_io_loader_resetn};
+    assign gpio_resetn_2_shifted = {mprj_io_loader_resetn,
+					gpio_resetn_2[`MPRJ_IO_PADS_2-1:1]};
+    assign gpio_load_1_shifted = {gpio_load_1[`MPRJ_IO_PADS_1-2:0],
+					 mprj_io_loader_strobe};
+    assign gpio_load_2_shifted = {mprj_io_loader_strobe,
+					gpio_load_2[`MPRJ_IO_PADS_2-1:1]};
+
+    wire [2:0] spi_pll_sel;
+    wire [2:0] spi_pll90_sel;
+    wire [4:0] spi_pll_div;
+    wire [25:0] spi_pll_trim;
+
+    // Clocking control
+
+    caravel_clocking clocking(
+    `ifdef USE_POWER_PINS
+		.VPWR(vccd_core),
+		.VGND(vssd_core),
+    `endif
+        .ext_clk_sel(ext_clk_sel),
+        .ext_clk(clock_core),
+        .pll_clk(pll_clk),
+        .pll_clk90(pll_clk90),
+        .resetb(rstb_l),
+        .sel(spi_pll_sel),
+        .sel2(spi_pll90_sel),
+        .ext_reset(ext_reset),  // From housekeeping SPI
+        .core_clk(caravel_clk),
+        .user_clk(caravel_clk2),
+        .resetb_sync(caravel_rstn)
+    );
+
+    // DCO/Digital Locked Loop
+
+    digital_pll pll (
+    `ifdef USE_POWER_PINS
+		.VPWR(vccd_core),
+		.VGND(vssd_core),
+    `endif
+        .resetb(rstb_l),
+        .enable(spi_pll_ena),
+        .osc(clock_core),
+        .clockp({pll_clk, pll_clk90}),
+        .div(spi_pll_div),
+        .dco(spi_pll_dco_ena),
+        .ext_trim(spi_pll_trim)
+    );
+
+    // Housekeeping interface
+
+    housekeeping housekeeping (
+    `ifdef USE_POWER_PINS
+		.VPWR(vccd_core),
+		.VGND(vssd_core),
+    `endif
+
+        .wb_clk_i(caravel_clk),
+        .wb_rstn_i(caravel_rstn),
+
+        .wb_adr_i(mprj_adr_o_core),
+        .wb_dat_i(mprj_dat_o_core),
+        .wb_sel_i(mprj_sel_o_core),
+        .wb_we_i(mprj_we_o_core),
+        .wb_cyc_i(hk_cyc_o),
+        .wb_stb_i(hk_stb_o),
+        .wb_ack_o(hk_ack_i),
+        .wb_dat_o(hk_dat_i),
+
+        .porb(porb_l),
+
+        .pll_ena(spi_pll_ena),
+        .pll_dco_ena(spi_pll_dco_ena),
+        .pll_div(spi_pll_div),
+        .pll_sel(spi_pll_sel),
+        .pll90_sel(spi_pll90_sel),
+        .pll_trim(spi_pll_trim),
+        .pll_bypass(ext_clk_sel),
+
+	.qspi_enabled(qspi_enabled),
+	.uart_enabled(uart_enabled),
+	.spi_enabled(spi_enabled),
+	.debug_mode(debug_mode),
+
+	.ser_tx(ser_tx),
+	.ser_rx(ser_rx),
+
+	.spi_sdi(spi_sdi),
+	.spi_csb(spi_csb),
+	.spi_sck(spi_sck),
+	.spi_sdo(spi_sdo),
+	.spi_sdoenb(spi_sdoenb),
+
+	.debug_in(debug_in),
+	.debug_out(debug_out),
+	.debug_oeb(debug_oeb),
+
+        .irq(irq_spi),
+        .reset(ext_reset),
+
+        .serial_clock(mprj_io_loader_clock),
+        .serial_load(mprj_io_loader_strobe),
+        .serial_resetn(mprj_io_loader_resetn),
+        .serial_data_1(mprj_io_loader_data_1),
+        .serial_data_2(mprj_io_loader_data_2),
+
+	.mgmt_gpio_in(mgmt_io_in),
+	.mgmt_gpio_out({mgmt_io_out[4:2], mgmt_io_in[`MPRJ_IO_PADS-4:2],
+			mgmt_io_out[1:0]}),
+	.mgmt_gpio_oeb({mgmt_io_oeb[4:2], mgmt_io_nc[`MPRJ_IO_PADS-6:0],
+			mgmt_io_oeb[1:0]}),
+
+	.pwr_ctrl_out(pwr_ctrl_nc),	/* Not used in this version */
+
+        .trap(trap),
+
+	.user_clock(caravel_clk2),
+
+        .mask_rev_in(mask_rev),
+
+	.spimemio_flash_csb(flash_csb_core),
+	.spimemio_flash_clk(flash_clk_core),
+	.spimemio_flash_io0_oeb(flash_io0_oeb_core),
+	.spimemio_flash_io1_oeb(flash_io1_oeb_core),
+	.spimemio_flash_io2_oeb(flash_io2_oeb_core),
+	.spimemio_flash_io3_oeb(flash_io3_oeb_core),
+	.spimemio_flash_io0_do(flash_io0_do_core),
+	.spimemio_flash_io1_do(flash_io1_do_core),
+	.spimemio_flash_io2_do(flash_io2_do_core),
+	.spimemio_flash_io3_do(flash_io3_do_core),
+	.spimemio_flash_io0_di(flash_io0_di_core),
+	.spimemio_flash_io1_di(flash_io1_di_core),
+	.spimemio_flash_io2_di(flash_io2_di_core),
+	.spimemio_flash_io3_di(flash_io3_di_core),
+
+	.pad_flash_csb(flash_csb_frame),
+	.pad_flash_csb_oeb(flash_csb_oeb),
+	.pad_flash_clk(flash_clk_frame),
+	.pad_flash_clk_oeb(flash_clk_oeb),
+	.pad_flash_io0_oeb(flash_io0_oeb),
+	.pad_flash_io1_oeb(flash_io1_oeb),
+	.pad_flash_io0_ieb(flash_io0_ieb),
+	.pad_flash_io1_ieb(flash_io1_ieb),
+	.pad_flash_io0_do(flash_io0_do),
+	.pad_flash_io1_do(flash_io1_do),
+	.pad_flash_io0_di(flash_io0_di),
+	.pad_flash_io1_di(flash_io1_di),
+
+	.sram_ro_clk(hkspi_sram_clk),
+	.sram_ro_csb(hkspi_sram_csb),
+	.sram_ro_addr(hkspi_sram_addr),
+	.sram_ro_data(hkspi_sram_data),
+
+	.usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+	.usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+	.usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+	.usr2_vdd_pwrgood(mprj2_vdd_pwrgood)
+    );
+
+    /* GPIO defaults (via programmed) */
+    wire [`MPRJ_IO_PADS*13-1:0] gpio_defaults;
+
+    /* Fixed defaults for the first 5 GPIO pins */
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(13'h1803)
+    ) gpio_defaults_block_0 [1:0] (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[25:0])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(13'h0403)
+    ) gpio_defaults_block_2 [2:0] (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[64:26])
+    );
+
+    /* Via-programmable defaults for the rest of the GPIO pins */
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_5_INIT)
+    ) gpio_defaults_block_5 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[77:65])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_6_INIT)
+    ) gpio_defaults_block_6 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[90:78])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_7_INIT)
+    ) gpio_defaults_block_7 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[103:91])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_8_INIT)
+    ) gpio_defaults_block_8 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[116:104])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_9_INIT)
+    ) gpio_defaults_block_9 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[129:117])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_10_INIT)
+    ) gpio_defaults_block_10 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[142:130])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_11_INIT)
+    ) gpio_defaults_block_11 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[155:143])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_12_INIT)
+    ) gpio_defaults_block_12 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[168:156])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_13_INIT)
+    ) gpio_defaults_block_13 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[181:169])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_14_INIT)
+    ) gpio_defaults_block_14 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[194:182])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_15_INIT)
+    ) gpio_defaults_block_15 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[207:195])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_16_INIT)
+    ) gpio_defaults_block_16 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[220:208])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_17_INIT)
+    ) gpio_defaults_block_17 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[233:221])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_18_INIT)
+    ) gpio_defaults_block_18 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[246:234])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_19_INIT)
+    ) gpio_defaults_block_19 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[259:247])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_20_INIT)
+    ) gpio_defaults_block_20 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[272:260])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_21_INIT)
+    ) gpio_defaults_block_21 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[285:273])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_22_INIT)
+    ) gpio_defaults_block_22 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[298:286])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_23_INIT)
+    ) gpio_defaults_block_23 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[311:299])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_24_INIT)
+    ) gpio_defaults_block_24 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[324:312])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_25_INIT)
+    ) gpio_defaults_block_25 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[337:325])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_26_INIT)
+    ) gpio_defaults_block_26 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[350:338])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_27_INIT)
+    ) gpio_defaults_block_27 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[363:351])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_28_INIT)
+    ) gpio_defaults_block_28 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[376:364])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_29_INIT)
+    ) gpio_defaults_block_29 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[389:377])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_30_INIT)
+    ) gpio_defaults_block_30 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[402:390])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_31_INIT)
+    ) gpio_defaults_block_31 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[415:403])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_32_INIT)
+    ) gpio_defaults_block_32 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[428:416])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_33_INIT)
+    ) gpio_defaults_block_33 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[441:429])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_34_INIT)
+    ) gpio_defaults_block_34 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[454:442])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_35_INIT)
+    ) gpio_defaults_block_35 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[467:455])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_36_INIT)
+    ) gpio_defaults_block_36 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[480:468])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_37_INIT)
+    ) gpio_defaults_block_37 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[493:481])
+    );
+
+    // Each control block sits next to an I/O pad in the user area.
+    // It gets input through a serial chain from the previous control
+    // block and passes it to the next control block.  Due to the nature
+    // of the shift register, bits are presented in reverse, as the first
+    // bit in ends up as the last bit of the last I/O pad control block.
+
+    // There are two types of block;  the first two and the last two
+    // are configured to be full bidirectional under control of the
+    // management Soc (JTAG and SDO for the first two;  flash_io2 and
+    // flash_io3 for the last two).  The rest are configured to be default
+    // (input).  Note that the first two and last two are the ones closest
+    // to the management SoC on either side, which minimizes the wire length
+    // of the extra signals those pads need.
+
+    /* First two GPIOs (JTAG and SDO) */
+
+    gpio_control_block gpio_control_bidir_1 [1:0] (
+    	`ifdef USE_POWER_PINS
+	    .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+        `endif
+
+	.gpio_defaults(gpio_defaults[25:0]),
+
+    	// Management Soc-facing signals
+
+    	.resetn(gpio_resetn_1_shifted[1:0]),
+    	.serial_clock(gpio_clock_1_shifted[1:0]),
+    	.serial_load(gpio_load_1_shifted[1:0]),
+
+    	.resetn_out(gpio_resetn_1[1:0]),
+    	.serial_clock_out(gpio_clock_1[1:0]),
+    	.serial_load_out(gpio_load_1[1:0]),
+
+    	.mgmt_gpio_in(mgmt_io_in[1:0]),
+	.mgmt_gpio_out(mgmt_io_out[1:0]),
+	.mgmt_gpio_oeb(mgmt_io_oeb[1:0]),
+
+        .one(),
+        .zero(),
+
+    	// Serial data chain for pad configuration
+    	.serial_data_in(gpio_serial_link_1_shifted[1:0]),
+    	.serial_data_out(gpio_serial_link_1[1:0]),
+
+    	// User-facing signals
+    	.user_gpio_out(user_io_out[1:0]),
+    	.user_gpio_oeb(user_io_oeb[1:0]),
+    	.user_gpio_in(user_io_in[1:0]),
+
+    	// Pad-facing signals (Pad GPIOv2)
+    	.pad_gpio_inenb(mprj_io_inp_dis[1:0]),
+    	.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[1:0]),
+    	.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[1:0]),
+    	.pad_gpio_slow_sel(mprj_io_slow_sel[1:0]),
+    	.pad_gpio_holdover(mprj_io_holdover[1:0]),
+    	.pad_gpio_ana_en(mprj_io_analog_en[1:0]),
+    	.pad_gpio_ana_sel(mprj_io_analog_sel[1:0]),
+    	.pad_gpio_ana_pol(mprj_io_analog_pol[1:0]),
+    	.pad_gpio_dm(mprj_io_dm[5:0]),
+    	.pad_gpio_outenb(mprj_io_oeb[1:0]),
+    	.pad_gpio_out(mprj_io_out[1:0]),
+    	.pad_gpio_in(mprj_io_in[1:0])
+    );
+
+    /* Section 1 GPIOs (GPIO 0 to 18) */
+    wire [`MPRJ_IO_PADS_1-1:2] one_loop1;
+
+    /* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */
+
+    gpio_control_block gpio_control_in_1a [5:0] (
+        `ifdef USE_POWER_PINS
+            .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+        `endif
+
+	.gpio_defaults(gpio_defaults[103:26]),
+
+    	// Management Soc-facing signals
+
+    	.resetn(gpio_resetn_1_shifted[7:2]),
+    	.serial_clock(gpio_clock_1_shifted[7:2]),
+    	.serial_load(gpio_load_1_shifted[7:2]),
+
+    	.resetn_out(gpio_resetn_1[7:2]),
+    	.serial_clock_out(gpio_clock_1[7:2]),
+    	.serial_load_out(gpio_load_1[7:2]),
+
+	.mgmt_gpio_in(mgmt_io_in[7:2]),
+	.mgmt_gpio_out(mgmt_io_in[7:2]),
+	.mgmt_gpio_oeb(one_loop1[7:2]),
+
+        .one(one_loop1[7:2]),
+        .zero(),
+
+    	// Serial data chain for pad configuration
+    	.serial_data_in(gpio_serial_link_1_shifted[7:2]),
+    	.serial_data_out(gpio_serial_link_1[7:2]),
+
+    	// User-facing signals
+    	.user_gpio_out(user_io_out[7:2]),
+    	.user_gpio_oeb(user_io_oeb[7:2]),
+    	.user_gpio_in(user_io_in[7:2]),
+
+    	// Pad-facing signals (Pad GPIOv2)
+    	.pad_gpio_inenb(mprj_io_inp_dis[7:2]),
+    	.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[7:2]),
+    	.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[7:2]),
+    	.pad_gpio_slow_sel(mprj_io_slow_sel[7:2]),
+    	.pad_gpio_holdover(mprj_io_holdover[7:2]),
+    	.pad_gpio_ana_en(mprj_io_analog_en[7:2]),
+    	.pad_gpio_ana_sel(mprj_io_analog_sel[7:2]),
+    	.pad_gpio_ana_pol(mprj_io_analog_pol[7:2]),
+    	.pad_gpio_dm(mprj_io_dm[23:6]),
+    	.pad_gpio_outenb(mprj_io_oeb[7:2]),
+    	.pad_gpio_out(mprj_io_out[7:2]),
+    	.pad_gpio_in(mprj_io_in[7:2])
+    );
+
+    /* Section 1 GPIOs (GPIO 8 to 18) */
+
+    gpio_control_block gpio_control_in_1 [`MPRJ_IO_PADS_1-9:0] (
+        `ifdef USE_POWER_PINS
+            .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+        `endif
+
+	.gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS_1*13-1):104]),
+
+    	// Management Soc-facing signals
+
+    	.resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+    	.serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+    	.serial_load(gpio_load_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+
+    	.resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_1-1):8]),
+    	.serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_1-1):8]),
+    	.serial_load_out(gpio_load_1[(`MPRJ_IO_PADS_1-1):8]),
+
+	.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]),
+	.mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]),
+	.mgmt_gpio_oeb(one_loop1[(`MPRJ_IO_PADS_1-1):8]),
+
+        .one(one_loop1[(`MPRJ_IO_PADS_1-1):8]),
+        .zero(),
+
+    	// Serial data chain for pad configuration
+    	.serial_data_in(gpio_serial_link_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+    	.serial_data_out(gpio_serial_link_1[(`MPRJ_IO_PADS_1-1):8]),
+
+    	// User-facing signals
+    	.user_gpio_out(user_io_out[(`MPRJ_IO_PADS_1-1):8]),
+    	.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS_1-1):8]),
+    	.user_gpio_in(user_io_in[(`MPRJ_IO_PADS_1-1):8]),
+
+    	// Pad-facing signals (Pad GPIOv2)
+    	.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS_1*3-1):24]),
+    	.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS_1-1):8])
+    );
+
+    /* Last three GPIOs (spi_sdo, flash_io2, and flash_io3) */
+
+    gpio_control_block gpio_control_bidir_2 [2:0] (
+    	`ifdef USE_POWER_PINS
+	    .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+        `endif
+
+	.gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS*13-1):(`MPRJ_IO_PADS*13-39)]),
+
+    	// Management Soc-facing signals
+
+    	.resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+    	.serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+    	.serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+    	.resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+    	.serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+    	.serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+    	.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+	.mgmt_gpio_out(mgmt_io_out[4:2]),
+	.mgmt_gpio_oeb(mgmt_io_oeb[4:2]),
+
+        .one(),
+        .zero(),
+
+    	// Serial data chain for pad configuration
+    	.serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+    	.serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+    	// User-facing signals
+    	.user_gpio_out(user_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.user_gpio_in(user_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+
+    	// Pad-facing signals (Pad GPIOv2)
+    	.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-1):(`MPRJ_IO_PADS*3-9)]),
+    	.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)])
+    );
+
+    /* Section 2 GPIOs (GPIO 19 to 34) */
+    wire [`MPRJ_IO_PADS_2-4:0] one_loop2;
+
+    gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-4:0] (
+    	`ifdef USE_POWER_PINS
+            .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+        `endif
+
+	.gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS*13-40):(`MPRJ_IO_PADS_1*13)]),
+
+    	// Management Soc-facing signals
+
+    	.resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+    	.serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+    	.serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+
+    	.resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-4):0]),
+    	.serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-4):0]),
+    	.serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-4):0]),
+
+	.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+	.mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+	.mgmt_gpio_oeb(one_loop2),
+
+        .one(one_loop2),
+        .zero(),
+
+    	// Serial data chain for pad configuration
+    	.serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+    	.serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-4):0]),
+
+    	// User-facing signals
+    	.user_gpio_out(user_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.user_gpio_in(user_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+
+    	// Pad-facing signals (Pad GPIOv2)
+    	.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-10):(`MPRJ_IO_PADS_1*3)]),
+    	.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)])
+    );
+
+    user_id_programming #(
+	.USER_PROJECT_ID(USER_PROJECT_ID)
+    ) user_id_value (
+	`ifdef USE_POWER_PINS
+		.VPWR(vccd_core),
+		.VGND(vssd_core),
+	`endif
+	.mask_rev(mask_rev)
+    );
+
+    // Power-on-reset circuit
+    simple_por por (
+	`ifdef USE_POWER_PINS
+		.vdd3v3(vddio_core),
+		.vdd1v8(vccd_core),
+		.vss3v3(vssio_core),
+		.vss1v8(vssd_core),
+	`endif
+		.porb_h(porb_h),
+		.porb_l(porb_l),
+		.por_l(por_l)
+    );
+
+    // XRES (chip input pin reset) reset level converter
+    xres_buf rstb_level (
+	`ifdef USE_POWER_PINS
+		.VPWR(vddio_core),
+		.LVPWR(vccd_core),
+		.LVGND(vssd_core),
+		.VGND(vssio_core),
+	`endif
+		.A(rstb_h),
+		.X(rstb_l)
+    );
+
+    // Spare logic for metal mask fixes
+    wire [107:0] spare_xz_nc;
+    wire [15:0] spare_xi_nc;
+    wire [3:0] spare_xib_nc;
+    wire [7:0] spare_xna_nc;
+    wire [7:0] spare_xno_nc;
+    wire [7:0] spare_xmx_nc;
+    wire [7:0] spare_xfq_nc;
+    wire [7:0] spare_xfqn_nc;
+
+    spare_logic_block spare_logic [3:0] (
+	`ifdef USE_POWER_PINS
+		.vccd(vccd_core),
+		.vssd(vssd_core),
+	`endif
+		.spare_xz(spare_xz_nc),
+		.spare_xi(spare_xi_nc),
+		.spare_xib(spare_xib_nc),
+		.spare_xna(spare_xna_nc),
+		.spare_xno(spare_xno_nc),
+		.spare_xmx(spare_xmx_nc),
+		.spare_xfq(spare_xfq_nc),
+		.spare_xfqn(spare_xfqn_nc)
+    );
+
+endmodule
+// `default_nettype wire