diff --git a/README.md b/README.md
index 53d1508..7bae8bb 100644
--- a/README.md
+++ b/README.md
@@ -31,7 +31,8 @@
 - Caravel User Project Features -- https://youtu.be/zJhnmilXGPo
 - Aboard Caravel -- How to put your design on Caravel? -- https://youtu.be/9QV8SDelURk
 - Things to Clarify About Caravel -- What versions to use with Caravel? -- https://youtu.be/-LZ522mxXMw
-
+    - You could only use openlane:rc5
+    - Make sure you have the commit hashes provided here inside the [Makefile](./Makefile)
 ## Aboard Caravel:
 
 Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper. For example, if your design is analog or you're using a different tool other than OpenLANE.
@@ -80,6 +81,20 @@
 
 This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect hundred of thousands of magic DRC violations with the current "development" state of caravel.
 
+## Required Directory Structure
+
+- ./gds/ : includes all the gds files used or produced from the project.
+- ./def/ : includes all the def files used or produced from the project.
+- ./lef/ : includes all the lef files used or produced from the project.
+- ./mag/ : includes all the mag files used or produced from the project.
+- ./maglef/ : includes all the maglef files used or produced from the project.
+- ./spi/lvs/ : includes all the maglef files used or produced from the project.
+- ./verilog/dv/ : includes all the simulation test benches and how to run them. 
+- ./verilog/gl/ : includes all the synthesized/elaborated netlists. 
+- ./verilog/rtl/ : includes all the Verilog RTLs and source files.
+- ./openlane/`<macro>`/ : includes all configuration files used to run openlane on your project.
+- info.yaml: includes all the info required in [this example](info.yaml). Please make sure that you are pointing to an elaborated caravel netlist as well as a synthesized gate-level-netlist for the user_project_wrapper
+
 ## Managment SoC
 The managment SoC runs firmware that can be used to:
 - Configure User Project I/O pads
diff --git a/openlane/Makefile b/openlane/Makefile
index 8d2e712..44e9415 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -47,7 +47,7 @@
 	@echo "Please export OPENLANE_ROOT"
 	@exit 1
 endif
-	git clone https://github.com/efabless/openlane.git --branch=develop $(OPENLANE_ROOT) && \
+	git clone https://github.com/efabless/openlane.git --branch=master $(OPENLANE_ROOT) && \
 		cd $(OPENLANE_ROOT) && \
 		make openlane
 
diff --git a/openlane/README.md b/openlane/README.md
index 9218d7d..82381e9 100644
--- a/openlane/README.md
+++ b/openlane/README.md
@@ -10,16 +10,16 @@
 
 **NOTE:** rc5 and caravel are still WIP so expect to run into some issues when using it.
 
-If you don't have openlane already, then you can get it from [here](https://github.com/efabless/openlane) and checkout out to `develop` branch. Alternatively, you can clone and build the openlane develop branch through:
+If you don't have openlane already, then you can get it from [here](https://github.com/efabless/openlane) and checkout out to `rc5` tag. Alternatively, you can clone and build openlane through:
 ```bash
     make openlane
 ```
 
-**NOTE:** We are developing caravel using openlane:rc5 which is the current develop branch. openlane:rc5 will be merged to master once the caravel chip is finalized.
+**NOTE:** We are developing caravel using openlane:rc5 which is the current master branch.
 
-**NOTE:** rc5 (current openlane develop) and rc4 (current openlane master) are using two different concepts of cell padding. rc4 is modifying the LEF, while rc5 is relying on openroad to handle the cell padding. Also, rc4 is using the standalone version of openDP while rc5 is using the one integrated in the openroad app. This affects the concept of PL_TARGET_DENSITY and while in rc4 it was preferred to have PL_TARGET_DENSITY=(FP_CORE_UTIL-(5\~10)/100). Now, in rc5 it is preferred to be  PL_TARGET_DENSITY=(FP_CORE_UTIL+(1\~5)/100).
+**NOTE:** rc5 (current openlane master) and rc4 (previous openlane master) are using two different concepts of cell padding. rc4 is modifying the LEF, while rc5 is relying on openroad to handle the cell padding. Also, rc4 is using the standalone version of openDP while rc5 is using the one integrated in the openroad app. This affects the concept of PL_TARGET_DENSITY and while in rc4 it was preferred to have PL_TARGET_DENSITY=(FP_CORE_UTIL-(5\~10)/100). Now, in rc5 it is preferred to be  PL_TARGET_DENSITY=(FP_CORE_UTIL+(1\~5)/100).
 FP_CORE_UTIL should be relaxed as well as it became more representative of the actual core utilization, which wasn't so much the case earlier. So, the perception of these two variables as well as CELL_PAD changed between rc4 and rc5 which necessitates a change in the configurations of almost every single design.
-CELL_PAD should be 4~6 for the skywater libraries in rc5 unlike rc4 which was 8.This will be included in the release notes when rc5 is released as well as the openlane wiki.
+CELL_PAD should be 4~6 for the skywater libraries in rc5 unlike rc4 which was 8.
 
 Then, you have two options:
 1. Create a macro for your design and harden it, then insert it into user_project_wrapper.
@@ -57,7 +57,7 @@
 
 Then, follow the instructions given in Option 2.
 
-**NOTE:** You might have other macros inside your design. In which case, you may need to have some special power configurations. This is covered [here](https://github.com/efabless/openlane/blob/develop/doc/hardening_macros.md#power-grid-pdn).
+**NOTE:** You might have other macros inside your design. In which case, you may need to have some special power configurations. This is covered [here](https://github.com/efabless/openlane/blob/master/doc/hardening_macros.md#power-grid-pdn).
 
 ## Option 2:
 
@@ -83,18 +83,25 @@
 ```
 **NOTE:** Don't change the size or the pin order!
 
-3. Remove this line `add_macro_placement mprj 1150 1700 N` from the interactive script [here](./user_project_wrapper/config.tcl) and replace it with the placement for your macro instances. Or, remove it entirely if you have no macros, along with this line `manual_macro_placement f`.
+3. If your design has standard cells then you need to replace `verilog_elaborate` with `run_synthesis` [here](./user_project_wrapper/interactive.tcl).
 
-4. Run your design through the flow: `make user_project_wrapper`
+4. If your design has standard cells then you need to replace `init_floorplan; place_io_ol;` with `run_floorplan` [here](./user_project_wrapper/interactive.tcl).
+ 
+5. If your design has standard cells then add `run_placement` after `manual_macro_placement f` [here](./user_project_wrapper/interactive.tcl).
 
-5. Re-iterate until you have what you want.
+6. Remove this line `add_macro_placement mprj 1150 1700 N` from the interactive script [here](./user_project_wrapper/interactive.tcl) and replace it with the placement for your macro instances. Or, remove it entirely if you have no macros, along with this line `manual_macro_placement f`.
 
-6. Go back to the main [README.md](../README.md) and continue the process of boarding the chip.
+7. Run your design through the flow: `make user_project_wrapper`
 
-**NOTE:** In both cases you might have other macros inside your design. In which case, you may need to have some special power configurations. This is covered [here](https://github.com/efabless/openlane/blob/develop/doc/hardening_macros.md#power-grid-pdn).
+8. You may want to take a look at the [Extra Pointers](#extra-pointers) to apply any necessary changes to the interactive script.
 
-## Extra Pointers:
+8. Re-iterate until you have what you want.
 
+9. Go back to the main [README.md](../README.md) and continue the process of boarding the chip.
+
+**NOTE:** In both cases you might have other macros inside your design. In which case, you may need to have some special power configurations. This is covered [here](https://github.com/efabless/openlane/blob/master/doc/hardening_macros.md#power-grid-pdn).
+
+## Extra Pointers
 
 - The OpenLANE documentation should cover everything you might need to create your design. You can find that [here](https://github.com/efabless/openlane/blob/master/README.md).
 - The OpenLANE [FAQs](https://github.com/efabless/openlane/wiki) can guide through your troubles.
@@ -102,4 +109,4 @@
 - [Here](https://github.com/efabless/openlane/blob/master/doc/advanced_readme.md) you can learn how to write an interactive script.
 - [Here](https://github.com/efabless/openlane/blob/master/doc/OpenLANE_commands.md) you can find a full documentation for all OpenLANE commands.
 - [This documentation](https://github.com/efabless/openlane/blob/master/regression_results/README.md) describes how to use the exploration script to achieve an LVS/DRC clean design.
-- [This documentation](https://github.com/efabless/openlane/blob/develop/doc/hardening_macros.md) walks you through hardening a macro and all the decisions you should make.
+- [This documentation](https://github.com/efabless/openlane/blob/master/doc/hardening_macros.md) walks you through hardening a macro and all the decisions you should make.