)]}'
{
  "commit": "94dabb8582f4760d43d328fb676ba74dcfa1c08c",
  "tree": "3c5cb16a0e328c8b1522a232e792c39c6d3b4fb8",
  "parents": [
    "9c7e77248481168fb8364ef2e1a76a095d213a5c"
  ],
  "author": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Mon Dec 14 19:02:22 2020 +0200"
  },
  "committer": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Mon Dec 14 19:02:22 2020 +0200"
  },
  "message": "Fix the driver of the user2_vcc_powergood signal\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8cb927f2588b98cb63f430b11f6e9c443dcde770",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_protect.v",
      "new_id": "25e0b8ea6ba31a288c0959185cd5ddbfbf919434",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_protect.v"
    }
  ]
}