)]}'
{
  "commit": "589a528c7eec14294621d99747bb0850dcfae114",
  "tree": "64a4cc6b3d0f53e1ccfdff6560449668d7b995fc",
  "parents": [
    "ea96b3a6c6fa5e4c7236be9292cda5f9774c128f"
  ],
  "author": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Sat Dec 05 01:06:48 2020 +0200"
  },
  "committer": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Sat Dec 05 01:06:48 2020 +0200"
  },
  "message": "RTL updates to fix gl sim\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "51d65298ea63a6b36f5d039ee70544026726ff95",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "08a6241f949c5054cde2795353c1c73806c1d668",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "a72f0c8eabb519443b01e4f703649d74996c8732",
      "old_mode": 33188,
      "old_path": "verilog/rtl/defines.v",
      "new_id": "b9df2bd4952c249e7f01322c69e0a6bdec2ccac7",
      "new_mode": 33188,
      "new_path": "verilog/rtl/defines.v"
    },
    {
      "type": "modify",
      "old_id": "8ccdfddee0a8c993877dab6250428dbf60c7bac8",
      "old_mode": 33188,
      "old_path": "verilog/rtl/gpio_control_block.v",
      "new_id": "9f9ac7a612cd600160ba25e8a56aac6be7aec093",
      "new_mode": 33188,
      "new_path": "verilog/rtl/gpio_control_block.v"
    },
    {
      "type": "modify",
      "old_id": "f6e920372146ea43a9ebe3a9568f18d1807fe3b6",
      "old_mode": 33188,
      "old_path": "verilog/rtl/picorv32.v",
      "new_id": "17969b5b8b54079efb6d6a1c3d1edf0b1c227938",
      "new_mode": 33188,
      "new_path": "verilog/rtl/picorv32.v"
    }
  ]
}