tree 97b8b3cc0068976dbcb200285b14717f2639e197
parent f48448d4736bd6d56fed4dbf7f9cc50552d8745d
author Alex Underwood <alexander.underwood@okstate.edu> 1608076329 -0600
committer Alex Underwood <alexander.underwood@okstate.edu> 1608076329 -0600

Add the final caravel GDS that contains a RISC-V core

The GDS located at gds/caravel.gds has the single-cycle OSU RISC-V core
implemented inside of it.  The RISC-V core is located in
gds/user_project_wrapper.gds and the black-box verilog is in
verilog/gl/user_project_wrapper.gds.