)]}'
{
  "commit": "55c781d97d503c89e9e804c018992f673469f4f9",
  "tree": "97b8b3cc0068976dbcb200285b14717f2639e197",
  "parents": [
    "f48448d4736bd6d56fed4dbf7f9cc50552d8745d"
  ],
  "author": {
    "name": "Alex Underwood",
    "email": "alexander.underwood@okstate.edu",
    "time": "Tue Dec 15 17:52:09 2020 -0600"
  },
  "committer": {
    "name": "Alex Underwood",
    "email": "alexander.underwood@okstate.edu",
    "time": "Tue Dec 15 17:52:09 2020 -0600"
  },
  "message": "Add the final caravel GDS that contains a RISC-V core\n\nThe GDS located at gds/caravel.gds has the single-cycle OSU RISC-V core\nimplemented inside of it.  The RISC-V core is located in\ngds/user_project_wrapper.gds and the black-box verilog is in\nverilog/gl/user_project_wrapper.gds.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d729e240f4d7039ed85d599965ebf90bd73bcbe8",
      "old_mode": 33188,
      "old_path": "gds/caravel.gds.gz",
      "new_id": "e4884dcd7ab1310b56156bc4b56dfe09aa4fa6bc",
      "new_mode": 33188,
      "new_path": "gds/caravel.gds.gz"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "1d32c6cb326fd5903b2def57ab498f921fa34daf",
      "new_mode": 33188,
      "new_path": "gds/caravel.mag"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "d729e240f4d7039ed85d599965ebf90bd73bcbe8",
      "new_mode": 33188,
      "new_path": "gds/caravel.old.gds.gz"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "gds/user_project_wrapper.gds.gz",
      "new_id": "fda57af957cdddeae44993a1d151d8dc80fd5112",
      "new_mode": 33188,
      "new_path": "gds/user_project_wrapper.gds.gz"
    },
    {
      "type": "modify",
      "old_id": "158d5da18eaf5f0156001ddbbcbd6d4209dff121",
      "old_mode": 33188,
      "old_path": "lef/user_project_wrapper.lef",
      "new_id": "1d95c20c3e8d90abefa6a29fc438ded1f4bef9c8",
      "new_mode": 33188,
      "new_path": "lef/user_project_wrapper.lef"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "verilog/gl/user_project_wrapper.v",
      "new_id": "cf8a65f544a474ad4f8e9eb8e6b0949f8c4cb3cf",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_project_wrapper.v"
    }
  ]
}