)]}'
{
  "commit": "c752431b89db399edff09e826d67ddca73c0db5f",
  "tree": "def6fffecc7bda7f9538f1430f44b64eb6e70c3c",
  "parents": [
    "c4b44ece687c33b21597ff003ea38ab2f14da328"
  ],
  "author": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Mon Dec 07 18:13:54 2020 +0200"
  },
  "committer": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Mon Dec 07 18:13:54 2020 +0200"
  },
  "message": "Added more macros under GL\n\n- updated chip_io.v GL\n- renamed user_id_programming power ports to match the GL\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b6b5e7063d7acb316c09fa42d1ecd0ec78e05544",
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      "old_path": "verilog/gl/chip_io.v",
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      "new_mode": 33188,
      "new_path": "verilog/gl/chip_io.v"
    },
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      "new_path": "verilog/rtl/caravel.v"
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}