diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index b55ec62..675a873 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -72,6 +72,7 @@
 
     inout gpio,			// Used for external LDO control
     inout [`MPRJ_IO_PADS-1:0] mprj_io,
+    output [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
     input clock,	    	// CMOS core clock input, not a crystal
     input resetb,
 
@@ -367,6 +368,7 @@
 		.mprj_io_loader_data(mprj_io_loader_data),
 		.mgmt_in_data(mgmt_io_in),
 		.mgmt_out_data({mgmt_io_in[(`MPRJ_IO_PADS-1):2], mgmt_io_nc2}),
+		.pwr_ctrl_out(pwr_ctrl_out),
 		.sdo_out(sdo_out),
 		.sdo_outenb(sdo_outenb),
 		.jtag_out(jtag_out),
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index 4db3ada..38a4238 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -45,6 +45,7 @@
 	// User Project Control Signals
 	input [MPRJ_IO_PADS-1:0] mgmt_in_data,
 	output [MPRJ_IO_PADS-1:0] mgmt_out_data,
+	output [MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
 	input mprj_vcc_pwrgood,
 	input mprj2_vcc_pwrgood,
 	input mprj_vdd_pwrgood,
@@ -209,6 +210,7 @@
 		// I/O data
 		.mgmt_in_data(mgmt_in_data),
 		.mgmt_out_data(mgmt_out_data),
+		.pwr_ctrl_out(pwr_ctrl_out),
 		// User Project Slave ports (WB MI A)
 		.mprj_cyc_o(mprj_cyc_o),
 		.mprj_stb_o(mprj_stb_o),
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index f92fa36..478b9ee 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -83,6 +83,7 @@
     // User Project pad data (when management SoC controls the pad)
     input [MPRJ_IO_PADS-1:0] mgmt_in_data,
     output [MPRJ_IO_PADS-1:0] mgmt_out_data,
+    output [MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
 
     // IRQ
     input  irq_spi,		// IRQ from standalone SPI
@@ -699,7 +700,8 @@
 	.sdo_oenb_state(sdo_oenb_state),
 	.jtag_oenb_state(jtag_oenb_state),
 	.mgmt_gpio_out(mgmt_out_pre),
-	.mgmt_gpio_in(mgmt_in_data)
+	.mgmt_gpio_in(mgmt_in_data),
+	.pwr_ctrl_out(pwr_ctrl_out)
     );
 
     // Wishbone Slave RAM
diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v
index 60ca974..e0a4683 100644
--- a/verilog/rtl/mprj_ctrl.v
+++ b/verilog/rtl/mprj_ctrl.v
@@ -1,10 +1,11 @@
 module mprj_ctrl_wb #(
-    parameter BASE_ADR = 32'h 2300_0000,
-    parameter DATA   = 8'h 00,
-    parameter XFER   = 8'h 04,
-    parameter CONFIG = 8'h 08,
-    parameter IO_PADS = 32,   // Number of IO control registers
-    parameter PWR_PADS = 32  // Number of power control registers
+    parameter BASE_ADR  = 32'h 2300_0000,
+    parameter XFER      = 8'h 00,
+    parameter PWRDATA   = 8'h 04,
+    parameter IODATA    = 8'h 08, // One word per 32 IOs
+    parameter IOCONFIG  = 8'h 20,
+    parameter IO_PADS   = 32,     // Number of IO control registers (may be > 32)
+    parameter PWR_PADS  = 32  	  // Number of power control registers (always < 32)
 )(
     input wb_clk_i,
     input wb_rst_i,
@@ -31,7 +32,10 @@
 
     // Read/write data to each GPIO pad from management SoC
     input [IO_PADS-1:0] mgmt_gpio_in,
-    output [IO_PADS-1:0] mgmt_gpio_out
+    output [IO_PADS-1:0] mgmt_gpio_out,
+
+    // Write data to power controls
+    output [PWR_PADS-1:0] pwr_ctrl_out
 );
     wire resetn;
     wire valid;
@@ -46,9 +50,10 @@
 
     mprj_ctrl #(
         .BASE_ADR(BASE_ADR),
-	.DATA(DATA),
-        .CONFIG(CONFIG),
         .XFER(XFER),
+	.PWRDATA(PWRDATA),
+	.IODATA(IODATA),
+        .IOCONFIG(IOCONFIG),
 	.IO_PADS(IO_PADS),
         .PWR_PADS(PWR_PADS)
     ) mprj_ctrl (
@@ -74,14 +79,14 @@
 endmodule
 
 module mprj_ctrl #(
-    parameter BASE_ADR = 32'h 2300_0000,
-    parameter DATA   = 8'h 00,
-    parameter XFER   = 8'h 04,
-    parameter CONFIG = 8'h 08,
-    parameter IO_PADS = 32,
-    parameter PWR_PADS = 32,
-    parameter IO_CTRL_BITS = 13,
-    parameter PWR_CTRL_BITS = 1
+    parameter BASE_ADR  = 32'h 2300_0000,
+    parameter XFER      = 8'h 00,
+    parameter PWRDATA   = 8'h 04,
+    parameter IODATA    = 8'h 08,
+    parameter IOCONFIG  = 8'h 20,
+    parameter IO_PADS   = 32,
+    parameter PWR_PADS  = 32,
+    parameter IO_CTRL_BITS = 13
 )(
     input clk,
     input resetn,
@@ -108,24 +113,23 @@
 `define LOAD	2'b11
 
     localparam IO_WORDS = (IO_PADS % 32 != 0) + (IO_PADS / 32);
-    localparam PWR_WORDS = (PWR_PADS % 32 != 0) + (PWR_PADS / 32);
 
-    localparam IO_BASE_ADR = (BASE_ADR | CONFIG) + ((IO_WORDS + PWR_WORDS - 2) * 4);
-    localparam PWR_BASE_ADR = IO_BASE_ADR + (IO_PADS * 4);
+    localparam IO_BASE_ADR = (BASE_ADR | IOCONFIG);
+
     localparam OEB = 1;			// Offset of output enable in shift register.
     localparam INP_DIS = 3;		// Offset of input disable in shift register. 
-    localparam XFER_ADJ = XFER + ((IO_WORDS + PWR_WORDS - 2) * 4);
 
-    reg [IO_CTRL_BITS-1:0] io_ctrl[IO_PADS-1:0];  // I/O control, 1 word per gpio pad
-    reg [PWR_CTRL_BITS-1:0] pwr_ctrl[PWR_PADS-1:0]; // Power control, 1 word per power pad
-    reg [IO_PADS-1:0] mgmt_gpio_outr; // I/O write data, 1 bit per gpio pad
+    reg  [IO_CTRL_BITS-1:0] io_ctrl[IO_PADS-1:0];  // I/O control, 1 word per gpio pad
+    reg  [IO_PADS-1:0] mgmt_gpio_outr; 	 // I/O write data, 1 bit per gpio pad
     wire [IO_PADS-1:0] mgmt_gpio_out;	 // I/O write data output when input disabled
-    reg xfer_ctrl;			// Transfer control (1 bit)
+    reg  [PWR_PADS-1:0] pwr_ctrl_out;	 // Power write data, 1 bit per power pad
+    reg xfer_ctrl;			 // Transfer control (1 bit)
 
     wire [IO_WORDS-1:0] io_data_sel;	// wishbone selects
+    wire pwr_data_sel;
     wire xfer_sel;
     wire [IO_PADS-1:0] io_ctrl_sel;
-    wire [PWR_PADS-1:0] pwr_ctrl_sel;
+
     wire [IO_PADS-1:0] mgmt_gpio_in;
 
     wire sdo_oenb_state, jtag_oenb_state;
@@ -138,17 +142,16 @@
     assign jtag_oenb_state = io_ctrl[0][OEB];
     assign sdo_oenb_state = io_ctrl[1][OEB];
 
-    assign xfer_sel = (iomem_addr[7:0] == XFER_ADJ);
+    assign xfer_sel = (iomem_addr[7:0] == XFER);
+    assign pwr_data_sel = (iomem_addr[7:0] == PWRDATA);
 
     genvar i;
 
     generate
         for (i=0; i<IO_WORDS; i=i+1) begin
-    	    assign io_data_sel[i] = (iomem_addr[7:0] == (DATA + i*4)); 
+    	    assign io_data_sel[i] = (iomem_addr[7:0] == (IODATA + i*4)); 
 	end
-    endgenerate
 
-    generate
         for (i=0; i<IO_PADS; i=i+1) begin
             assign io_ctrl_sel[i] = (iomem_addr[7:0] == (IO_BASE_ADR[7:0] + i*4)); 
     	    assign mgmt_gpio_out[i] = (io_ctrl[i][INP_DIS] == 1'b1) ?
@@ -156,17 +159,12 @@
         end
     endgenerate
 
-    generate
-        for (i=0; i<PWR_PADS; i=i+1) begin
-            assign pwr_ctrl_sel[i] = (iomem_addr[7:0] == (PWR_BASE_ADR[7:0] + i*4)); 
-        end
-    endgenerate
-
-    // I/O transfer of xfer bit.  Also handles iomem_ready signal.
+    // I/O transfer of xfer bit.  Also handles iomem_ready signal and power data.
 
     always @(posedge clk) begin
 	if (!resetn) begin
 	    xfer_ctrl <= 0;
+            pwr_ctrl_out <= 0;
 	end else begin
 	    iomem_ready <= 0;
 	    if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
@@ -175,6 +173,9 @@
 		if (xfer_sel) begin
 		    iomem_rdata <= {31'd0, busy};
 		    if (iomem_wstrb[0]) xfer_ctrl <= iomem_wdata[0];
+		end else if (pwr_data_sel) begin
+                    iomem_rdata <= pwr_ctrl_out;
+                    if (iomem_wstrb[0]) pwr_ctrl_out <= iomem_wdata[PWR_PADS-1:0];
 		end
 	    end else begin
 		xfer_ctrl <= 1'b0;	// Immediately self-resetting
@@ -198,7 +199,7 @@
 		    if (iomem_valid && !iomem_ready && iomem_addr[31:8] ==
 					BASE_ADR[31:8]) begin
 			if (io_data_sel[i]) begin
-			    iomem_rdata[`rtop:0] <= mgmt_gpio_in[`wtop:`wbot];
+			    iomem_rdata <= mgmt_gpio_in[`wtop:`wbot];
 			    if (iomem_wstrb[0]) begin
 				mgmt_gpio_outr[`wtop:`wbot] <= iomem_wdata[`rtop:0];
 			    end
@@ -207,9 +208,7 @@
 		end
 	    end
 	end
-    endgenerate
 
-    generate 
         for (i=0; i<IO_PADS; i=i+1) begin
              always @(posedge clk) begin
                 if (!resetn) begin
@@ -222,7 +221,8 @@
                     	io_ctrl[i] <= 'h0403;
 		    end
                 end else begin
-                    if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
+                    if (iomem_valid && !iomem_ready &&
+					iomem_addr[31:8] == BASE_ADR[31:8]) begin
                         if (io_ctrl_sel[i]) begin
                             iomem_rdata <= io_ctrl[i];
 			    // NOTE:  Byte-wide write to io_ctrl is prohibited
@@ -235,24 +235,6 @@
         end
     endgenerate
 
-    generate 
-        for (i=0; i<PWR_PADS; i=i+1) begin
-             always @(posedge clk) begin
-                if (!resetn) begin
-                    pwr_ctrl[i] <= 'd0;
-                end else begin
-                    if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
-                        if (pwr_ctrl_sel[i]) begin
-                            iomem_rdata <= pwr_ctrl[i];
-                            if (iomem_wstrb[0])
-				pwr_ctrl[i] <= iomem_wdata[PWR_CTRL_BITS-1:0];
-                        end 
-                    end
-                end
-            end
-        end
-    endgenerate
-
     reg [3:0]  xfer_count;
     reg [5:0]  pad_count;
     reg [1:0]  xfer_state;