diff --git a/verilog/rtl/DFFRAM.v b/verilog/rtl/DFFRAM.v
index 55a03a2..b80677f 100644
--- a/verilog/rtl/DFFRAM.v
+++ b/verilog/rtl/DFFRAM.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/DFFRAMBB.v b/verilog/rtl/DFFRAMBB.v
index defb258..22ab55e 100644
--- a/verilog/rtl/DFFRAMBB.v
+++ b/verilog/rtl/DFFRAMBB.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 2ee50bc..430b2f5 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -1,4 +1,18 @@
 // `default_nettype none
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
 /*--------------------------------------------------------------*/
 /* caravel, a project harness for the Google/SkyWater sky130	*/
 /* fabrication process and open source PDK			*/
diff --git a/verilog/rtl/caravel_clocking.v b/verilog/rtl/caravel_clocking.v
index 0235f19..cc0af25 100644
--- a/verilog/rtl/caravel_clocking.v
+++ b/verilog/rtl/caravel_clocking.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index d45af63..850549f 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/clock_div.v b/verilog/rtl/clock_div.v
index 8535243..49ff44b 100644
--- a/verilog/rtl/clock_div.v
+++ b/verilog/rtl/clock_div.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/convert_gpio_sigs.v b/verilog/rtl/convert_gpio_sigs.v
index b197c7d..e9e8351 100644
--- a/verilog/rtl/convert_gpio_sigs.v
+++ b/verilog/rtl/convert_gpio_sigs.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/counter_timer_high.v b/verilog/rtl/counter_timer_high.v
index 235e740..ea946f0 100755
--- a/verilog/rtl/counter_timer_high.v
+++ b/verilog/rtl/counter_timer_high.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/counter_timer_low.v b/verilog/rtl/counter_timer_low.v
index 074fab4..c543a6b 100755
--- a/verilog/rtl/counter_timer_low.v
+++ b/verilog/rtl/counter_timer_low.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index 508ef4e..3c9e595 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index 3458349..b8dd69e 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/digital_pll_controller.v b/verilog/rtl/digital_pll_controller.v
index 3b745c7..ae13d9d 100644
--- a/verilog/rtl/digital_pll_controller.v
+++ b/verilog/rtl/digital_pll_controller.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
index f4a92bb..8c4ef3f 100644
--- a/verilog/rtl/gpio_control_block.v
+++ b/verilog/rtl/gpio_control_block.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/gpio_wb.v b/verilog/rtl/gpio_wb.v
index bcd4a22..9941fc9 100644
--- a/verilog/rtl/gpio_wb.v
+++ b/verilog/rtl/gpio_wb.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/housekeeping_spi.v b/verilog/rtl/housekeeping_spi.v
index c4bb78e..37c27c8 100644
--- a/verilog/rtl/housekeeping_spi.v
+++ b/verilog/rtl/housekeeping_spi.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/la_wb.v b/verilog/rtl/la_wb.v
index cec862f..79a88a9 100644
--- a/verilog/rtl/la_wb.v
+++ b/verilog/rtl/la_wb.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/manifest b/verilog/rtl/manifest
index aac1940..7f78a51 100644
--- a/verilog/rtl/manifest
+++ b/verilog/rtl/manifest
@@ -1,35 +1,35 @@
-5e7d349fbdee30deee644794d8a02d9593145a6d  DFFRAM.v
-4af9b0f1f6d62aae4baeb6fc724fabc55f6b2581  DFFRAMBB.v
-7f2e64ff567d4a745aaae296db34294f5bbeb7f6  caravel.v
-b3a1f70e7ab737ebf8a0f8cc8bbd0099c50202d6  caravel_clocking.v
-9c4e56984c2564c8f84a0459553603ccb3ab0fd1  chip_io.v
-e01ff27f67d783ce12055c5b671256191a19c1b0  clock_div.v
-6af4e004999895d4ed75bf21d98a036ee3d44de5  convert_gpio_sigs.v
-9ce78d01ef2ba2524579cebc051e2eb9af18490e  counter_timer_high.v
-b7db20cf99e550da9c3d0fff9ad8f883fa48fb9b  counter_timer_low.v
-95473b2e0a30c0a799a76461800b5aba05a9845f  digital_pll.v
-b60c3bfa314ee7692a27e4e3695bc064cc69ee80  digital_pll_controller.v
-42dfa028e34bc9f41716ac06b55d34ed440fd926  gpio_control_block.v
-7acbb524393d1815f5d514b862b541f5e1282602  gpio_wb.v
-c251fda11936adc99cf525735d42e82223e56a11  housekeeping_spi.v
-21b1fe5035e01bf3c48341d2c13dc8a2c2871270  la_wb.v
-2c4eb3c797a5187893de9427878b293ab1e08372  mem_wb.v
-6cdfa07a1d17385ab35a0e5a4741c06155c03545  mgmt_core.v
-cb46861ca14c029c86b632ac0e95799e2f816b5d  mgmt_protect.v
-52e35a959d251644bb7a978d50f73b8d6104bb19  mgmt_protect_hv.v
+d328f88dd48e015bbaa95e0d7c88954343cc5632  DFFRAM.v
+dab57f3c5464ce3354219840dae589a3fcd27135  DFFRAMBB.v
+8a0bcbd870778416bb4e753909053881aca2368a  caravel.v
+b2feeb2a098894d5d731a5b011858a471e855d73  caravel_clocking.v
+38d2c674ea1f696bf2c9deaeee5f9b044f2445fb  chip_io.v
+d772308bd2a72121d7ed9dcdd40c8e6cbbe4b43c  clock_div.v
+f937b52e53d45bdbe41bcbd07c65b41104c21756  convert_gpio_sigs.v
+a16f89c8efa638eab43641ab7047bb8eeedd6fa6  counter_timer_high.v
+d8eab2f4cef158e3c7800778ffc2367ab4abe130  counter_timer_low.v
+fff2d08e49701312c2ebd6714b7425baf83f3d35  digital_pll.v
+ce49f9af199b5f16d2c39c417d58e5890bc7bab2  digital_pll_controller.v
+e6902f7a9958eab32b8904c6f7e2d3c81be7766a  gpio_control_block.v
+57554b3586f306944b31718a8c52526fa9a8a574  gpio_wb.v
+baf3aba29655ca7021398ddc3f68be81eff0fa0c  housekeeping_spi.v
+0544035d9f2bfc52ebcb3220a21f29e98a3784b4  la_wb.v
+ff3e65a783f3807340e25efac9207787d39fb6cd  mem_wb.v
+65feb79043201d3609307a3dd5af4e75cc26e81b  mgmt_core.v
+85dec445f0cf7afbef4aa6b919d31f0f5c9a0b7e  mgmt_protect.v
+f656dadb49cb97a46aada3d37a86a12f565e6e9e  mgmt_protect_hv.v
 20a482029168de93693a92ce03c00ec16e7b4776  mgmt_soc.v
-6d035b3ded00c1a279777598e3dd0d322be7a22a  mprj_ctrl.v
-8ede54ebe106e987d01aaaed59b0197ac6769b4f  mprj_io.v
-73ce18edaee6a019c537c7d0cfcaff72907886e1  pads.v
+93eb7aa0f8489715145ff0870737fecf8be1fa8c  mprj_ctrl.v
+b16ace2e7a9c02ed5f8f918fe9e4a460422c7304  mprj_io.v
+1352e5821905dce0b8203e9bee5e1adff02a9cbc  pads.v
 5f1d9a90287fa5ae6635933c287e8e9e3e39931a  picorv32.v
-c908a6ea89bd9cf78529b45db185f8963cb360a8  ring_osc2x13.v
-bbf4be77ad33b22e14b9532964c119981d781e3c  simple_por.v
-293f678d44b30abfab6c6a065828c916f05fd917  simple_spi_master.v
+669d16642d5dd5f6824812754db20db98c9fe17b  ring_osc2x13.v
+6864cc10dacfd3edb4c66825b7a301ab097cea0d  simple_por.v
+917aa6e1bb869f973c79fb2c7894eab882ead74c  simple_spi_master.v
 7a949db8a5665540e0125bfb7544852167e821b0  simpleuart.v
-c4f74b2b66f108ffeedb1f2ccbaa8df97f25a8ae  sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
+ec5fa62d935e1139de104b9201740020fdea4a17  sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
 b77b7eb6ae4b253abf157a01f6f349719a81628c  spimemio.v
-c4adcc886b2c2d1ebdd80b801c0c05d326b31d22  sram_1rw1r_32_256_8_sky130.v
-4514db10d3739a716ceaef87080cac7ee901fd44  storage.v
-2b07a0653c16f790d37a972a352383fd6d04558d  storage_bridge_wb.v
-b5714f36f90edb3e7ed5e58808eebb761b81af8e  sysctrl.v
-e0c25f0bffc166c0051227a8940ac30d718be8b0  wb_intercon.v
+3b4c3de623f8af0f0780f1e5b0f2217ef6406a2f  sram_1rw1r_32_256_8_sky130.v
+8dea2030f1f59fc58ce50d943c395b8041ff1fb3  storage.v
+7e8d789570ed224df49cf61f69593cc738790a5d  storage_bridge_wb.v
+5e314e94a13d7291117123395ae088e1d17cf487  sysctrl.v
+e6246df6bbf0860a331b3547d64f7d235b0eca9a  wb_intercon.v
diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index 10fe839..01bd2e1 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index f88155c..dff9c0f 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index 306de34..8cb927f 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/mgmt_protect_hv.v b/verilog/rtl/mgmt_protect_hv.v
index 99e4baf..c1ecd0b 100644
--- a/verilog/rtl/mgmt_protect_hv.v
+++ b/verilog/rtl/mgmt_protect_hv.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v
index c9648ab..d5c24bf 100644
--- a/verilog/rtl/mprj_ctrl.v
+++ b/verilog/rtl/mprj_ctrl.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v
index 16a49a7..8e7a669 100644
--- a/verilog/rtl/mprj_io.v
+++ b/verilog/rtl/mprj_io.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index 6813066..a523518 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/ring_osc2x13.v b/verilog/rtl/ring_osc2x13.v
index a96167f..f20110e 100644
--- a/verilog/rtl/ring_osc2x13.v
+++ b/verilog/rtl/ring_osc2x13.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index 04bbafe..8168c0b 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/simple_spi_master.v b/verilog/rtl/simple_spi_master.v
index 4576925..c319de8 100755
--- a/verilog/rtl/simple_spi_master.v
+++ b/verilog/rtl/simple_spi_master.v
@@ -1,4 +1,18 @@
 `default_nettype none
+// SPDX-FileCopyrightText: 2019 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
 //----------------------------------------------------------------------------
 // Module: simple_spi_master
 //
diff --git a/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v b/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
index 1ec81ef..a746169 100644
--- a/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
+++ b/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
index 5840f13..f622079 100644
--- a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
+++ b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/storage.v b/verilog/rtl/storage.v
index b519e0d..2efacb8 100644
--- a/verilog/rtl/storage.v
+++ b/verilog/rtl/storage.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/storage_bridge_wb.v b/verilog/rtl/storage_bridge_wb.v
index 23c81e2..0f24321 100644
--- a/verilog/rtl/storage_bridge_wb.v
+++ b/verilog/rtl/storage_bridge_wb.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/sysctrl.v b/verilog/rtl/sysctrl.v
index 8a694aa..c18979e 100644
--- a/verilog/rtl/sysctrl.v
+++ b/verilog/rtl/sysctrl.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
index 41fd248..873bbce 100644
--- a/verilog/rtl/user_id_programming.v
+++ b/verilog/rtl/user_id_programming.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index ec99e66..44e8eda 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 2e5b525..47d92f4 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
diff --git a/verilog/rtl/wb_intercon.v b/verilog/rtl/wb_intercon.v
index e008406..7ebce83 100644
--- a/verilog/rtl/wb_intercon.v
+++ b/verilog/rtl/wb_intercon.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.