)]}'
{
  "commit": "44bab477f9cce5e8229fbd63a16ad84b57663938",
  "tree": "7f48e6862ee2c465e479707de32f424544937b3e",
  "parents": [
    "61bfc1f4c75fbb9a2c915bcd539f7e01c5978a55"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sun Oct 04 22:09:54 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sun Oct 04 22:09:54 2020 -0400"
  },
  "message": "In spite of many errors that still need fixing, this is a major advance\nover the previous commit.  All verilog modules are in place more or less\nas intended, with various functions such as the housekeeping SPI placed\non user area pads, with the ability to switch to user control from the\nconfiguration.  The pad control bits are local to the pads and loaded\nvia serial shift register, so that there are not hundreds of control wires\nfeeding into the user space.  The user has three basic controls over each\npad:  in, out, and outenb.  Two timer/counters and an SPI master have been\nadded to the SoC.  The SPI master shares I/O with the housekeeping SPI, so\nthat all housekeeping SPI registers can be accessed from the SoC directly.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "68ef6b024f5b848b8557f2d6b9da967e5f562604",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/defs.h",
      "new_id": "559151d4a6ba112cbabea72d6f0c6e7053e93db1",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/defs.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "f1935ddd23a82bfe1189a8d369f618055ebe7416",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/README"
    },
    {
      "type": "modify",
      "old_id": "4dbacc68824cf8497d40d2f2d1543a1e43ae3161",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio.c",
      "new_id": "bd6a17c02776c6f842df70ac13feef6941327207",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio.c"
    },
    {
      "type": "modify",
      "old_id": "667a214098cfe84847b64608022b71f59e1b5700",
      "old_mode": 33261,
      "old_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio.hex",
      "new_id": "adcdbdd915b154167e4bc8c44ab76928eb72d5be",
      "new_mode": 33261,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio.hex"
    },
    {
      "type": "modify",
      "old_id": "f82373741eeff382e768d407cc3b915c37850f63",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v",
      "new_id": "56781da7b78100d75faf0ae2d8b3039f0dd8b8d9",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "ec44791391d4dded59e97e5a818331fb8edd0910",
      "new_mode": 33188,
      "new_path": "verilog/rtl/README"
    },
    {
      "type": "modify",
      "old_id": "abcbd8ad85103016f3d59a3a023ddb85e50f82a8",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "492712ebb6fb9493ae7b3bcc8b0cfccd4fbed1c4",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "delete",
      "old_id": "3abd22796b37603676a9bd1f6cf1eb6a021eee12",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel_spi.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "e8a6494a0e1b99e81dc16e336b21e71548921ca1",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel_spi_slave.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "modify",
      "old_id": "82df32dd61f67695ae118d992b7bcf700f6c124d",
      "old_mode": 33188,
      "old_path": "verilog/rtl/chip_io.v",
      "new_id": "dc46ebf1577ecac9358f7172161d78b9c7820145",
      "new_mode": 33188,
      "new_path": "verilog/rtl/chip_io.v"
    },
    {
      "type": "modify",
      "old_id": "157584106725552d3154e13028fe21a04a190633",
      "old_mode": 33188,
      "old_path": "verilog/rtl/gpio_control_block.v",
      "new_id": "2325b39ea1cc942c6a8f48ddb4cc30ebd299627c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/gpio_control_block.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "b28a02e80d9c2721c16a31f66820cc4478b8382c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/gpio_control_block2.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "97bd7a11c73c20e692814f7885962cd493947220",
      "new_mode": 33188,
      "new_path": "verilog/rtl/housekeeping_spi.v"
    },
    {
      "type": "modify",
      "old_id": "26e7e55585387e2e1ccd0b7c4853b084b82e9f46",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_core.v",
      "new_id": "bd520273748d3e97a4dba3493e78af071383783c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_core.v"
    },
    {
      "type": "modify",
      "old_id": "5162a9bb35967f8102b87ce9ea55f5ae41167d76",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_soc.v",
      "new_id": "ce43250d372ea910357272773e445c0be437747d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_soc.v"
    },
    {
      "type": "modify",
      "old_id": "8970c41cae96a9edb7d6f53f21d17536966eaa7f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mprj_ctrl.v",
      "new_id": "cb67ac44e50088677ae9a70d02992e0683068931",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mprj_ctrl.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "35fc3464343df5b940993d453dd7938cf4dd747c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mprj_ctrl.v.orig"
    },
    {
      "type": "modify",
      "old_id": "02386494969830d1021e7e5d210a03ef92886d7e",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mprj_io.v",
      "new_id": "32ae628fb2bf66cf445a57c0947e02adb17bfbd1",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mprj_io.v"
    },
    {
      "type": "modify",
      "old_id": "de6ac2af5ca77e902275f008f3c43fb1de6def22",
      "old_mode": 33261,
      "old_path": "verilog/rtl/simple_spi_master.v",
      "new_id": "dad5471f6e1c68ff717df0793bf0b341924110c8",
      "new_mode": 33261,
      "new_path": "verilog/rtl/simple_spi_master.v"
    },
    {
      "type": "modify",
      "old_id": "456c2d0400be471ea4c0318140708a23f58ff923",
      "old_mode": 33188,
      "old_path": "verilog/rtl/spimemio.v",
      "new_id": "2d0b6feb01c3d146546b9e6a1d494ea6f7e5addf",
      "new_mode": 33188,
      "new_path": "verilog/rtl/spimemio.v"
    },
    {
      "type": "modify",
      "old_id": "62ed4fc08110935c7a4d8e31ed3d24b78df1b6ff",
      "old_mode": 33188,
      "old_path": "verilog/rtl/sysctrl.v",
      "new_id": "86ec1e5be02b53ff19087844744a9546d6c59e08",
      "new_mode": 33188,
      "new_path": "verilog/rtl/sysctrl.v"
    }
  ]
}