FULL RUN LOG:
SPDX NON-COMPLIANT FILES
/usr/local/workspace/Caravel-SOFA-CHD/README.md
/usr/local/workspace/Caravel-SOFA-CHD/source_commit_hash.txt
/usr/local/workspace/Caravel-SOFA-CHD/doc/caravel_datasheet.ps
/usr/local/workspace/Caravel-SOFA-CHD/mag/clamp_list.txt
/usr/local/workspace/Caravel-SOFA-CHD/openlane/chip_dimensions.txt
/usr/local/workspace/Caravel-SOFA-CHD/openlane/mgmt_protect/pdn.tcl
/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/DFFRAM.spice
/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/chip_io.spice
/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/digital_pll.spice
/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/gpio_control_block.spice
/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/simple_por.spice
/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/storage.spice
/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/user_id_programming.spice
/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mgmt_core.spice
/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mgmt_protect.spice
/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mgmt_protect_hv.spice
/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mprj2_logic_high.spice
/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mprj_logic_high.spice
/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.spice
/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/user_proj_example.spice
/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/user_project_wrapper.spice
/usr/local/workspace/Caravel-SOFA-CHD/verilog/dv/caravel/sections.lds
/usr/local/workspace/Caravel-SOFA-CHD/verilog/dv/caravel/spiflash.v
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/usr/local/workspace/Caravel-SOFA-CHD/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/gl/caravel.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/gl/chip_io.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/gl/mgmt_protect.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/gl/mgmt_protect_hv.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/gl/mprj2_logic_high.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/gl/user_proj_example.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/gl/mprj_logic_high.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/gl/user_project_wrapper.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/gl/caravel_sofa_chd_top.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/rtl/mgmt_soc.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/rtl/picorv32.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/rtl/simpleuart.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/rtl/spimemio.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/rtl/mprj2_logic_high.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/rtl/mprj_logic_high.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/InstancesMap.txt
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/define_simulation.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/fabric_netlists.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/fpga_core.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/fpga_defines.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/fpga_top.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/top_include_netlists.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/lb/grid_clb.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_clb_.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/lb/logical_tile_io_mode_io_.v
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/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/routing/cbx_1__0_.v
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/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/routing/cby_0__1_.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/routing/cby_1__1_.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/routing/cby_2__1_.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/routing/sb_0__0_.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/routing/sb_0__1_.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/routing/sb_0__2_.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/routing/sb_1__0_.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/routing/sb_1__1_.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/routing/sb_1__2_.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/routing/sb_2__0_.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/routing/sb_2__1_.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/routing/sb_2__2_.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/arch_encoder.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/decoder2to4_post_synth.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/digital_io_hd.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/fd_hd_mux_custom_cells_tt.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/fpga_top.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/inv_buf_passgate.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/local_encoder1to1_post_synth.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/local_encoder1to2_post_synth.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/local_encoder2to3_post_synth.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/local_encoder2to4_post_synth.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/luts.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/memories.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/mux_primitives.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/muxes.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/sky130_fd_sc_hd_wrapper.v
/usr/local/workspace/Caravel-SOFA-CHD/verilog/OpenFPGA_Verilog/sub_module/wires.v
/usr/local/workspace/Caravel-SOFA-CHD/checks/caravel.magic.typelist
/usr/local/workspace/Caravel-SOFA-CHD/checks/caravel.magic.namelist
/usr/local/workspace/Caravel-SOFA-CHD/checks/compare_caravel.txt
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/design_variables.yml
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/generate_fabric.openfpga
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/generate_testbench.openfpga
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/process_top_def.sh
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/arch/fabric_key.xml
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/arch/openfpga_arch.xml
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/arch/vpr_arch.xml
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/config/task.conf
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/config/task_generation.conf
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/config/task_simulation.conf
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/micro_benchmark/and.act
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/micro_benchmark/and.blif
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/micro_benchmark/and.v
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/sc_verilog/decoder2to4_post_synth.v
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/sc_verilog/digital_io_hd.v
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/sc_verilog/fd_hd_mux_custom_cells_tt.v
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/sc_verilog/fpga_top.v
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/sc_verilog/local_encoder1to1_post_synth.v
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/sc_verilog/local_encoder1to2_post_synth.v
/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/sc_verilog/local_encoder2to3_post_synth.v
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/usr/local/workspace/Caravel-SOFA-CHD/OpenFPGA_task/sc_verilog/sky130_fd_sc_hd_wrapper.v